TWI730247B - Semiconductor devices and methods of fabricating the same - Google Patents

Abstract

A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Description

Semiconductor device and manufacturing method thereof

The embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof, and particularly relates to a method of forming a via hole pre-made metal gate contact and its related structure.

The semiconductor industry has experienced an increasing demand for smaller and faster electronic devices, and electronic devices can simultaneously support a large number of increasingly complex and sophisticated functions. Therefore, the semiconductor industry continues to develop towards manufacturing low-cost, high-efficiency, and low-power integrated circuits. These ambitious goals have been largely achieved by reducing the size of semiconductor integrated circuits (such as the smallest component size), thereby improving production efficiency and reducing accompanying costs. However, this reduction also increases the complexity of the semiconductor manufacturing process. Therefore, the realization of continuous development in semiconductor integrated circuits and devices requires similar development in semiconductor manufacturing process and technology.

Just as an example, a reliable contact is formed to the metal gate layer and is located between the metal gate layer and the adjacent source, drain, and/or body regions, which requires a high degree of overlap control (such as pattern pairing). Pattern alignment) and sufficient process tolerance. However, with the continuous reduction in the size of integrated circuits and the connection with new patterning technologies (such as double patterning), accurate overlap control is more critical than ever. In addition, for a drastically reduced integrated circuit, The process tolerance becomes narrower, which may lead to device degradation and/or failure. For at least some conventional processes, for forming such contacts to the metal gate layer, and between the metal gate layer and the adjacent source, drain, and/or body regions, the semiconductor manufacturing process The process tolerance has become too narrow, and there is no way to meet the process tolerance requirements for longer.

Therefore, the existing technology cannot be completely satisfactory in all aspects.

In some embodiments, the method for manufacturing a semiconductor device includes depositing a first dielectric layer on a substrate, the substrate includes a gate structure having a metal gate layer; forming an opening in the first dielectric layer to expose adjacent Part of the base of the gate structure, and deposit a first metal layer in the opening; deposit a second dielectric layer on the first dielectric layer and on the first metal layer; etch the first dielectric layer and the second dielectric layer Electrical layer to form the opening of the gate via hole, which exposes the metal gate layer of the gate structure; remove a part of the second dielectric layer to form a contact opening, which exposes the first metal layer, wherein the gate conductive The opening of the hole and the contact opening are merged to form a composite opening; and a second metal layer is deposited in the composite opening, wherein the second metal layer is electrically connected to the metal of the gate structure through the gate via portion of the second metal layer The gate layer to the first metal layer.

In other embodiments, the manufacturing method of the semiconductor device includes forming a first metal layer adjacent to the sidewall of the gate structure, wherein the first metal layer contacts a region of the substrate below the first metal layer, and wherein the gate structure Including a metal gate; depositing a first dielectric layer on the substrate; etching the first dielectric layer in a region above the gate structure to form the opening of the gate via, wherein the opening of the gate via The metal gate of the gate structure is exposed; the one etched on the first metal layer The first dielectric layer in the region to form the opening of the contact via hole, wherein the opening of the contact via hole exposes the first metal layer; from a region between the opening of the gate via hole and the opening of the contact via hole Removing the first dielectric layer to form a contact opening, wherein the contact opening, the opening of the gate via hole and the opening of the contact via hole merge to form a composite opening; and forming a second metal layer in the composite opening, The metal gate of the gate structure is electrically connected to the first metal layer through the gate via hole portion of the second metal layer and the contact via hole portion.

In still other embodiments, the semiconductor device includes a substrate, and the gate structure included in the substrate has a metal gate; the first metal layer is adjacent to the sidewall spacer, and the sidewall spacer is disposed on the sidewall of the gate structure, wherein the first metal The layer is in contact with a region of the substrate below the first metal layer; and the dielectric layer is located on the substrate, the dielectric layer includes a composite opening filled with a second metal layer; wherein the second metal layer includes a gate via, which defines In the gate via part of the composite opening, the gate via contacts the metal gate, and the gate via is aligned with the metal gate; and the second metal layer contacts the first metal layer in the contact part of the composite opening.

100‧‧‧Transistor

102‧‧‧Base

104‧‧‧Gate Stack

106‧‧‧Gate Dielectric Layer

108‧‧‧Gate electrode layer

110‧‧‧Source area

112‧‧‧Dip pole area

114‧‧‧Access area

W‧‧‧Channel width

L‧‧‧Channel length

150‧‧‧FinFET device

152‧‧‧Base

154‧‧‧Fin element

155‧‧‧Source Region

156‧‧‧Isolation Area

157‧‧‧Dip pole area

158‧‧‧Gate structure

160‧‧‧Interface layer

162‧‧‧Gate Dielectric Layer

164‧‧‧Metal layer

200, 700, 1600‧‧‧Method

202, 204, 206, 208, 210, 702, 704, 706, 708, 710, 712, 714, 716, 1602, 1604, 1606, 1608, 1610, 1612, 1614, 1616‧‧‧block

800, 1700‧‧‧ device

802、1702‧‧‧Base

804, 806, 808, 1704, 1706, 1708‧‧‧Gate structure

810, 812, 1710, 1712‧‧‧ area

814、1714‧‧‧Metal gate layer

816, 818, 1716, 1718‧‧‧ sidewall spacer layer

820, 832, 1720, 1732‧‧‧Dielectric layer

822, 824, 1722, 1724‧‧‧ opening

826, 840, 1726, 1742‧‧‧Glue layer or barrier layer

828, 829, 842, 1728, 1729, 1744‧‧‧Metal layer

830、1730‧‧‧Contact etching stop layer

834, 1734‧‧‧ Gate openings

836、1738‧‧‧Contact opening

838、1740‧‧‧Composite opening

A, A’, B, B’, C, C’‧‧‧distance

Z‧‧‧ Increased distance

900、1800‧‧‧Layout design

914、1814‧‧‧Metal gate layer

928, 929, 942, 1828, 1829‧‧‧Metal layer

934、1834‧‧‧Gate via

1736‧‧‧The opening of the contact guide hole

1836‧‧‧Contact guide hole

In order to make the various aspects of the embodiments of the present invention easier to understand, detailed descriptions are given below in conjunction with the accompanying drawings. It should be noted that according to industry standard paradigms, various features are not necessarily drawn to scale. In fact, in order to make the discussion clear and easy to understand, the size of each component may be arbitrarily enlarged or reduced.

FIG. 1A is a cross-sectional view of a metal oxide semiconductor (MOS) transistor according to some embodiments.

FIG. 1B is a perspective view of an embodiment of a FinFET device according to one or more aspects of the embodiments of the present invention.

FIG. 2 is a flowchart of a method of forming direct contacts between a metal gate and adjacent source, drain, and/or body regions.

Figures 3 to 6 are cross-sectional views of the device in an intermediate stage of manufacturing and processing according to the method of Figure 2.

FIG. 7 is a flowchart of a method of forming a via hole pre-made metal gate contact according to some embodiments.

Figures 8 to 14 are cross-sectional views of the device in an intermediate stage of manufacturing and processing according to the method of Figure 7.

Figure 15 provides a layout design and illustrates various aspects of some embodiments of the present invention.

FIG. 16 is a flowchart of another method of forming a via hole pre-made metal gate contact according to some embodiments.

Figures 17 to 23 are cross-sectional views of the device at an intermediate stage of manufacturing and processing according to the method of Figure 16.

Figure 24 provides a layout design and illustrates various aspects of other embodiments of the present invention.

The following content provides many different embodiments or examples to realize different features of the provided subject matter. Specific examples of components and configuration methods are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, in the following description, it is mentioned that the first part is formed above or on the second part, which may include an embodiment in which the first part and the second part are formed in direct contact, and may also be included in the first part. An additional part is formed between the part and the second part, so that the first part and the second part An embodiment where the components may not be in direct contact. In addition, in the embodiments of the present invention, reference numerals and/or letters may be repeated in each example. This repetition is for the purpose of simplification and clarity, and is not used in itself to specify the relationship between the various embodiments and/or configurations discussed.

Furthermore, in order to easily describe the relationship between one element or component and another element or component in the figure, spatially related terms such as "below", "below", "Lower", "higher", "above", "above" and similar terms. These spatially related terms are intended to cover different directions of the device in use or operation in addition to the directions drawn in the illustration. The device can be positioned in other directions (rotated by 90 degrees or in other directions), and the space-related terms used in this description can be interpreted accordingly.

It should be noted that the embodiment of the present invention is described in the form of a via-first metal gate contact, but it can also be used in any type of device. For example, the embodiment of the present invention can be used to form metal-oxide-semiconductor field-effect transistors (MOSFETs) in which the metal gate contacts are formed in a planar block with via holes; Polar transistors (planar or vertical), such as FinFET devices, gate-all-around (GAA) devices, Ω-gate devices, or Π-gate devices; and strained semiconductor devices, silicon-on-insulator (SOI) devices, partially-depleted SOI devices, fully-depleted devices 1) Pre-made metal gate contacts with via holes formed in SOI devices or other known devices. In addition, the embodiments of the present invention may be used in the formation of P-type and/or N-type devices. This invention belongs to Those with ordinary knowledge in the technical field can understand that other embodiments of the semiconductor device can also benefit from various aspects of the embodiments of the present invention.

Referring to the example in FIG. 1A, a metal oxide semiconductor (MOS) transistor 100 is described here, which is only provided as an example of a device type that can include embodiments of the present invention. It can be understood that the exemplary transistor 100 is not limited to any form, and those with ordinary knowledge in the technical field of the present invention can understand that the embodiments of the present invention can be equally applied to any kind of other device types, such as those described above. Those devices. The transistor 100 is fabricated on a substrate 102 and includes a gate stack 104. The substrate 102 may be a semiconductor substrate, such as a silicon substrate. The substrate 102 may include various layers, including a conductive or insulating layer formed on the substrate 102. The substrate 102 may include various doping configurations, which depend on well-known design requirements. The substrate 102 may also include other semiconductor materials, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. In addition, the substrate 102 may include a compound semiconductor and/or an alloy semiconductor. In addition, in some embodiments, the substrate 102 may include an epi-layer. The substrate 102 may be strained to improve performance. The substrate 102 may include a silicon-on-insulator (SOI) structure, and/or the substrate 102 may have other suitable reinforcement components.

The gate stack 104 includes a gate dielectric layer 106 and a gate electrode layer 108 disposed on the gate dielectric layer 106. In some embodiments, the gate dielectric layer 106 may include an interface layer, such as silicon _{oxide (SiO 2} ) or silicon oxynitride (SiON), and the interface layer may be chemical oxidation, thermal oxidation, or atomic layer deposition (atomic layer deposition, ALD), chemical vapor deposition (CVD), and/or other suitable methods. In some examples, the gate dielectric layer 106 includes a high-k dielectric layer, such as hafnium oxide (HfO ₂ ). In addition, high-k dielectric layer may comprise other high k dielectric, such as _{TiO 2, HfZrO, Ta 2 O} 3, HfSiO 4, ZrO 2, ZrSiO 2, LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , Si ₃ N ₄ , silicon oxynitride (SiON), a combination of the foregoing, or other suitable materials. The high-permittivity gate dielectric layer used and described herein includes a dielectric material with a high permittivity, such as a permittivity greater than that of thermal silicon oxide (~3.9). In other embodiments, the gate dielectric layer 106 may include silicon dioxide or other suitable dielectrics. The gate dielectric layer 106 may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, and/or other suitable methods. In some embodiments, the gate electrode layer 108 may be deposited as part of a gate first or gate last (eg, replacement gate) process. In various embodiments, the gate electrode layer 108 includes conductive layers such as W, Ti, TiN, TiAl, TiAlN, Ta, TaN, WN, Re, Ir, Ru, Mo, Al, Cu, Co, CoSi, Ni , NiSi, a combination of the foregoing, and/or other suitable compositions. In some examples, the gate electrode layer 108 may include a first metal material for N-type transistors and a second metal material for P-type transistors. Therefore, the transistor 100 may include a dual work function metal gate configuration. For example, the first metal material (for example for an N-type device) may include a metal, which has a work function approximately aligned with the work function of the substrate conduction band, or at least approximately aligned with the channel region of the transistor 100 Work function of the conduction band of 114. Similarly, the second metal material (for example, for a P-type device) may include a metal, which has a work function that is approximately aligned with the work function of the valence band of the substrate, or at least approximately aligned with the channel region 114 of the transistor 100 The work function of the valence band. Therefore, the gate electrode layer 108 may provide a gate electrode for the transistor 100, which includes both N-type and P-type devices. In some embodiments, the gate electrode layer 108 may alternatively or additionally include a polysilicon layer. In various examples, physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam (e-beam) evaporation, and/or other suitable processes can be used to form the gate electrode layer 108. In some embodiments, sidewall spacers are formed on the sidewalls of the gate stack 104. The sidewall spacers may include dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a combination of the foregoing.

The transistor 100 also includes a source region 110 and a drain region 112, which are respectively formed in the substrate 102 of the semiconductor. The source region 110 and the drain region 112 are adjacent to the gate stack 104 and on both sides of the gate stack 104. In some embodiments, the source region 110 and the drain region 112 include diffused source/drain regions, ion-implanted source/drain regions, epitaxial growth regions, or a combination of the foregoing. The channel region 114 of the transistor 100 is defined as the region between the source region 110 and the drain region 112. The channel region 114 is under the gate dielectric layer 106 and in the substrate 102 of the semiconductor. The channel area 114 has an accompanying channel length "L" and an accompanying channel width "W". When a bias voltage greater than the threshold voltage (V _t ) of the transistor 100 (that is, the turn-on voltage) is applied to the gate electrode layer 108, the bias voltage is simultaneously applied to the source region 110 and the drain electrode. Between the regions 112, a current (for example, a transistor driving current) flows between the source region 110 and the drain region 112 through the channel region 114. The amount of drive current developed for a given bias voltage (for example, applied to the gate electrode layer 108 or applied between the source region 110 and the drain region 112), which is the mobility of the material forming the channel region 114 and Functions between other parameters. In some examples, the channel region 114 includes silicon (Si) and/or high-mobility materials, such as germanium, which can be formed by epitaxial growth, and the channel region 114 can also include any known compound semiconductors or alloy semiconductors. High-mobility materials include those with electron and/or hole mobility greater than silicon (Si). Silicon has an intrinsic electron mobility of about 1350cm ² /Vs at room temperature (300K), and silicon at room temperature ( The intrinsic hole mobility of 300K) is about 480 cm ² /Vs.

Referring to FIG. 1B, a fin field effect transistor (FinFET) device 150 is described here to provide an example of another device type, which may include embodiments of the present invention. By way of example, the FinFET device 150 includes one or more multi-gate field-effect transistors (FETs) based on a fin structure. The FinFET device 150 includes a substrate 152, at least one fin element 154 extending from the substrate 152, an isolation region 156, and a gate structure 158 disposed on the fin element 154 and around the fin element 154. The substrate 152 may be a semiconductor substrate, such as a silicon substrate. In various embodiments, the substrate 152 may be substantially the same as the substrate 102, and may include one or more materials for the substrate 102 as described above.

The fin element 154 is similar to the substrate 152, and may include one or more epitaxial growth layers, and may include silicon or other elemental semiconductors, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, Indium arsenide and/or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP; or a combination of the foregoing. Suitable processes can be used to manufacture the fin element 154, including lithography and etching processes. The photolithography process may include forming a photoresist layer (photoresist) on a substrate (for example, on a silicon layer), exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a photoresist Mask component. In some embodiments, an electron beam (e-beam) lithography process may be used to pattern the photoresist to form a mask element. Then, when the etching process forms a depression in the silicon layer, the mask element can be used to protect some areas of the substrate, by This leaves the fin element 154 extended. Dry etching (such as chemical oxide removal), wet etching, and/or other suitable processes may be used to etch the recesses. Various methods of other embodiments can also be used to form the fin element 154 on the substrate 152.

Each of the fin elements 154 further includes a source region 155 and a drain region 157, wherein the source region 155 and the drain region 157 are formed in, on, and/or surrounding the fin element 154. The source region 155 and the drain region 157 can be epitaxially grown above the fin element 154. In addition, the channel region of the transistor is disposed in the fin element 154, located under the gate structure 158 and along a plane, which is substantially parallel to the plane defined by the cross-section AA' of FIG. 1B. In some examples, the channel region of the fin element 154 includes a high mobility material as described above.

The isolation region 156 may be a shallow trench isolation (STI) feature. In addition, field oxide, local oxidation of silicon (LOCOS) components, and/or other suitable isolation components may be performed on and/or in the substrate 152. The isolation region 156 can be made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (fluorine-doped silicate glass, FSG), low-k dielectric, a combination of the foregoing, and/or known The composition of other suitable materials. In one embodiment, the isolation region 156 is a shallow trench isolation (STI) feature, and the trench is etched in the substrate 152, then the trench is filled with an isolation material, and then chemical mechanical polishing (chemical mechanical polishing, CMP) process. However, other embodiments are also possible. In some embodiments, the isolation region 156 may include a multilayer structure, such as one or more lining layers.

The gate structure 158 includes a gate stack having an interface layer 160 formed on the channel region of the fin element 154, a gate dielectric layer 162 is formed on the interface layer 160, and a metal layer 164 is formed on the gate dielectric layer 162 . In various embodiments Here, the interface layer 160 is substantially the same as the interface layer of a part of the gate dielectric layer 106 described. In some embodiments, the gate dielectric layer 162 is substantially the same as the gate dielectric layer 106, and may include a high-k dielectric, which is similar to the high-k dielectric used in the gate dielectric layer 106 Dielectric. Similarly, in various embodiments, the metal layer 164 is substantially the same as the aforementioned gate electrode layer 108. In some embodiments, sidewall spacers are formed on the sidewalls of the gate structure 158. The sidewall spacers may include dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a combination of the foregoing.

As discussed above, each of the transistor 100 and the FinFET device 150 may include one or more via-hole prefabricated metal gate contacts, embodiments of which are described in detail as follows. In some examples, the via-hole prefabricated metal gate contacts described herein may be part of a local interconnect structure. As used herein, the term "local interconnect" is used to describe the lowest level metal interconnection, and is different from the intermediate and/or overall interconnection. Local interconnects span relatively short distances, and are sometimes used, for example, to electrically connect to the source, drain, body, and/or gate of a given device or nearby devices. In addition, local interconnects can be used to facilitate the vertical connection of one or more devices with the upper metal layer (such as the middle interconnect layer), for example, via one or more vias. Interconnections (for example, including partial, intermediate, or overall interconnections) are usually formed as part of a back-end-of-line (BEOL) manufacturing process and include a multilayer mesh of metal wires. In addition, any multiple integrated circuits and/or devices (such as transistor 100 or FinFET 150) can be connected by interconnection.

With the drastic reduction and increasing complexity of advanced integrated circuit devices and circuits, the design of contacts and local interconnections has shown difficulties challenge. For example, forming a reliable contact to the metal gate layer and between the metal gate layer and the adjacent source, drain, and/or body region, which requires a high degree of overlap control ( Such as pattern-to-pattern alignment) and sufficient process tolerance. The term "process window" used here is used to define a specific focus point and exposure (intensity), which is used to pattern the final image into the photoresist layer (for example, by a photolithography process) , And meet the defined specifications (for example, for a given technology node, for a given tool set, etc.). In another way, the process tolerance can be used to set the focus point and the upper and lower boundaries of the exposure. Within this range, a patterned photoresist layer can still be produced and meet the defined specification limits. Those skilled in the art to which the present invention pertains will understand that it is generally desirable to improve (that is, increase) the size of the process tolerance. The continuous reduction in the size of integrated circuits, coupled with new patterning techniques (such as double patterning) has made accurate overlap control more difficult and more critical than ever. In addition, the process tolerance of the drastically reduced integrated circuit becomes quite narrow, which may lead to device degradation and/or failure. For at least some conventional processes, for forming such contacts to the metal gate layer, and between the metal gate layer and the adjacent source, drain, and/or body regions, the semiconductor manufacturing process The process tolerance has become too narrow, and there is no way to meet the process tolerance requirement for a longer period of time. In addition, in some current processes, during the formation of the contact to the metal gate layer, oxidation of the source and/or drain may occur, and after the contact is formed to the metal gate layer, the source and/or drain are usually formed. The silicide process of the electrode and the drain electrode. Therefore, the existing methods are no longer completely satisfactory in all aspects.

In order to further clarify the shortcomings of some existing processes, according to at least For some conventional manufacturing processes, refer to FIG. 2 to illustrate the method 200 of forming direct contacts between the metal gate and the adjacent source, drain, and/or body regions. The method 200 is described in more detail with reference to FIGS. 3 to 6 as follows. The method 200 starts at block 202, where a substrate with a gate structure is provided. Referring to FIG. 3, in an embodiment of block 202, a device 300 is provided, which has a substrate 302 and includes gate structures 304, 306, and 308. In some embodiments, the substrate 302 may be substantially the same as the aforementioned substrate 102 or 152. Gate structures 304, 306, and 308 are formed on a region of the substrate 302, and this region includes some regions of the substrate 302 between adjacent gate structures 304, 306, and 308. This region may include the active region of the substrate 302 . In various embodiments, each gate structure 304, 306, 308 may include an interface layer formed on the substrate 302, a gate dielectric layer formed on the interface layer, and a metal gate (MG) layer 310 is formed On the gate dielectric layer. In some embodiments, each interface layer, gate dielectric layer, and metal gate layer 310 of the gate structures 304, 306, and 308 may be substantially the same as those of the aforementioned transistor 100 and FinFET 150. In addition, each gate structure 304, 306, 308 may include sidewall spacer layers 312, 314. In some examples, the materials included in each sidewall spacer layer 312, 314 have different dielectric constant values (for example, k values).

The method 200 proceeds to block 204, where a dielectric layer is deposited on the substrate. Still referring to FIG. 3, and in an embodiment of the block 204, a dielectric layer 316 is formed on the substrate 302 and on each of the gate structures 304, 306, and 308. By way of example, the dielectric layer 316 may include an inter-layer dielectric (ILD) layer, which may include materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicon Salt glass, or doped silica, such as borophosphosilicate glass (borophosphosilicate glass, BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable media Electric materials. The dielectric layer 316 may be deposited by a subatmospheric CVD (SACVD) process, a flowable CVD process, or other suitable deposition techniques.

The method 200 proceeds to block 206, where a first pattern is formed in the dielectric layer. Referring to FIGS. 3 and 4, and in an embodiment of the block 206, a first pattern including openings 318 and 320 is formed in the dielectric layer 316. In some examples, the openings 318, 320 provide access to adjacent source, drain, or body contact regions. By way of example, the openings 318 and 320 can be formed by an appropriate combination of lithography patterning and etching (for example, wet etching or dry etching) processes.

The method 200 proceeds to block 208, where a second pattern is formed in the dielectric layer. Referring to FIGS. 4 and 5, and in an embodiment of the block 208, the second pattern including the opening 322 is formed in the dielectric layer 316. The opening 322 can also be formed by an appropriate combination of lithography patterning and etching (for example, wet etching or dry etching) processes. In some examples, the opening 322 provides an entrance to the metal gate layer 310 of the gate structure 306. In addition, as illustrated in FIG. 5, the opening 322 can be combined with the opening 318 to form a composite opening 324. After depositing one or more metal layers, as described below, the composite opening 324 thus provides direct contact between the metal gate layer and adjacent source, drain, and/or body regions.

Figure 5 also illustrates the distances of various main components, which are critical for determining process tolerances. For example, the double arrow marked A provides the opening 322 (for example, including the deposited metal subsequently disposed therein) and the gold of the gate structure 304 It belongs to the distance A between the gate layers 310. In at least some current manufacturing processes, a too small distance A may cause an unacceptable amount of leakage current. The double arrow marked B provides a distance B at which the opening 322 (for example, including the deposited metal subsequently disposed therein) overlaps the metal gate layer 310 of the gate structure 306, and this overlap may be referred to as a "landing window." In at least some current manufacturing processes, the distance B and the too small landing window may directly affect the quality and reliability of the connection with the metal gate layer 310 of the gate structure 306. The double arrow marked C provides the distance C between the opening 322 (for example, including the deposited metal subsequently disposed therein) and the opening 320 (for example, including the deposited metal subsequently disposed therein). In at least some current manufacturing processes, too small a distance C may also result in an unacceptable amount of leakage current. Therefore, for at least some conventional processes, the semiconductor manufacturing process used to form contacts to the metal gate layer and located between the metal gate layer and the adjacent source, drain, and/or body regions The process tolerance has become too narrow and cannot meet the requirement of process tolerance for a long time.

The method 200 proceeds to block 210, where metallization and chemical mechanical polishing processes are performed. Referring to FIGS. 5 and 6, and in an embodiment of block 210, a silicidation process can be initially performed to form a silicide layer on the exposed portion of the substrate 302 (for example, by combining the opening 324 and the opening 320 The exposed part), thereby providing a low-resistance contact. In some examples, and in another embodiment of the block 210, a glue layer or barrier layer 326 may be formed in each of the composite opening 324 and the opening 320. In some examples, the glue layer or barrier layer 326 may include Ti, TiN, Ta, TaN, W, or other suitable materials. In addition, in an embodiment of the block 210, a metal layer 328 may be formed on the glue layer or the barrier layer 326 in each of the composite opening 324 and the opening 320. In some examples, the metal layer 328 It may contain W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti or other suitable materials. After the metal layer 328 is deposited, and in an embodiment of the block 210, a chemical mechanical planarization (CMP) process may be performed to remove excess material and planarize the top surface of the device 300. Therefore, after the metal layer 328 is deposited, a direct contact is provided between the metal gate layer and the adjacent source, drain, and/or body regions. As described above, because of the narrow process tolerances in at least some existing processes, the device 300 may withstand an unacceptable amount of leakage current (for example, between the metal layer 328 and the metal gate layer 310 of the gate structure 304, and/or Between the metal layer 328 deposited in each composite opening 324 and opening 320). In addition, the landing window of the metal layer 328 in contact with the metal gate layer 310 of the gate structure 306 may be too small, which negatively affects the quality and reliability of the electrical connection of the metal gate layer 310 of the gate structure 306. Therefore, this proves that the existing technology is no longer completely satisfactory in all aspects.

The embodiments of the present invention provide advantages over existing technologies. However, it is understood that other embodiments may also provide different advantages. Not all advantages need to be discussed here, and specific advantages are not required for all embodiments. For example, the embodiments discussed include methods and structures related to the manufacturing process of via-hole prefabricated metal gate contacts. In at least some embodiments, a via hole pre-made metal gate contact process is provided, in which the gate via hole is first formed on the metal gate, and then the metal contact layer is formed on the gate via hole, instead of as in at least some traditional During the manufacturing process, the metal gate directly contacts the metal contact layer. In various examples, the metal contact layer may also be connected to adjacent source, drain, and/or body regions. In some embodiments, the gate vias are concentrated on the metal gate, and a larger landing window can be provided for the metal contact layer (for example, compared to allowing the metal gate to directly contact the metal Belongs to the contact layer). As a result of increasing the gate vias between the metal gate and the metal contact layer, it improves (eg increases) the process tolerance. In addition, the use of the gate vias described herein allows the metal contact layer (for example, the metal contact layer to contact the gate vias) to be set at an increased distance'Z' in the direction perpendicular to the substrate (for example, compared to at least some Traditional manufacturing process), thus providing greater isolation between the metal contact layer and the adjacent metal gate, wherein the metal contact layer is not connected to the adjacent metal gate. In this way, the leakage current between the metal contact layer and one or more adjacent metal gates is reduced, wherein the metal contact layer is not connected to the adjacent metal gates. Other details of the embodiments of the present invention are provided as follows, and those skilled in the art to which the present invention pertains can see additional benefits and/or other benefits from the benefits of the embodiments of the present invention.

Referring now to FIG. 7, a method 700 of forming a via hole prefabricated metal gate contact according to some embodiments is described. The method 700 is described in more detail with reference to FIGS. 8 to 14 as follows. The method 700 can be implemented on a single-gate planar device, such as the exemplary transistor 100 described above in Figure 1A, or on a multi-gate device, such as the FinFET device 150 described above in Figure 1B. Therefore, one or more of the points discussed above with reference to transistor 100 and/or FinFET 150 can also be applied to method 700. Undeniably, in various embodiments, the method 700 can be implemented on other devices, such as gate all-around (GAA) devices, Ω-shaped gate devices, or Π-shaped gate devices, as well as strained semiconductor devices and insulators. Silicon (SOI) devices, partially depleted SOI (PD-SOI) devices, fully depleted SOI (FD-SOI) devices, or other known devices.

It is understood that part of the method 700 and/or any exemplary transistor device discussed with reference to the method 700 can be made of a known complementary metal The process flow of the oxide semiconductor (CMOS) technology is manufactured, so some processes are only briefly described here. For clarity, some points of method 700 that are shared with method 200 may only be briefly discussed. In addition, it is understood that any of the exemplary transistor devices discussed herein may include various other devices and components, such as additional transistors, bipolar junction transistors, resistors, capacitors, diodes, and fuse elements. Etc., but simplified in order to make it easier to understand the concept of the embodiments of the present invention. In addition, in some embodiments, the exemplary transistor devices disclosed herein may include a plurality of semiconductor devices (such as transistors), and these semiconductor devices may be connected to each other. In addition, in some embodiments, various aspects of the embodiments of the present invention can be applied to a post-gate manufacturing process or a gate-first manufacturing process.

In addition, in some embodiments, the exemplary transistor device described herein may include a description of the device in an intermediate stage of the manufacturing process, may be manufactured during the manufacturing process of an integrated circuit, or may be part of an integrated circuit, which may include Static random access memory (SRAM) and/or other logic circuits; passive components, such as resistors, capacitors, and inductors; and active components, such as P-channel field effect transistors (PFETs), N-channel field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, etc. Memory cell, and/or a combination of the foregoing.

The method 700 starts at block 702, where a substrate with a gate structure is provided. Refer to FIG. 8 and in an embodiment of block 702, a device 800 is provided, which has a substrate 802 and includes gate structures 804, 806, and 808. In some embodiments, the substrate 802 may be substantially the same as the aforementioned substrates 102 and 152. Gate structures 804, 806, and 808 are formed on a region of the substrate 802, and this region includes some regions of the substrate 802 between adjacent gate structures 804, 806, and 808. This region may include the active region of the substrate 802 . It is understandable that the device 800 is only for illustration and provides a clear discussion of the pre-made metal gate contacts used for the subsequent formation of via holes. For example, in some examples, the device 800 may include a planar device, such as the transistor 100. In addition, in some examples, the device 800 may include a multi-gate device, such as the FinFET device 150. In addition, in some examples, the device 800 may include a gate-all-around (GAA) device, an Ω-shaped gate device, a Π-shaped gate device, a strained semiconductor device, a silicon-on-insulator (SOI) device, and a partially depleted SOI ( PD-SOI) device, fully depleted SOI (FD-SOI) device, or other known devices. In some embodiments, the device 800 includes regions 810 and 812 adjacent to the gate structures 804, 806, and 808. The regions 810 and 812 may include source regions, drain regions, or body contact regions (body contact regions). region). In various embodiments, each gate structure 804, 806, 808 may include an interface layer formed on the substrate 802, a gate dielectric layer formed on the interface layer, and a metal gate (MG) layer 814 formed on the gate On the dielectric layer. In some embodiments, each interface layer, gate dielectric layer, and metal gate layer 814 of the gate structures 804, 806, and 808 may be substantially the same as those previously described with respect to the transistor 100 and the FinFET device 150. In addition, each gate structure 804, 806, 808 may include sidewall spacer layers 816, 818. In some examples, the materials included in each sidewall spacer layer 816, 818 have different dielectric constant values (for example, k values). In various embodiments, the sidewall spacer layers 816, 818 include SiO _x , SiN, SiO _x N _y , SiC _x N _y , SiO _x C _y N _z , AlO _x , AlO _x N _y , AlN, HfO, ZrO, HfZrO, CN, poly-Si, a combination of the foregoing, or other suitable dielectric materials. In some embodiments, the sidewall spacer layers 816, 818 include multiple layers, such as main spacer walls, lining layers, and the like. By way of example, the sidewall spacer layers 816 and 818 can be formed by depositing a dielectric material on the device 800 and anisotropically etching the dielectric material back. In some embodiments, the etch-back process (for example, for forming spacers) may include a multi-step etch process to improve etch selectivity and provide over-etch control.

The method 700 proceeds to block 704, where a first dielectric layer is deposited on the substrate. Still referring to FIG. 8, and in an embodiment of block 704, a dielectric layer 820 is formed on the substrate 802 and on each of the gate structures 804, 806, and 808. By way of example, the dielectric layer 820 may include an interlayer dielectric (ILD) layer, which may include materials such as tetraethoxysilane (TEOS) oxide, undoped silicate glass, or doped Silica, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and/or other suitable media Electric materials. The dielectric layer 820 can be deposited by a sub-atmospheric chemical vapor deposition (SACVD) process, a flowable chemical vapor deposition process, or other suitable deposition techniques. In some embodiments, the thickness of the dielectric layer 820 is about 5-40 nm.

The method 700 proceeds to block 706, where a pattern is formed in the dielectric layer. Referring to FIGS. 8 and 9, and in an embodiment of the block 706, a pattern including openings 822 and 824 is formed in the dielectric layer 820. In some examples, the openings 822 and 824 provide entrances to the regions 810 and 812. The regions 810 and 812 are adjacent to the gate structures 804, 806 and 808. The regions 810 and 812 may include source regions, drain regions, Or body contact area. By way of example, the openings 822 and 824 can be formed by a suitable combination of lithography patterning and etching (such as wet etching or dry etching) processes. In some embodiments, the width of the openings 822, 824 is about 12-25 nm.

Method 700 proceeds to block 708, where metalization is performed (metallization) and chemical mechanical polishing process. Refer to Figures 9 and 10, and in an embodiment of block 708, a metal silicidation process can be initially performed to form a silicide layer in the regions 810 and 812 on the exposed portion of the substrate 802 (for example, by The exposed portions of the openings 822 and 824), therefore, low-resistance contacts are provided here. In some examples, and in another embodiment of the block 708, a glue layer or barrier layer 826 may be formed in each opening 822, 824. In some examples, the glue layer or barrier layer 826 may include Ti, TiN, Ta, TaN, W, or other suitable materials. In some embodiments, the thickness of the glue layer or barrier layer 826 is about 1-4 nm. In addition, in an embodiment of the block 708, a metal layer 828, 829 may be formed on the glue layer or the barrier layer 826 in each opening 822, 824. In some examples, the metal layers 828 and 829 may include W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti, TiN, TaN, WN, metal silicide, or other suitable conductive materials. In some examples, the metal layers 828 and 829 may comprise the same material, and may be deposited together as part of a single deposition process. In some embodiments, the metal layers 828, 829 may have a width of about 10-20 nm and a height of about 30-60 nm. After the metal layers 828 and 829 are deposited, and in one embodiment of the block 708, a chemical mechanical planarization (CMP) process may be performed to remove excess material and planarize the top surface of the device 800.

The method 700 proceeds to block 710, where a contact etch stop layer and a second dielectric layer are deposited on the substrate. Referring to FIGS. 10 and 11, and in an embodiment of block 710, a contact etch stop layer (CESL) 830 is formed on the substrate 802, and a dielectric layer 832 is formed on the contact etch stop layer 830 on. By way of example, the contact etching stop layer 830 may include Ti, TiN, TiC, TiCN, Ta, TaN, TaC, TaCN, W, WN, WC, WCN, TiAl, TiAlN, TiAlC, TiAlCN, or a combination of the foregoing. In some embodiments, the dielectric layer 832 may include an interlayer dielectric (ILD) layer, which may include materials such as tetraethoxysilane (TEOS) oxide, undoped silicate glass, or doped Silica, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and/or other suitable media Electric materials. Therefore, in some examples, the dielectric layer 832 may be substantially the same as the dielectric layer 820. In various embodiments, the contact etch stop layer 830 and the dielectric layer 832 may be formed by a sub-atmospheric chemical vapor deposition (SACVD) process, a flowable chemical vapor deposition process, an atomic layer deposition (ALD) process, or a physical vapor deposition process. Deposition (PVD) process, or other suitable deposition technology deposition. In some examples, the thickness of the contact etch stop layer 830 is about 5-20 nm, and the thickness of the dielectric layer 832 is about 5-40 nm.

The method 700 proceeds to block 712, where an opening for the gate via is formed. Referring to FIGS. 11 and 12, in an embodiment of the block 712, an opening 834 of the gate via is formed. By way of example, the opening 834 of the gate via provides an entrance to the metal gate layer 814 of the gate structure 806. By way of example, the opening 834 of the gate via can be formed by a suitable combination of lithography patterning and etching (for example, wet etching or dry etching) processes. In some examples, the opening 834 of the gate via has a width of about 12-25 nm. In some embodiments, one or more etching processes may be used to sequentially etch through each of the dielectric layer 832, contact the etch stop layer 830, and the dielectric layer 820. In various embodiments, the openings 834 of the gate vias are substantially aligned with (eg, concentrated on) the metal gate layer 814 of the gate structure 806. In addition, it should be understood that similar openings for gate vias can be formed to provide gate structures 804, 808, or to other metal gate layers of gate structures not shown. The entrance of 814.

The method 700 proceeds to block 714 where a contact opening is formed. Referring to FIGS. 12 and 13, and in an embodiment of the block 714, a contact opening 836 is formed. The contact opening 836 can also be formed by a suitable combination of lithography patterning and etching (for example, wet etching or dry etching) processes. In some examples, the contact opening 836 has a width of about 30-60 nm. In some embodiments, one or more etching processes may be used to sequentially etch through the dielectric layer 832 and contact the etch stop layer 830. In some examples, the contact opening 836 provides access to the metal layer 828. In addition, as shown in FIG. 13, the contact opening 836 can be combined with or overlapped with the opening 834 of the gate via to form a composite opening 838. In some embodiments, the contact opening 836 and the gate via opening 834 overlap each other by approximately 0-20 nm. After depositing one or more metal layers, as described below, the composite opening 838 thereby provides a contact between the metal gate layer and adjacent source, drain, and/or body regions. However, because of the pilot hole pre-manufacturing process described here, at least some of the shortcomings of the current process can be overcome.

For example, Figure 13 also illustrates the distances of various main components, which are critical for determining the process tolerance. In particular, when compared with the distances of at least some parts of the current manufacturing process (for example, as shown in FIG. 5), the advantages of the embodiments of the present invention are clear. For example, the double arrow labeled A'provides the distance between the contact opening 836 (e.g., including metal disposed therein for subsequent deposition) and the metal gate layer 814 of the gate structure 804. Compared to some current processes, and in some embodiments, the distance indicated by the double arrow labeled A'(Figure 13) is greater than the distance indicated by the double arrow labeled A (Figure 5). Therefore, in some embodiments, because of the increased distance'Z' of the metal in the contact opening 836 (for example, in the direction perpendicular to the substrate) Upward), the embodiment of the present invention provides greater isolation between the metal in the contact opening 836 and the adjacent metal gate, wherein the metal contact layer is not connected to the adjacent metal gate (such as a gate structure 804 of the metal gate layer 814). In this way, the leakage current between the metal in the contact opening 836 and the metal gate layer 814 of the gate structure 804 is reduced.

As another example, the double arrow marked B'provides the distance of the effective landing window. In the effective landing window, the contact opening 836 (for example, including the metal deposited later) can be connected to the gate via opening 834 (for example, Contains the metal disposed in it that is subsequently deposited) overlap. Compared to some current processes, and in some embodiments, the distance indicated by the double arrow labeled B'(Figure 13) is greater than the distance indicated by the double arrow labeled B (Figure 5). Therefore, in some embodiments, because of the increased landing window provided by the via-hole pre-manufacturing process disclosed herein, embodiments of the present invention provide higher quality and stronger gate connections.

As yet another example, the double arrow labeled C'provides the distance between the contact opening 836 (e.g., including the metal disposed therein for subsequent deposition) and the metal layer 829. Compared to some current processes, and in some embodiments, the distance indicated by the double arrow labeled C'(Figure 13) is greater than the distance indicated by the double arrow labeled C (Figure 5). Therefore, in some embodiments, because of the increased distance'Z' of the metal in the contact opening 836 (for example, in a direction perpendicular to the substrate), the metal and the metal layer 829 in the contact opening 836 are Provide greater isolation between. In this way, the leakage current between the metal in the contact opening 836 and the metal layer 829 is reduced.

Therefore, the embodiments of the present invention provide improved (that is, increased) process tolerance for forming contacts to the metal gate layer, and located between the metal gate layer and the metal gate layer. Between adjacent source, drain, and/or body regions. In some examples, the process tolerance can be improved by 10 nm (for example, regarding the distance between the main components indicated by the double arrow marked A'). In some embodiments, the process tolerance can be improved by at least 3 nm (for example, regarding the distance between the main components indicated by the double arrows marked B'and C').

The method 700 proceeds to block 716, where the metallization and chemical mechanical polishing processes are performed. Refer to FIGS. 13 and 14, and in an embodiment of block 716, a glue layer or barrier layer 840 may be formed in the composite opening 838. In some examples, the glue layer or barrier layer 840 may include Ti, TiN, Ta, TaN, W, or other suitable materials. In some embodiments, the thickness of the glue layer or barrier layer 840 is about 1-4 nm. In addition, in an embodiment of the block 716, a metal layer 842 may be formed on the glue layer or the barrier layer 840 in the composite opening 838. In some examples, the metal layer 842 may include W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti, or other conductive materials. It should be noted that the metal layer 842 in the composite opening 838 can be described as equivalent to the metal layer 842 formed in each of the contact openings 836 and the openings 834 of the gate vias, where the contact openings 836 and the gate The openings 834 of the vias are merged and/or overlapped as described above. Therefore, in some embodiments, and in the area of the contact opening 836, the metal layer 842 may have a width of about 30-60 nm and a height of about 10-30 nm. In addition, in some embodiments, and in the region of the opening 834 of the gate via, the metal layer 842 may have a width of about 10-25 nm and a height of about 20-45 nm. In some examples, the width of the metal layer 842 spans the length of the composite opening 838, which includes both the contact opening 836 and the gate via opening 834, and may be approximately 30-85 nm. After the metal layer 842 is deposited, and in an embodiment of the block 716, a chemical mechanical planarization (CMP) process may be performed to remove excess material and planarize the top surface of the device 800. Therefore, when depositing the metal layer After 842, a contact is made through the metal gate via hole and is located between the metal gate layer and the adjacent source, drain, and/or body regions. As mentioned above, and because of the improved (eg increased) process tolerance provided by the embodiments disclosed herein, the device 800 is more robust (eg, compared to at least some current devices).

Referring to Figure 15, the layout design 900 is illustrated here, which effectively provides a top view of the device 800 discussed above. In some embodiments, the cross-sectional views of the device 800 shown in Figures 8 to 14 are provided along a plane substantially parallel to the line X-X' drawn in Figure 15. The layout design 900 of FIG. 15 further illustrates the metal gate layer 914, which can be the aforementioned metal gate layer 814; the metal layers 928 and 929, which can be the aforementioned metal layers 828 and 829; and the metal layer 942, which It can be the aforementioned metal layer 842; and the gate via 934, which can be the aforementioned gate via formed in the opening 834 of the gate via. By way of example, and in some embodiments, the metal layer 942 may have a length of about 30-60 nm along the X axis and a width of about 10-30 nm along the Y axis. In some examples, the gate via 934 may have a length of about 10-25 nm along the X axis and a width of about 10-25 nm along the Y axis. In addition, in some embodiments, the metal gate layer 914 may have a width of about 4-10 nm along the X axis, and the metal layers 928 and 928 may have a width of about 10-30 nm along the X axis.

Referring now to FIG. 16, another method 1600 for forming via hole pre-fabricated metal gate contacts according to some embodiments is described. Generally speaking, when the method 700 describes the via-hole pre-manufacturing process including the via on the gate structure, the method 1600 shows that the via-hole pre-manufacturing process includes the via on the gate structure and the via on the metal contact. The metal contact is to the adjacent source region, drain region, or body contact region. Refer to Figures 17 to 23 to describe in detail the method 1600 as follows. The method 1600 can be used in a single gate flat It can be implemented on a surface device, such as the above-described exemplary transistor 100 in FIG. 1A, and it can also be implemented on a multi-gate device, such as the FinFET device 150 in FIG. 1B. Therefore, one or more of the points discussed above regarding the transistor 100 and/or the FinFET device 150 can also be applied to the method 1600. Undeniably, in various embodiments, the method 1600 can be implemented on other devices, such as gate all-around (GAA) devices, Ω-shaped gate devices, or Π-shaped gate devices, as well as strained semiconductor devices and insulators. Silicon (SOI) devices, partially depleted SOI (PD-SOI) devices, fully depleted SOI (FD-SOI) devices, or other known devices.

It is understandable that part of the method 1600 and/or any exemplary transistor devices discussed with reference to the method 1600 can be manufactured by the known complementary metal oxide semiconductor (CMOS) technology process flow, so some of the processes are only here. Briefly describe. For the sake of clarity, some points of method 1600 that are shared with method 200 or method 700 may only be briefly discussed. In addition, it is understood that any of the exemplary transistor devices discussed herein may include various other devices and components, such as additional transistors, bipolar junction transistors, resistors, capacitors, diodes, and fuse elements. Etc., but simplified in order to make it easier to understand the inventive concept of the embodiments of the present invention. In addition, in some embodiments, the exemplary transistor devices disclosed herein may include a plurality of semiconductor devices (such as transistors), and these semiconductor devices may be connected to each other. In addition, in some embodiments, various aspects of the embodiments of the present invention can be applied to a post-gate manufacturing process or a gate-first manufacturing process.

In addition, in some embodiments, the exemplary transistor device described herein may include a description of the device at an intermediate stage of the manufacturing process, which may be manufactured during the manufacturing process of an integrated circuit or a part of the integrated circuit, which may include static Random access memory (SRAM) and/or other logic circuits; passive components, such as resistors Devices, capacitors and inductors; and active components, such as P-channel field-effect transistors (PFETs), N-channel field-effect transistors (NFETs), metal oxide semiconductor field-effect transistors (MOSFETs), and complementary metal oxides Semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and/or combinations of the foregoing.

The method 1600 starts at block 1602, where a substrate with a gate structure is provided. Refer to FIG. 17 and in an embodiment of block 1602, a device 1700 is provided, which has a substrate 1702 and includes gate structures 1704, 1706, and 1708. In some embodiments, the substrate 1702 may be substantially the same as the aforementioned substrates 102 and 152. Gate structures 1704, 1706, 1708 are formed on a region of the substrate 1702, and this region includes some regions of the substrate 1702 located between adjacent gate structures 1704, 1706, 1708, and this region may include the active region of the substrate 1702 . It is understandable that the device 1700 is only for illustration and provided for clear discussion. In addition, in some examples, the device 1700 may include the aforementioned planar device, a multi-gate device, or other devices. In some embodiments, the device 1700 includes regions 1710, 1712 adjacent to the gate structures 1704, 1706, 1708, and the regions 1710, 1712 may include a source region, a drain region, or a body contact region. In various embodiments, each gate structure 1704, 1706, 1708 may include an interface layer formed on the substrate 1702, a gate dielectric layer formed on the interface layer, and a metal gate (MG) layer 1714 formed on the gate On the dielectric layer. In some embodiments, each interface layer, gate dielectric layer, and metal gate layer 1714 of the gate structures 1704, 1706, 1708 may be substantially the same as those previously described with respect to the transistor 100 and the FinFET device 150. In addition, each gate structure 1704, 1706, 1708 may include sidewall spacer layers 1716, 1718. In some examples, the material contained in each sidewall spacer layer 1716, 1718 has Different dielectric constant values (such as k value) can include one or more of the aforementioned materials, and can be formed by the aforementioned methods.

The method 1600 proceeds to block 1604, where a first dielectric layer is deposited on the substrate. Still referring to FIG. 17, and in an embodiment of block 1604, a dielectric layer 1720 is formed on the substrate 1702 and on each of the gate structures 1704, 1706, 1708. By way of example, the dielectric layer 1720 can include an interlayer dielectric (ILD) layer, which can include one or more of the aforementioned materials, and can be formed by one or more of the aforementioned methods. In some embodiments, the thickness of the dielectric layer 1720 is about 5-40 nm.

The method 1600 proceeds to block 1606, where a pattern is formed in the dielectric layer. Refer to FIGS. 17 and 18, and in an embodiment of the block 1606, a pattern including openings 1722, 1724 is formed in the dielectric layer 1720. In some examples, the openings 1722, 1724 provide entrances to the regions 1710, 1712, the regions 1710, 1712 are adjacent to the gate structures 1704, 1706, 1708, and the regions 1710, 1712 may include source regions, drain regions, Or body contact area. The openings 1722, 1724 may be formed by a suitable combination of lithography patterning and etching (for example, wet etching or dry etching) processes. In some embodiments, the width of the openings 1722, 1724 is about 12-25 nm.

The method 1600 proceeds to block 1608, where the metallization and chemical mechanical polishing processes are performed. Refer to Figures 18 and 19, and in an embodiment of block 1608, a metal silicide process can be initially performed to form a silicide layer in the regions 1710 and 1712 on the exposed part of the substrate 1702 (for example, through the opening 1722 1724 is exposed), so low-resistance contacts are provided here. In some examples, and in another embodiment of block 1608, a glue layer or barrier layer 1726 may be formed in each opening 1722, 1724. In some examples, the glue layer or barrier layer 1726 may include Ti, TiN, Ta, TaN, W, or other suitable materials. In some embodiments, the thickness of the glue layer or barrier layer 1726 is about 1-4 nm. In addition, in an embodiment of the block 1608, a metal layer 1728, 1729 may be formed on the glue layer or barrier layer 1726 in each opening 1722, 1724. In some examples, the metal layers 1728, 1729 may include W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti, TiN, TaN, WN, metal silicide, or other suitable conductive materials. In some examples, the metal layers 1728 and 1729 may comprise the same material, and may be deposited together as part of a single deposition process. In some embodiments, the metal layers 1728, 1729 may have a width of about 10-20 nm and a height of about 30-60 nm. After the metal layers 1728 and 1729 are deposited, and in an embodiment of the block 1608, a chemical mechanical planarization (CMP) process may be performed to remove excess material and planarize the top surface of the device 1700. Compared with the block 708 of the method 700, a part of the dielectric layer 820 remains after the CMP process; the CMP process of the block 1608 can be ground down to the top surface of the metal gate layer 1714 (for example, stop on it), so Remove substantially all of the dielectric layer 1720.

The method 1600 proceeds to block 1610, where a contact etch stop layer and a second dielectric layer are deposited on the substrate. Referring to FIGS. 19 and 20, and in an embodiment of block 1610, a contact etch stop layer (CESL) 1730 is formed on the substrate 1702, and a dielectric layer 1732 is formed on the contact etch stop layer 1730. By way of example, the contact etch stop layer 1730 may include Ti, TiN, TiC, TiCN, Ta, TaN, TaC, TaCN, W, WN, WC, WCN, TiAl, TiAlN, TiAlC, TiAlCN, or a combination of the foregoing. In some embodiments, the dielectric layer 1732 may include an interlayer dielectric (ILD) layer, which may include one or more of the aforementioned materials, and can be formed by one or more of the aforementioned methods. In some cases, connect The thickness of the contact etch stop layer 1730 is about 5-20 nm, and the thickness of the dielectric layer 1732 is about 5-40 nm.

The method 1600 proceeds to block 1612, where openings for gate vias and contact vias are formed. Referring to FIGS. 20 and 21, and in an embodiment of the block 1612, an opening 1734 of a gate via and an opening 1736 of a contact via are formed. By way of example, the opening 1734 of the gate via provides access to the metal gate layer 1714 of the gate structure 1706, and the opening 1736 of the contact via provides access to the metal layer 1728. By way of example, the openings 1734 of the gate vias and the openings 1736 of the contact vias can be formed by a suitable combination of lithography patterning and etching (such as wet etching or dry etching) processes. In some examples, each of the openings 1734 of the gate vias and the openings 1736 of the contact vias has a width of about 12-25 nm. In some embodiments, one or more etching processes may be used to sequentially etch through each of the dielectric layer 1732 and contact the etch stop layer 1730. As mentioned above, in various embodiments, the openings 1734 of the gate vias are substantially aligned with (eg, concentrated on) the metal gate layer 1714 of the gate structure 1706. Similarly, in some embodiments, the openings 1736 of the contact vias are substantially aligned with (eg, concentrated on) the metal layer 1728.

Method 1600 proceeds to block 1614, where contact openings are formed. Refer to FIGS. 21 and 22, and in an embodiment of the block 1614, a contact opening 1738 is formed. The contact opening 1738 can also be formed by a suitable combination of lithography patterning and etching (for example, wet etching or dry etching) processes. In some examples, the contact opening 1738 has a width of about 30-60 nm. In some embodiments, the etching process may etch the dielectric layer 1732 and stop on the contact etch stop layer 1730. In some examples, the contact opening 1738 may be in contact with the opening 1734 of the gate via The openings 1736 of the component guide holes merge and/or overlap to form a composite opening 1740. In some embodiments, the contact opening 1738 overlaps each of the gate via opening 1734 and the contact via opening 1736 by about 0-20 nm. After depositing one or more metal layers, as described below, the composite opening 1740 thus provides contacts between the metal gate layer and adjacent source, drain, and/or body regions.

It should be noted that the embodiment of the method 1600 described herein also provides an increased distance'Z' (for example, in the direction perpendicular to the substrate) of the metal in the contact opening 1738, thereby 1738 provides greater isolation between the metal and the adjacent metal gate or other metal contacts, where the metal contact layer is not connected to the adjacent metal gate or other metal contacts (such as the gate structure 1704 The metal gate layer 1714, or the metal layer 1729). In this way, leakage current can be reduced. In addition, the embodiment described with respect to the method 1600 also provides an increased landing window, ensuring a higher quality and stronger connection.

The method 1600 proceeds to block 1616, where the metallization and chemical mechanical polishing processes are performed. Refer to FIGS. 22 and 23, and in an embodiment of the block 1616, a glue layer or barrier layer 1742 may be formed in the composite opening 1740. In some examples, the glue layer or barrier layer 1742 may include Ti, TiN, Ta, TaN, W, or other suitable materials. In some embodiments, the thickness of the glue layer or barrier layer 1742 is about 1-4 nm. In addition, in an embodiment of the block 1616, a metal layer 1744 may be formed on the glue layer or barrier layer 1742 in the composite opening 1740. In some examples, the metal layer 1744 may include W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti, or other conductive materials. It should be noted that the metal layer 1744 in the composite opening 1740 can be described as equivalent to the metal layer 1744 formed in each contact opening 1738, gate via opening 1734, and contact via opening 1736, such as The aforementioned contact The element opening 1738 overlaps each of the opening 1734 of the gate via and the opening 1736 of the contact via. Therefore, in some embodiments, the width of the metal layer 1744 across the length of the composite opening 1740 is about 30-60 nm, and the height of the metal layer 1744 is about 10-30 nm. After the metal layer 1744 is deposited, and in one embodiment of the block 1616, a chemical mechanical planarization (CMP) process may be performed to remove excess material and planarize the top surface of the device 1700. Therefore, after the metal layer 1744 is deposited, the contact is made through the metal gate via and the contact via, and the contact is located between the metal gate layer and the adjacent source, drain, and/or body regions . As mentioned above, because of the improved (eg increased) process tolerance provided by the embodiments disclosed herein, the device 1700 is more robust (eg, compared to at least some current devices).

Referring to Figure 24, the layout design 1800 is illustrated here, which effectively provides a top view of the device 1700 discussed previously. In some embodiments, the cross-sectional view of the device 1700 shown in Figures 17 to 23 is provided along a plane substantially parallel to the line Y-Y' drawn in Figure 24. The layout design 1800 of FIG. 24 further illustrates the metal gate layer 1814, which can be the aforementioned metal gate layer 1714; the metal layers 1828 and 1829, which can be the aforementioned metal layers 1728 and 1729; the metal layer 1844, which It can be the aforementioned metal layer 1744; the gate via 1834, which can be the aforementioned gate via formed in the opening 1734 of the gate via; and the contact via 1836, which can be the aforementioned formed in the contact guide. The contact guide hole in the opening 1736 of the hole. By way of example, and in some embodiments, the metal layer 1844 may have a length of about 30-60 nm along the X axis, and a width of about 10-30 nm along the Y axis. In some examples, the gate via 1834 may have a length of about 10-25 nm along the X axis, and a width of about 10-25 nm along the Y axis. In a In some examples, the contact via 1836 may have a length of about 10-25 nm along the X axis, and a width of about 10-25 nm along the Y axis. In addition, in some embodiments, the metal gate layer 1814 may have a width of about 4-10 nm along the X axis, and the metal layers 1828 and 1829 may have a width of about 10-30 nm along the X axis.

The various embodiments described herein provide several advantages over existing technologies. It should be understood that not all of the advantages need to be described here, for all embodiments, specific advantages are not required, and other embodiments may provide different advantage. As an example, the embodiment discussed here includes the method and structure of the manufacturing process of the via-hole prefabricated metal gate contact. In at least some embodiments, a via hole pre-made metal gate contact process is provided. The gate via is first formed on the metal gate, and then the metal contact layer is formed on the gate via, instead of as in at least some traditional processes Let the metal gate directly contact the metal contact layer. In various examples, the metal contact layer may also be connected to adjacent source, drain, and/or body regions. In some embodiments, the gate vias are concentrated on the metal gate, and a larger landing window can be provided for the metal contact layer (for example, compared to the metal gate directly contacting the metal contact layer). As a result of increasing the gate vias between the metal gate and the metal contact layer, it improves (eg increases) the process tolerance. In addition, the gate vias described herein are used so that the metal contact layer (for example, which is in contact with the gate vias) is arranged at an increased distance'Z' in the direction perpendicular to the substrate (for example, compared to at least some conventional Process), therefore, a greater isolation is provided between the metal contact layer and the adjacent metal gate, wherein the metal contact layer is not connected to the adjacent metal gate. In this way, the leakage current between the metal contact layer and one or more adjacent metal gates is reduced, wherein the metal contact layer is not connected to the adjacent metal gates. Therefore, the various embodiments disclosed herein provide higher quality and stronger gate connections, which further Provides improved device and circuit performance.

Therefore, one of the embodiments of the present invention describes a method of manufacturing a semiconductor device, which includes depositing a first dielectric layer on a substrate. In some embodiments, the substrate includes a gate structure, and the gate structure has a metal gate layer. In some examples, an opening is formed in the first dielectric layer to expose a portion of the substrate adjacent to the gate structure, and the first metal layer is deposited in the opening. In various embodiments, the second dielectric layer is deposited on the first dielectric layer and on the first metal layer. Afterwards, in some embodiments, the first dielectric layer and the second dielectric layer are etched to form the opening of the gate via, where the opening of the gate via exposes the metal gate layer of the gate structure. In some examples, a part of the second dielectric layer is removed to form a contact opening, which exposes the first metal layer, where the gate via opening and the contact opening merge to form a composite opening. In some embodiments, a second metal layer is deposited in the composite opening, where the second metal layer electrically connects the metal gate layer of the gate structure to the first metal layer through the gate via hole portion of the second metal layer .

In one embodiment, the above method further includes depositing a contact etch stop layer on the substrate after depositing the first metal layer and before depositing the second dielectric layer, and depositing a second dielectric layer on the contact etch stop layer.

In one embodiment, the above method further includes etching the first dielectric layer, contacting the etch stop layer and the second dielectric layer to form the opening of the gate via.

In one embodiment, the above method further includes removing a part of the second dielectric layer and a part of the contact etch stop layer to form a contact opening, which exposes the first metal layer.

In one embodiment, the above method further includes forming a silicide layer on the substrate after forming the opening in the first dielectric layer and before depositing the first metal layer On the exposed part, the exposed part is adjacent to the gate structure; and the first metal layer is deposited on the silicide layer.

In one embodiment, the above method further includes performing a chemical mechanical polishing process after depositing the first metal layer, wherein the chemical mechanical polishing process planarizes the top surface of the semiconductor device, and wherein a part of the first dielectric layer is subjected to chemical mechanical polishing. Retained after the mechanical grinding process.

In one embodiment, the first dielectric layer and the second dielectric layer include interlayer dielectric layers.

In one embodiment, the exposed portion of the substrate adjacent to the gate structure includes a source region, a drain region or a body contact region.

In one embodiment, the opening of the gate via is aligned with the metal gate layer of the gate structure.

In one embodiment, the second metal layer is electrically connected to the metal gate layer of the gate structure to the first metal layer, and the first metal layer is electrically connected to the source region, the drain region or the body contact region.

In another embodiment, a method is discussed, in which a first metal layer is formed, which is adjacent to the sidewall of the gate structure. In some embodiments, the first metal layer is in contact with a region of the substrate under the first metal layer, and the gate structure includes a metal gate. In some examples, the first dielectric layer is deposited on the substrate. In some embodiments, and in a region above the gate structure, the first dielectric layer is etched to form an opening of the gate via, where the opening of the gate via exposes the metal gate of the gate structure. In various examples, and in a region above the first metal layer, the first dielectric layer is etched to form the opening of the contact via hole, where the opening of the contact via hole exposes the first metal layer. In some embodiments, and from the opening of the gate via and contact In a region between the openings of the via holes, the first dielectric layer is removed to form a contact opening, where the contact opening, the gate via opening and the contact via opening are combined to form a composite opening. Afterwards, in some embodiments, a second metal layer is formed in the composite opening, and the metal gate of the gate structure is electrically connected to the first through the gate via portion and the contact via portion of the second metal layer. Metal layer.

In one embodiment, the above method further includes depositing a contact etch stop layer on the substrate before depositing the first dielectric layer, and depositing a first dielectric layer on the contact etch stop layer.

In one embodiment, the above method further includes etching the contact etch stop layer and the first dielectric layer in a region above the gate structure to form the opening of the gate via.

In one embodiment, the above method further includes etching the contact etch stop layer and the first dielectric layer in a region above the first metal layer to form the opening of the contact via hole.

In one embodiment, the above method further includes depositing a second dielectric layer on the substrate before forming the first metal layer; forming an opening in the second dielectric layer to expose the substrate under the first metal layer A region; and forming a first metal layer in the opening.

In one embodiment, the above method further includes performing a chemical mechanical polishing process to planarize the top surface of the semiconductor device after forming the first metal layer in the opening and before depositing the first dielectric layer, wherein the chemical mechanical polishing process is moved Remove the second dielectric layer and stop on the top surface of the metal gate.

In one embodiment, a region of the substrate under the first metal layer includes a source region, a drain region, or a body contact region.

In one embodiment, the opening of the gate via is aligned with the metal gate of the gate structure, and the opening of the contact via is aligned with the first metal layer.

In yet another embodiment, a semiconductor device is discussed, which includes a substrate having a gate structure, and the gate structure includes a metal gate. In some examples, the first metal layer is adjacent to the sidewall spacers disposed on the sidewalls of the gate structure, where the first metal layer contacts a region of the substrate below the first metal layer. In some embodiments, the dielectric layer is disposed on the substrate, where the dielectric layer includes a composite opening filled with the second metal layer. In various examples, the second metal layer includes a gate via defined in the gate via portion of the composite opening, where the gate via contacts the metal gate, and the gate via is substantially aligned with the metal gate. In some embodiments, the second metal layer contacts the first metal layer in the contact portion of the composite opening.

In one embodiment, a region of the substrate under the first metal layer includes a source region, a drain region, or a body contact region.

The components of several embodiments are summarized above, so that those with ordinary knowledge in the technical field of the present invention can better understand the concept of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that the embodiments of the present invention can be used as a basis to design or modify other processes and structures to achieve the same purpose and/or the same as the embodiments described herein. the benefits of. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that these equivalent structures do not depart from the spirit and scope of the present invention, and various modifications can be made here without departing from the spirit and scope of the present invention. Changes, substitutions and other choices. Therefore, the scope of protection of the present invention shall be subject to the definition of the attached patent scope.

800‧‧‧device

802‧‧‧Base

810, 812‧‧‧ area

828、829‧‧‧Metal layer

830‧‧‧Contact etching stop layer

832‧‧‧Dielectric layer

834‧‧‧The opening of the gate via

836‧‧‧Contact opening

838‧‧‧Composite opening

A’, B’, C’‧‧‧distance

Z‧‧‧ Increased distance

Claims (14)

A method for manufacturing a semiconductor device includes: depositing a first dielectric layer on a substrate, wherein the substrate includes a gate structure with a metal gate layer; forming an opening in the first dielectric layer to Expose a portion of the substrate adjacent to the gate structure, and deposit a first metal layer in the opening; deposit a second dielectric layer on the first dielectric layer and on the first metal layer Etching the first dielectric layer and the second dielectric layer to form a gate via opening, wherein the gate via opening exposes the metal gate layer of the gate structure; removing the first A part of the two dielectric layers to form a contact opening exposing the first metal layer and the metal gate layer, wherein the opening of the gate via and the contact opening merge to form a composite opening And depositing a second metal layer in the composite opening, wherein the second metal layer is electrically connected to the metal gate layer of the gate structure through a gate via hole portion of the second metal layer A metal layer. The method for manufacturing a semiconductor device as described in claim 1 further includes: after depositing the first metal layer and before depositing the second dielectric layer, depositing a contact etch stop layer on the substrate, and Depositing the second dielectric layer on the contact etch stop layer. The method of manufacturing a semiconductor device as described in item 2 of the scope of the patent application further includes: After depositing the first metal layer, the first dielectric layer, the contact etch stop layer and the second dielectric layer are etched to form the opening of the gate via. The method for manufacturing a semiconductor device as described in claim 2 further includes: removing the part of the second dielectric layer and a part of the contact etching stop layer to form the contact opening, the contact opening The first metal layer is exposed. The method for manufacturing a semiconductor device as described in any one of claims 1 to 4, wherein the exposed portion of the substrate adjacent to the gate structure includes a source region, a drain region or a body Contact area. A method for manufacturing a semiconductor device includes: forming a first metal layer adjacent to a sidewall of a gate structure, wherein the first metal layer contacts a region of a substrate located below the first metal layer, and wherein the The gate structure includes a metal gate; depositing a first dielectric layer on the substrate; etching the first dielectric layer in a region above the gate structure to form a gate via Opening, wherein the opening of the gate via hole exposes the metal gate of the gate structure; the first dielectric layer in a region above the first metal layer is etched to form a contact via hole Opening, wherein the opening of the contact via hole exposes the first metal layer; the first dielectric layer is removed from a region between the opening of the gate via and the opening of the contact via to form a Contact opening, wherein the contact opening, the opening of the gate guide hole and the opening of the contact guide hole are combined to form Forming a composite opening, the composite opening exposing the first metal layer and the metal gate; and forming a second metal layer in the composite opening through a gate via hole portion of the second metal layer and a contact guide The hole portion electrically connects the metal gate of the gate structure to the first metal layer. The method for manufacturing a semiconductor device as described in claim 6 further includes: before depositing the first dielectric layer, depositing a contact etch stop layer on the substrate, and depositing the first dielectric layer on the substrate. The contact etch stop layer. The method for manufacturing a semiconductor device as described in claim 7 further comprises: etching the contact etching stop layer and the first dielectric layer in the region above the gate structure to form the gate The opening of the pilot hole. The method for manufacturing a semiconductor device as described in claim 7 further comprises: etching the contact etch stop layer and the first dielectric layer in the region above the first metal layer to form the contact The opening of the guide hole of the piece. The method for manufacturing a semiconductor device as described in any one of claims 6 to 9 of the scope of the patent application further includes: before forming the first metal layer, depositing a second dielectric layer on the substrate; forming an opening In the second dielectric layer to expose the region of the substrate under the first metal layer; and forming the first metal layer in the opening. The method for manufacturing a semiconductor device as described in claim 10 further includes: after forming the first metal layer in the opening and before depositing the first dielectric layer, performing a chemical mechanical polishing process to The top surface of the semiconductor device is planarized, wherein the chemical mechanical polishing process removes the second dielectric layer and stops on the top surface of the metal gate. The method for manufacturing a semiconductor device as described in any one of claims 6 to 9, wherein the opening of the gate via is aligned with the metal gate of the gate structure, and wherein the opening of the contact via The sidewalls of the first metal layer extend beyond the sidewalls of the first metal layer. A semiconductor device includes: a substrate including a gate structure with a metal gate; a first metal layer adjacent to a sidewall spacer arranged on a sidewall of the gate structure, wherein the first metal layer Contacting a region of the substrate under the first metal layer; and a dielectric layer on the substrate, wherein the dielectric layer includes a composite opening filled with a second metal layer; wherein the second metal The layer includes a gate via hole defined in a gate via hole portion of the composite opening, wherein the gate via hole contacts the metal gate, and wherein the gate via hole is aligned with the metal gate, and the gate The top surface of the via hole is higher than the top surface of the first metal layer; and wherein the first metal layer contacts the second metal layer in a contact part of the composite opening. The semiconductor device described in item 13 of the scope of patent application, wherein the first gold The attribute layer contacts the sidewall spacer.

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