TWI713154B - Memory device - Google Patents

Abstract

A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.

Description

Memory device

The present invention relates to a memory device, and in particular to a NAND memory device.

As the critical size of components in integrated circuits gradually shrinks to the perceptible limit of the process technology, designers have begun to look for technologies that can achieve greater memory density, thereby achieving lower costs per bit. The technology currently being watched includes NAND memory and its operation.

The invention relates to a memory device.

According to one aspect of the present invention, a memory device is provided that includes a channel element, a gate electrode layer, and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds the side channel surface of the channel element.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

C: Channel element

CS1: First side channel surface

CS2: Second side channel surface

CS3: Third side channel surface

D1: First direction

D2: second direction

D3: Third party

M: memory element

M1A: The first memory layer

M1S1: side surface

M2, M2A, M2B, M2C: the second memory layer

M3, M3A, M3B, M3C: the third memory layer

MA: the first memory part

MB: The second memory part

MC: The third memory part

G, GT, GM, GB: gate electrode layer

GS1: side surface

GS2: upper surface

GS3: bottom surface

112: Dielectric Strip

114: conductive layer

116: Electrode element

118: Electrode element

250: first stacking area

260: second stacking area

330: Dielectric layer

330S1: side surface

330S2: upper surface

330S3: lower surface

473, 474: Sacrifice Layer

475: hole

477: Notch

480: groove

485: Gap

487: Electrode Material

489: Conductive column

491: Conductive Strip

493: conductive block

495: Conductive column

497: Conductive Strip

FIG. 1 is a cross-sectional view of a memory device according to an embodiment.

FIG. 2 is a longitudinal cross-sectional view of a memory device according to an embodiment.

3 to 13 illustrate a method of manufacturing a memory device according to an embodiment.

Some examples are described below. It should be noted that this disclosure does not show all possible embodiments, and other implementation aspects not mentioned in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn in proportion to the actual products. Therefore, the contents of the description and illustrations are only used to describe the embodiments, rather than to limit the protection scope of this disclosure. In addition, the descriptions in the embodiments, such as detailed structure, process steps, material applications, etc., are for illustrative purposes only, and are not intended to limit the scope of the disclosure. The respective details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. In the following description, the same/similar symbols represent the same/similar elements.

FIG. 1 is a cross-sectional view of a memory device according to an embodiment. FIG. 2 is a longitudinal cross-sectional view of a memory device according to an embodiment. In one embodiment, the first figure may be a cross-sectional view drawn along the KK section line of the second figure, and the second figure may be a cross-sectional view drawn along the JJ section line of the first figure.

Please refer to FIG. 1, the memory device includes a channel element C, a gate electrode layer G and a memory element M.

In the embodiment, the channel element C has a U shape. Channel element C The side channel surface may include a first side channel surface CS1, a second side channel surface CS2, and a third side channel surface CS3. The second side channel surface CS2 is between the first side channel surface CS1 and the third side channel surface CS3. In an embodiment, the channel element C may have a U-shaped configuration of a horseshoe pattern or an open loop pattern. The first side channel surface CS1 (the outer surface of the horseshoe pattern or the open loop pattern) and the third side channel surface CS3 (the inner surface of the horseshoe pattern or the open loop pattern) have a U shape. The second side channel surface CS2 (the end side surface of the horseshoe pattern or the open loop pattern) may have a flat shape. The dielectric pillar 110 may be on the third side channel surface CS3.

The memory element M may include several memory layers. In one embodiment, the memory element M includes a first memory layer M1A, a second memory layer M2, and a third memory layer M3. The second memory layer M2 is on the side surface of the first memory layer M1A. The third memory layer M3 is on the side surface of the second memory layer M2.

The memory element M includes a first memory part MA and a second memory part MB. The first memory part MA is on the first side channel surface CS1. The first memory part MA has a U shape. The second memory portion MB is on the second side channel surface CS2 of the channel element C. The second memory portion MB may be on the same side plane of the first memory layer M1A and the channel element C. The second memory part MB has a straight shape. The first memory portion MA and the second memory portion MB form a ring shape, surrounding the side channel surface of the channel element C and the side surface of the dielectric pillar 110.

The number of memory layers of the first memory part MA may be different from the number of memory layers of the second memory part MB. In this embodiment, the number of memory layers in the first memory portion MA is greater than the number of memory layers in the second memory portion MB. The first memory part The MA may include a first memory layer M1A, a second memory layer M2A, and a third memory layer M3A. In other words, the first memory part MA has 3 memory layers. The second memory part MB may include a second memory layer M2B and a third memory layer M3B. In other words, the second memory part MB has two memory layers. The second memory part MB may not include the first memory layer. The first memory layer M1A, the second memory layer M2A, and the third memory layer M3B of the first memory portion MA have a U shape. The side surface M1S1 of the first memory layer M1A may be coplanar with the second side channel surface CS2 of the channel element C. The second memory layer M2B and the third memory layer M3B of the second memory portion MB have a flat shape.

The first memory portion MA may include any charge trapping structure, such as an oxide-nitride-oxide (ONO) structure or an oxide-nitride-oxide-nitride-oxide (BE-SONOS) structure, etc. . For example, the charge trapping layer can use nitrides such as silicon nitride, or other similar high dielectric constant materials including metal oxides, such as aluminum oxide (Al ₂ O ₃ ), zirconium oxide (HfO ₂ ), etc. . The first memory layer M1A includes a tunneling layer. The second memory layer M2 (including the second memory layer M2A and the second memory layer M2B) includes a charge trapping layer. The third memory layer M3 (including the third memory layer M3A and the third memory layer M3B) includes a barrier layer. In one embodiment, the tunneling layer includes oxide such as silicon oxide. The charge trapping layer includes nitride such as silicon nitride. The barrier layer includes oxides such as silicon oxide, aluminum oxide, and the like.

The first memory portion MA and the channel element C are between the second memory portion MB and the gate electrode layer G. The second memory part MB is between the dielectric pillar 110 and the dielectric bar 112. The dielectric pillar 110 may include an oxide such as silicon oxide, but is not limited thereto.

Please refer to Figure 1 and Figure 2, the memory device can include several stacks Stack areas, such as the first stack area 250, the second stack area 260, and so on. The dielectric strip 112 is between the gate electrode layer G of the first stack region 250 and the gate electrode layer G of the second stack region 260. The first stack region 250 and the second stack region 260 each include a gate electrode layer G and a dielectric layer 330. The gate electrode layer G and the dielectric layer 330 are alternately arranged in the first direction D1 (for example, the vertical direction). The gate electrode layer G is electrically coupled to the channel element C. The gate electrode layer G may include a gate electrode layer GT located at the topmost layer, a gate electrode layer GB located at the bottommost layer, and a gate electrode layer GM between the gate electrode layer GT and the gate electrode layer GB. The stacking areas of the memory device, such as the first stacking area 250, the second stacking area 260, etc., may be arranged in a horizontal direction (for example, the second direction D2).

In one embodiment, the memory element M further includes a third memory portion MC. The first memory part MA is connected between the second memory part MB and the third memory part MC. The third memory portion MC may continuously extend from the first memory portion MA to the side surface 330S1, the upper surface 330S2, and the lower surface 330S3 of the dielectric layer 330, and the upper surface GS2 and the lower surface GS3 of the gate electrode layer G.

The memory element M is between the gate electrode layer G and the dielectric layer 330. The memory element M is on the side surface GS1 (side electrode surface), upper surface GS2 (upper electrode surface), and lower surface GS3 (lower electrode surface) of the gate electrode layer G. The memory element M is on the side surface 330S1 (side dielectric surface), upper surface 330S2 (upper dielectric surface), and lower surface 330S3 (lower dielectric surface) of the dielectric layer 330. The side surface GS1 with the memory element M thereon is opposite to the side surface 330S1 with the memory element M thereon.

The number of memory layers of the first memory part MA may be different from the number of memory layers of the third memory part MC, or have different memory layer configurations. First memory The number of memory layers divided into MA may be greater than the number of memory layers in the third memory portion MC. The number of memory layers of the third memory portion MC may be the same as the number of memory layers of the second memory portion MB, or have the same memory layer configuration. The memory layer of the third memory portion MC may include a second memory layer M2C and a third memory layer M3C. The third memory portion MC may not include the first memory layer.

The conductive layer 114 may be on the first memory layer M1A, the channel element C and the dielectric pillar 110. The electrode element 116 and the electrode element 118 are electrically connected to the conductive layer 114 separated from the second memory portion MB by the dielectric strip 112, respectively.

The memory device includes a NAND memory string. The NAND memory string may include memory cells defined in the memory elements M between the gate electrode layers G of the channel elements C. The NAND memory string may include a U-channel NAND memory string or a vertical channel NAND memory string.

In an embodiment, the electrode element 116 may be a bit line, and the electrode element 118 may be a common source line. The NAND memory string may include memory cells defined in the memory element M between the channel element C and the gate electrode layer G of the first stack region 250 and the second stack region 260. The NAND memory string has a U-shaped effective channel path, and the U-shaped channel and the memory cell are electrically connected between the electrode element 116 as a bit line and the electrode element 118 as a common source line. The gate electrode layer GT of the first stack region 250 may be used as a string selection line (SSL). The gate electrode layer GT of the second stack region 260 may be used as a ground selection line (GSL). In an embodiment, the gate electrode layer GB of the first stack region 250 and the gate electrode layer GB of the second stack region 260 can be used as inversion gate electrodes. In an embodiment, the gate electrode layer GM of the first stack region 250 and the second stack region 260 The gate electrode layer GM can be used as a word line. In an embodiment, a portion of the gate electrode layer GM adjacent to the gate electrode layer GT in the first stack region 250 and/or the second stack region 260 can be used as dummy word lines to avoid possible interference. For example, the top gate electrode layer GM in the first stack region 250 and the top gate electrode layer GM in the second stack region 260 can be used as dummy word lines. The substrate 100 may be an insulating layer, for example, a buried oxide such as buried silicon oxide formed on a semiconductor substrate, but is not limited thereto.

In another embodiment, the electrode element 116 may be a bit line. The substrate 100 can be electrically connected to a common source terminal or used as a common source element. The substrate 100 may include a semiconductor substrate, such as a substrate containing silicon material, such as a silicon substrate. The NAND memory string may include memory cells defined in the memory element M between the channel element C and the gate electrode layer G of the first stack region 250. The NAND memory string has an effective vertical channel path extending in the first direction D1 (for example, the vertical direction), and is electrically connected between the electrode element 116 and the substrate 100. The gate electrode layer GT of the first stack region 250 may be used as a string selection line (SSL). The gate electrode layer GB of the first stack region 250 may be used as a ground selection line (GSL). In an embodiment, the gate electrode layer GM of the first stack region 250 can be used as a word line. In an embodiment, a part of the gate electrode layer GM of the first stack region 250 may be used as a dummy word line. The electrode element 118 can also be used as a bit line, or the vertical channel NAND memory series on the second stacking area 260 side can be analogized as described above.

3 to 13 illustrate a method of manufacturing a memory device according to an embodiment.

Please refer to Figure 3 to provide a substrate 100. A stacked structure may be formed on the substrate 100. The stacked structure may include sacrificial layers and dielectric layers 330 alternately stacked on the base 100 on the bottom. The sacrificial layer may include the sacrificial layer 474 and the sacrificial layer 473 thereunder. The sacrificial layer 473, the sacrificial layer 474, and the dielectric layer 330 may include different materials. In one embodiment, the sacrificial layer 473 and the sacrificial layer 474 include nitride, such as silicon nitride, but not limited thereto. The dielectric layer 330 includes oxide, such as silicon oxide, but is not limited thereto. The sacrificial layer 473, the sacrificial layer 474, and the dielectric layer 330 may be formed by a deposition method such as physical vapor deposition, chemical vapor deposition, or other suitable methods. Yellow light lithography and etching techniques can be used to form holes 475 in the stacked structure. In one embodiment, the etching step for forming the hole 475 can be stopped on the substrate 100. In one embodiment, the hole 475 exposes the buried oxide layer of the substrate 100.

Referring to FIG. 4, the first memory layer M1A may be formed on the side surface of the stack structure exposed by the hole 475 and the upper surface of the substrate 100. The first memory layer M1A may also be formed on the upper surface of the stacked structure. The channel element C may be formed on the first memory layer M1A exposed by the hole 475. The channel element C may also be formed on the first memory layer M1A on the upper surface of the stack structure. The channel element C may include polysilicon or other suitable semiconductor materials. In an embodiment, the dielectric pillar 110 may be formed on the channel element C and fill the hole 475. In one embodiment, the method for forming the dielectric pillar 110 may include forming a dielectric material to fill the hole 475 and extend on the channel element C on the upper surface of the stacked structure, and may use chemical mechanical polishing or other suitable etching methods to remove the The dielectric material on the upper surface of the stacked structure and the remaining dielectric material in the hole 475 form the dielectric pillar 110. The dielectric material may include oxide such as silicon oxide, but is not limited thereto. The first memory layer M1A and the channel element C on the upper surface of the stacked structure can also be removed by chemical mechanical polishing or other suitable etching methods. can The first memory layer M1A, the channel element C and the dielectric pillar 110 in the hole 475 are etched back by a suitable etching method to form a notch 477. The depth of the notch 477 does not reach the upper surface of the sacrificial layer 473 of the top layer.

Please refer to FIG. 5, the conductive layer 114 may form a filling recess 477. In an embodiment, the method for forming the conductive layer 114 may include forming a conductive material to fill the recess 477 on the upper surface of the stacked structure, and using chemical mechanical polishing or other suitable etching methods to position the conductive layer 114 on the stacked structure Part of the surface is removed. The conductive material may include doped polysilicon, such as heavily doped N-type polysilicon, or other suitable conductive materials such as metals. In one embodiment, the sacrificial layer 474 and the conductive layer 114 on the topmost dielectric layer 330 of the stacked structure can be removed by chemical mechanical polishing or other suitable etching methods (such as etchback) to planarize the stacked structure. Upper surface.

FIG. 5A is a cross-sectional view of the memory device of FIG. 5 drawn along the section line KK. Referring to FIG. 5A, in one embodiment, the dielectric pillar 110 in the hole 475 may have an elliptical shape or a playground shape. The channel element C has a ring shape and surrounds the dielectric pillar 110. The first memory layer M1A has a ring shape and surrounds the channel element C. FIG. 5B is a cross-sectional view of the memory device of FIG. 5 drawn along the QQ section line. Please refer to FIG. 5B, the conductive layer 114 may have an oval shape or a playground shape. Fig. 5 is a longitudinal sectional view of the memory device shown in Figs. 5A and 5B drawn along the JJ section line.

Referring to FIG. 6, a trench 480 can be formed. The trench 480 can be patterned with the conductive layer 114 and the stacked structure, the dielectric pillar 110, and the channel The element C and the upper part of the first memory layer M1A are formed. The trench 480 can expose the side surface of the dielectric pillar 110, the second side channel surface CS2 of the channel element C, the side surface M1S1 of the first memory layer M1A, the side surface of the sacrificial layer 473, the side surface of the dielectric layer 330, and the conductive layer. 114's side surface. The bottom of the trench 480 can expose the dielectric pillar 110, the channel element C, the first memory layer M1A, and the sacrificial layer 473 of the stacked structure. The trench 480 defines the stack structure to define different stacking regions (the first stacking region 250 and the second stacking region 260, etc.), so that the sacrificial layers 473 in the different stacking regions are separated from each other.

FIG. 6A is a cross-sectional view of the memory device of FIG. 6 drawn along the section line KK. Referring to FIG. 6A, the trench 480 extends in the third direction D3, and the patterned dielectric pillar 110 has a semicircular shape. The patterned channel element C may have a U shape, a horseshoe shape, or an open loop shape. The patterned first memory layer M1A may have a U shape, a horseshoe shape, or an open loop shape. Fig. 6B is a cross-sectional view of the memory device of Fig. 6 drawn along the QQ section line. Referring to FIG. 6B, the patterned conductive layer 114 may have a semicircular shape. Fig. 6 is a longitudinal sectional view of the memory device shown in Figs. 6A and 6B drawn along the JJ section line.

Referring to FIG. 7, the sacrificial layer 473 exposed by the trench 480 (FIG. 6) can be removed to form a gap 485. The sacrificial layer 473 can be removed by an etching process with etching selectivity. The gap 485 communicates with the groove 480. The gap 485 can expose the side surface of the first memory layer M1A, the upper surface 330S2 and the lower surface 330S3 of the dielectric layer 330, and the upper surface of the substrate 100.

FIG. 7A is a cross-sectional view of the memory device of FIG. 7 drawn along the section line KK. Please refer to Figure 7A. At this step, the memory device can use the The electric pillar 110, the channel element C and the first memory layer M1A serve as a support to support other elements, such as the dielectric layer 330. Fig. 7 is a longitudinal sectional view of the memory device shown in Fig. 7A drawn along the JJ section line.

Referring to FIG. 8, the second memory layer M2 can be formed on the trench 480 and the dielectric pillar 110 exposed by the gap 485, the channel element C, the first memory layer M1A, the dielectric layer 330, and the substrate 100.

Referring to FIG. 9, the third memory layer M3 may be formed on the second memory layer M2 exposed by the trench 480 and the gap 485.

FIG. 9A is a cross-sectional view of the memory device of FIG. 9 drawn along the section line KK. Referring to FIG. 9A, the second memory layer M2 may have a ring shape and surround the dielectric pillar 110, the channel element C, and the first memory layer M1A. The third memory layer M3 may have a ring shape and surround the second memory layer M2. Fig. 9 is a longitudinal sectional view of the memory device shown in Fig. 9A drawn along the JJ section line.

Referring to FIG. 10, the electrode material 487 may be formed on the third memory layer M3 exposed by the trench 480 and the gap 485. The electrode material 487 can fill the gap 485. In an embodiment, the electrode material 487 may include a barrier metal such as titanium nitride (TiN), and a filler metal formed on the barrier metal such as tungsten (W). But this disclosure is not limited to this. The electrode material 487 may also include other suitable configurations/materials such as conductive materials such as polysilicon or other metals.

Referring to FIG. 11, the electrode material 487 (FIG. 10) can be etched back to remove the part of the electrode material 487 in the trench 480, and leave the part in the gap 485 to form the gate electrode layer G. Different layers of gate electrode layer G can be made of dielectric layer 330 are separated from each other and electrically isolated.

Referring to FIG. 12, a dielectric strip 112 can be formed to fill the trench 480. The dielectric strip 112 can also fill part of the gap 485. The dielectric strip 112 may include oxide such as silicon oxide, but is not limited thereto.

Referring to FIG. 13, a conductive pillar 489 can be formed on the conductive layer 114. A conductive strip 491 and a conductive block 493 can be formed on the conductive pillar 489. A conductive pillar 495 may be formed on the conductive block 493. A conductive strip 497 may be formed on the conductive pillar 495. In an embodiment, the conductive strip 497 may extend in the second direction D2. The conductive strip 491 may extend in the third direction D3. In one embodiment, the conductive strip 491 can be used as a common source line. The conductive bar 497 can be used as a bit line. The U-shaped channel element C can be electrically connected between the conductive strip 491 and the conductive strip 497. The first direction D1, the second direction D2, and the third direction D3 may be different from each other, for example, are substantially perpendicular to each other. The first direction D1 may be the Z direction. The second direction D2 may be the X direction. The third direction D3 may be the Y direction.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

C: Channel element

CS1: First side channel surface

CS2: Second side channel surface

CS3: Third side channel surface

D1: First direction

D2: second direction

D3: Third party

M: memory element

M1A: The first memory layer

M1S1: side surface

M2, M2A, M2B, M2C: the second memory layer

M3, M3A, M3B, M3C: the third memory layer

MA: the first memory part

MB: The second memory part

MC: The third memory part

G: Gate electrode layer

112: Dielectric Strip

Claims (8)

A memory device includes: a channel element having a U shape; a gate electrode layer electrically coupled to the channel element; and a memory element surrounding a side channel surface of the channel element, and the side channel of the channel element The surface includes a first side channel surface, a second side channel surface, and a third side channel surface. The second side channel surface is between the first side channel surface and the third side channel surface. The first side The channel surface and the third side channel surface have a U shape, wherein the memory element includes: a first memory portion having a U shape and on the first side channel surface; and a second memory portion having a straight shape and On the surface of the second side channel. In the memory device described in claim 1, wherein the number of memory layers in the first memory portion is different from the number of memory layers in the second memory portion. The memory device described in claim 1, wherein the number of memory layers in the first memory portion is greater than the number of memory layers in the second memory portion. The memory device described in claim 1, wherein the memory element includes: a first memory layer; A second memory layer on a side surface of the first memory layer; and a third memory layer on a side surface of the second memory layer, wherein the first memory portion includes the first memory layer, The second memory layer and the third memory layer; the second memory portion includes the second memory layer and the third memory layer. The memory device described in claim 1 includes a plurality of the gate electrode layers, wherein the memory device further includes a plurality of dielectric layers, and the gate electrode layers and the dielectric layers are in a vertical direction The memory elements are arranged in a staggered arrangement on the upper side, and the memory elements are between the gate electrode layers and the dielectric layers. As for the memory device described in claim 5, the memory element is on an upper electrode surface and a lower electrode surface of each of the gate electrode layers, and on an upper dielectric surface of each of the dielectric layers With a bit on the dielectric surface. For the memory device described in item 5 of the patent application, the memory element is on one electrode surface of each of the gate electrode layers, and on one dielectric surface of each of the dielectric layers, the The surface of the side electrode is opposite to the surface of the side dielectric. The memory device according to claim 5, wherein the memory element includes: a third memory part connected to the first memory part and continuously extending to the upper surface, lower surface and/or of the dielectric layers Or side surface.

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