TWI798825B - Manufacturing method of semiconductor device - Google Patents

Abstract

A manufacturing method of a semiconductor device including following steps is provided. First, a substrate is provided, wherein there are a first well region, a second well region and a double-diffused region formed in a region of a high voltage semiconductor device defined in the substrate, and the second well region and the double-diffused region are located in the first well region. Then, an isolation structure is formed in the substrate. After that, a first oxidation process is performed in a region of a medium voltage semiconductor device defined in the substrate. After that, a second oxidation process is performed in a region of a low voltage semiconductor device defined in the substrate. After that, a gate structure is formed on the substrate, wherein the gate structure covers a portion of the isolation structure. Moreover, a source region and a drain region are formed in the substrate, wherein the source region is located in the first well region and disposed at one side of the gate structure, and the drain region is located in the double-diffused region and disposed at opposite side of the gate structure. A process step that a RESURF region is formed in the first well region after the isolation structure is formed in the substrate is further provided. The RESURF region is embedded in the double-diffused region and is simultaneously formed in one of the process steps of the first oxidation process, the second oxidation process and the forming process of the source region and the drain region.

Description

Manufacturing method of semiconductor element

The present invention relates to a manufacturing method of a semiconductor element, and in particular to a manufacturing method of a high-voltage semiconductor element.

High-voltage semiconductor elements must have a relatively high breakdown voltage during operation. Therefore, at present, when forming high-voltage semiconductor elements, a reduced surface electric field region ( RESURF region) to increase the breakdown voltage of high-voltage semiconductor components. Based on this, how to efficiently form the RESURF region is one of the current issues.

The invention provides a manufacturing method of a semiconductor element, which has process flexibility in the step of forming the RESURF region, and can reduce the process cost of forming the RESURF region.

A method of manufacturing a semiconductor element of the present invention includes the following steps. First, a substrate with the first conductivity type is provided, where the substrate is defined as a high-voltage semiconductor element In the region of the component, a first well region with the first conductivity type, a second well region with the first conductivity type, and a double diffusion region with the second conductivity type are formed, wherein the second well region and the double diffusion region are located at the first In a well area. Next, an isolation structure is formed in the substrate. Afterwards, a first oxidation process is performed in the region of the substrate defined as the medium-voltage semiconductor device. Then, a second oxidation process is performed in the region of the substrate defined as the low-voltage semiconductor device. Then, a gate structure is formed on the substrate, wherein the gate structure covers part of the isolation structure. Afterwards, a source region with a second conductivity type and a drain region with a second conductivity type are formed in the substrate, wherein the source region is located in the first well region and is disposed on one side of the gate structure, and the drain region is located at the side of the gate structure. In the double diffusion area and disposed on the other side of the gate structure. The manufacturing method of the semiconductor device in this embodiment further includes forming a RESURF region in the first well region after forming the isolation structure in the substrate, wherein the RESURF region is embedded in the double diffusion region, and the RESURF region is used for performing the first well region. The first oxidation process, the second oxidation process, or the step of forming the source region and the drain region are formed.

In an embodiment of the present invention, the above-mentioned double diffusion region is formed in the first well region by sequentially performing the first ion implantation process and the second ion implantation process.

In one embodiment of the present invention, the implantation dose in the first ion implantation process is 4.8E12cm ^-2 ~ 7.2E12cm ^-2 , and the implantation energy is 960keV ~ 1440keV, in the second ion implantation process The dose of implantation is 5.92E12cm ^-2 ~8.88E12cm ^-2 , and the energy of implantation is 280keV~420keV.

In an embodiment of the present invention, the method for forming the RESURF region includes performing a third ion implantation process, in which the dose of implantation in the third ion implantation process is 2.8E12cm ^-2 ~ 4.2E12cm ^-2 , and implanting The input energy is 240keV~360keV.

In an embodiment of the present invention, the above isolation structure includes a first isolation structure, a second isolation structure and a third isolation structure, the first isolation structure covers part of the second well region and is located on one side of the gate structure, the second The second isolation structure covers part of the double diffusion region and is located on the other side of the gate structure, and the third isolation structure is located between the first isolation structure and the second isolation structure, wherein part of the third isolation structure is covered by the gate structure .

In an embodiment of the present invention, the above-mentioned RESURF region partially overlaps with the third isolation structure.

字的形狀。 In an embodiment of the present invention, the above-mentioned RESURF region is close to the gate structure, and the double diffusion region has

The shape of the word.

In an embodiment of the present invention, the above-mentioned RESURF region is close to the drain region, and the double diffusion region has a ㄈ shape.

In an embodiment of the present invention, the above-mentioned RESURF region is buried in the double diffusion region.

Based on the above, the manufacturing method of the semiconductor element provided by the present invention is to form the RESURF region after the isolation structure is formed, and can choose to perform the process of forming the dielectric layer for the medium-voltage semiconductor element and the formation of the dielectric layer for the low-voltage semiconductor element. The dielectric layer of the element is formed during the process of forming the source region and the drain region. Compared with the prior art, which generally forms the reduced surface electric field region before the formation of the isolation structure, it has process flexibility. , can also reduce the process cost.

10: Semiconductor components

100: base

102: The first well area

104: The second well area

106: source region

108: Drain area

110:Double diffusion zone

120: Reduced surface electric field area

130: matrix area

200: isolation structure

200a: first isolation structure

200b: second isolation structure

200c: The third isolation structure

300: gate structure

302: gate oxide layer

304: gate

306: gap wall

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic partial cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a schematic partial cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a schematic partial cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

In the following embodiments, the first conductivity type is P-type, and the second conductivity type is N-type; however, the present invention is not limited thereto. In other embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type. The P-type dopant is, for example, boron, and the N-type dopant is, for example, phosphorous or arsenic.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

The schematic diagrams herein are only used to illustrate some embodiments of the present invention. because Therefore, the shape, quantity and scale of each element shown in the schematic diagrams should not be used to limit the present invention.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

A method of manufacturing a semiconductor element 10 according to a first embodiment of the present invention will be described below with reference to FIG. 1 . In detail, FIG. 1 mainly depicts a region of the substrate 100 defined as a high-voltage semiconductor device. It should be noted that although FIG. 1 only shows an embodiment of the high-voltage semiconductor element formed on the substrate 100, the medium-voltage semiconductor element and the low-voltage semiconductor element can be formed on other regions on the substrate 100 not shown in FIG. 1 , that is, the substrate 100 further includes a region defined as a medium-voltage semiconductor element and a region defined as a low-voltage semiconductor element.

First, a substrate 100 with a first conductivity type is provided. For example, the substrate in this embodiment may be a P-type substrate. After that, a first well region 102 with the first conductivity type and a second well region 104 with the first conductivity type are sequentially formed in the substrate, wherein the second well region 104 is located in the first well region 102 . In some embodiments, the first well region 102 is a P-type deep well (DPW) region, and the second well region 104 is a P-type high pressure well (HVPW or P-Body) region. In some embodiments, the method for forming the first well region 102 in the substrate may include performing the following steps. Firstly, a patterned mask layer is formed on the substrate. Next, an ion implantation process is performed to implant dopants in the substrate. The dopant implanted in the above-mentioned ion implantation process may be, for example, boron, and the implantation dose may be, for example, a commonly used dose in the technical field, and the present invention is not particularly limited. In addition, after removing the above-mentioned patterned mask layer, a thermal drive-in process is performed to diffuse dopants in the substrate 100 to form the first well region 102 . Additionally, in some embodiments Among them, the method for forming the second well region 104 in the substrate may include performing the above steps, wherein the difference is that the implanted dose for forming the second well region 104 is greater than the implanted dose for forming the first well region 102, and the above dose may be, for example, The dosage commonly used in the technical field is not particularly limited in the present invention.

Next, a double-diffused region 110 having a second conductivity type is formed in the substrate 100 . In some embodiments, the method for forming the double diffusion region 110 in the substrate may include performing the following steps. Firstly, a patterned mask layer is formed on the substrate. Next, the first ion implantation process and the second ion implantation process are sequentially performed to implant dopants in the substrate. The dopant implanted in the above-mentioned first ion implantation process and the second ion implantation process may be phosphorus or arsenic, for example. In some embodiments, the implantation dose in the first ion implantation process is 4.8E12cm ⁻² to 7.2E12cm ⁻² , and the implantation energy is 960keV˜1440keV. In addition, the implantation dose in the second ion implantation process is 5.92E12cm ⁻² ~8.88E12cm ⁻² , and the implantation energy is 280keV~420keV. In this embodiment, the implant dose in the first ion implantation process is 6E12 cm ⁻² , and the implant energy is 1200 keV. In addition, in this embodiment, the implantation dose in the second ion implantation process is 7.4E12 cm ^-2 , and the implantation energy is 350keV. In addition, after removing the above-mentioned patterned mask layer, a thermal entry process is performed to diffuse dopants in the substrate 100 to form the double diffusion region 110 . The double diffusion region 110 of this embodiment can be used to provide a higher breakdown voltage for the high-voltage semiconductor element to prevent damage to it caused by electrostatic discharge, etc., and solve the hot electron effect generated after the channel of the high-voltage semiconductor element is shortened, and then can Avoid electrical breakdown in the drain region under a high voltage operating environment. In detail, the double diffusion region 110 is used as a drift region in this embodiment, which can increase the current path from the drain region to the gate, so that the breakdown voltage from the drain region to the gate is increased.

Afterwards, an isolation structure 200 is formed in the substrate 100 . The isolation structure 200 may, for example, include a plurality of isolation structures. In this embodiment, the isolation structure 200 includes a first isolation structure 200a, a second isolation structure 200b, and a third isolation structure 200c. The formation method of the isolation structure 200 may be, for example, a shallow trench isolation method or a local area oxidation isolation method. In this embodiment, the formation method of the isolation structure 200 is a shallow trench isolation method.

Then, a first oxidation process is performed to form a dielectric layer (not shown) in the area of the substrate 100 where the medium-voltage semiconductor device is to be formed, wherein the dielectric layer is, for example, a gate dielectric layer for the medium-voltage semiconductor device. The above-mentioned first oxidation process may be, for example, a thermal oxidation process, and the present invention is not particularly limited.

In some embodiments, the RESURF region 120 of the first conductivity type can be formed together in the substrate 100 by utilizing the thermal budget provided during the first oxidation process, wherein the RESURF region 120 is embedded in the double A PN junction is formed in the diffusion region 110 in a horizontal direction (parallel to the direction in which the surface of the substrate 100 extends). In detail, the method for forming the RESURF region in the substrate may include the following steps. Firstly, a patterned mask layer is formed on the substrate. Next, an ion implantation process is performed to implant dopants in the substrate. The dopant implanted in the above-mentioned ion implantation process may be, for example, boron. In some embodiments, the implant dose in the ion implantation process is 2.8E12cm ⁻² to 4.2E12cm ⁻² , and the implant energy is 240keV˜360keV. In this embodiment, the implant dose in the ion implantation process is 3.5E12 cm ^-2 , and the implant energy is 300keV. In addition, after removing the above-mentioned patterned mask layer, a thermal annealing process is performed using the thermal budget provided during the above-mentioned first oxidation process, so that the implanted dopants are activated to occupy the crystal lattice to form the RESURF region 120. The RESURF region 120 of this embodiment can be used to extend the depletion region close to the drain region or the surface of the substrate 100 to increase the width of the depletion region, thereby reducing the isolation structure 200 between the drain region and the gate. The electric field below reduces the probability of electron collision, which increases the breakdown voltage from the drain region to the gate. It should be noted that, in other embodiments, the RESURF region 120 having the first conductivity type can be formed in a subsequent process.

After the first oxidation process is performed, a second oxidation process is performed to form a dielectric layer (not shown) in the region of the substrate 100 where low-voltage semiconductor elements are to be formed, wherein the above-mentioned dielectric layer is used as a gate of the low-voltage semiconductor element, for example. dielectric layer. The above-mentioned second oxidation process may be, for example, a thermal oxidation process, and the present invention is not particularly limited. In some other embodiments, the RESURF region 120 of the first conductivity type can be formed in the substrate 100 together by utilizing the thermal budget provided during the second oxidation process, wherein the RESURF region 120 is embedded in the double diffusion region 110 in order to form a PN junction in the horizontal direction. The possible steps of the method for forming the RESURF region 120 in the substrate have been described in the foregoing embodiments in detail, and will not be repeated here. It is worth noting that the RESURF region 120 of this embodiment is formed by utilizing the thermal budget given during the second oxidation process to perform a thermal annealing process, so that the implanted dopants are activated to occupy the crystal lattice.

Afterwards, a gate structure 300 is formed on the substrate 100 . In this embodiment, the formed gate structure 300 includes a gate oxide layer 302 , a gate 304 and a spacer 306 . The method for forming the gate structure 300 on the substrate 100 includes, for example, the following steps, but it should be noted that the present invention is not limited thereto. First, a gate oxide material layer and a gate material layer are formed on the substrate 100 by thermal oxidation or chemical vapor deposition. Next, a patterning process is performed on the gate material layer and the gate oxide material layer to form the gate electrode 304 and the gate oxide layer 302 respectively. Afterwards, a spacer material layer is formed by thermal oxidation or chemical vapor deposition, and an anisotropic etching process is performed on the spacer material layer to form a spacer 306 on the sidewall of the gate 304 .

Then, a source region 106 and a drain region 108 of the second conductivity type are formed in the substrate 100 , wherein the source region 106 is located in the second well region 104 , and the drain region 108 is located in the double diffusion region 110 . In some embodiments, the method of forming the source region 106 and the drain region 108 in the substrate may include the following steps. Firstly, a patterned mask layer is formed on the substrate. Next, an ion implantation process is performed to implant dopants in the substrate. The dopant implanted in the above-mentioned ion implantation process may be, for example, phosphorus or arsenic, and the implantation dose may be, for example, a commonly used dose in the technical field, and the present invention is not particularly limited. In addition, after removing the patterned mask layer, a thermal annealing process is performed to form the source region 106 and the drain region 108 . In yet other embodiments, the RESURF region 120 of the first conductivity type can be formed in the substrate 100 together by utilizing the thermal budget provided during the thermal annealing process, wherein the RESURU region 120 is embedded in the double diffusion region 110 to form a PN junction in the horizontal direction. The possible steps of the method for forming the RESURF region 120 in the substrate have been described in the foregoing embodiments in detail, and will not be repeated here. It is worth noting that the RESURF region 120 of this embodiment uses the thermal budget given during the thermal annealing process to carry out the thermal annealing process, so that the implanted The dopants are activated to occupy the crystal lattice to form.

In some embodiments, a base region 130 of the first conductivity type can be further formed in the substrate 100 , wherein the base region 130 is located in the second well region 104 and adjacent to the source region 106 . In some embodiments, the method for forming the body region 130 in the substrate may include performing the following steps. Firstly, a patterned mask layer is formed on the substrate. Next, an ion implantation process is performed to implant dopants in the substrate. The dopant implanted in the above-mentioned ion implantation process may be, for example, boron, and the implantation dose may be, for example, a commonly used dose in the technical field, and the present invention is not particularly limited. In addition, after removing the aforementioned patterned mask layer, a thermal annealing process is performed to form the base region 130 .

In summary, the manufacturing method of the semiconductor element 10 provided in this embodiment can be selected to perform the process of forming a dielectric layer for medium-voltage semiconductor elements, perform the process of forming a dielectric layer for low-voltage semiconductor elements, or perform the process of forming The source region 106 and the drain region 108 are formed together during the process. Compared with the prior art that generally forms the RESURF region before forming the isolation structure, it not only has process flexibility, but also can reduce the process cost.

So far, the fabrication of the semiconductor element 10 of the present invention is completed.

Although the method for manufacturing the semiconductor device 10 of this embodiment is described by taking the above method as an example, the method for manufacturing the semiconductor device 10 of the present invention is not limited thereto.

Please continue to refer to FIG. 1 , which illustrates a schematic cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention. In detail, FIG. 1 illustrates the region of the semiconductor device 10 where the high voltage semiconductor device is formed. It must be noted here that the following about the provincial For the description of the abbreviated part, reference may be made to the descriptions and effects of the foregoing embodiments, and the following embodiments will not be repeated.

In one embodiment, the semiconductor device 10 includes a substrate 100, a gate structure 300, a first well region 102, a second well region 104, a source region 106, a drain region 108, a double diffusion region 110, and a RESURF region 120. , the base region 130 and the isolation structure 200 . In this embodiment, the semiconductor device 10 has an asymmetric structure, but the invention is not limited thereto. That is, in other embodiments, the semiconductor device 10 may have a symmetrical structure, such as a symmetry plane passing through the center of the gate structure 300 , and the remaining components of the semiconductor device 10 are symmetrical to each other on this symmetry plane.

The substrate 100 is, for example, a semiconductor substrate with a first conductivity type. In this embodiment, the substrate 100 is a P-type substrate, and the material of the substrate 100 can be at least one selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP. a material. In other embodiments, the substrate 100 may also be a silicon-on-insulator (SOI) substrate. In yet other embodiments, the substrate 100 may be a P-type epitaxial (P-epi) wafer.

The gate structure 300 is, for example, disposed on the substrate 100 . In this embodiment, the gate structure 300 may include a gate oxide layer 302 , a gate 304 and a spacer 306 . The gate 304 is, for example, disposed on the substrate 100 , and the gate oxide layer 302 is, for example, disposed between the gate 304 and the substrate 100 , and the spacer 306 is, for example, disposed on a sidewall of the gate 304 . The material of the gate oxide layer 302 can be silicon oxide or a material with a high dielectric constant. The material of the gate 304 can be doped polysilicon, undoped polysilicon or a combination thereof, but the invention is not limited thereto. In another embodiment, the material of the gate 304 can be metal, gold Nitride or other suitable materials, which may include Ti, W, TiN, TaN, TiSiN, Mo, MoN, MoSiN, HfN, HfSi or combinations thereof. The material of the spacer 306 can be silicon oxide.

The first well region 102 is, for example, disposed in the substrate 100 and has the first conductivity type, that is, the first well region 102 is a P-type well region. In this embodiment, the first well region 102 may be a P-type deep well region.

The second well region 104 is, for example, disposed in the substrate 100 and located in the first well region 102 . The second well region 104 has the first conductivity type, that is, the second well region 104 is a P-type well region. In this embodiment, the second well region 104 can be used as a source well region of the semiconductor device 10 .

The double diffusion region 110 is, for example, disposed in the substrate 100 and located in the first well region 102 . In one embodiment, the double diffusion region 110 and the second well region 104 are respectively located on two sides of the gate structure 300 . The double diffusion region 110 has the second conductivity type, that is, the double diffusion region 110 is an N-type well region. In this embodiment, the double diffused region 110 can be used as a drift region of the semiconductor device 10 .

The source region 106 and the drain region 108 are, for example, disposed in the substrate 100 and respectively located on opposite sides of the gate structure 300 . In addition, the source region 106 and the drain region 108 have the second conductivity type, that is, the source region 106 and the drain region 108 are N-type well regions. In this embodiment, the source region 106 and the drain region 108 are respectively located in the second well region 104 and the double diffusion region 110 . In detail, the source region 106 is located in the second well region 104 , and the drain region 108 is located in the double diffusion region 110 .

The isolation structure 200 is, for example, disposed in the substrate 100 . In this example, The isolation structure 200 includes a first isolation structure 200a, a second isolation structure 200b and a third isolation structure 200c. For example, the first isolation structure 200 a covers part of the second well region 104 and is located at one side of the gate structure 300 . From another point of view, the source region 106 is located between the first isolation structure 200 a and the gate structure 300 , for example. For example, the second isolation structure 200 b covers part of the double diffusion region 110 and is located on the other side of the gate structure 300 . From another point of view, the drain region 108 is located between the second isolation structure 200 b and the gate structure 300 , for example. The third isolation structure 200c is, for example, located between the first isolation structure 200a and the second isolation structure 200b, and part of the third isolation structure 200c is covered by the gate structure 300 . In this embodiment, the isolation structure 200 is a shallow trench isolation structure. The material of the isolation structure 200 can be, for example, undoped silicon oxide, silicon nitride or a combination thereof.

The RESURF region 120 is, for example, disposed in the substrate 100 and located in the first well region 102 , and the RESURF region 120 partially overlaps with the third isolation structure 200c. In one embodiment, the RESURF region 120 is embedded in the double diffusion region 110 to form a PN junction in the horizontal direction, that is, the RESURF region 120 has the first conductivity type. In this embodiment, the RESURF region 120 can reduce the electric field under the third isolation structure 200c located between the drain region 108 and the gate 304 to reduce the electron collision probability, so that the distance between the drain region 108 and the gate 304 The breakdown voltage increases.

The base region 130 is, for example, disposed in the substrate 100 and located in the second well region 104 . In addition, the base region 130 has the first conductivity type, that is, the base region 130 is a P-type well region. In this embodiment, the base region 130 is adjacent to the source region 106 .

Fig. 2 is the partial sectional view of the semiconductor element of the second embodiment of the present invention 3 is a schematic partial cross-sectional view of a semiconductor device according to a third embodiment of the present invention, and FIG. 4 is a schematic partial cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

”字的形狀；圖2示出的降低表面電場區120較靠近汲極區108，且使得雙重擴散區110具有接近“ㄈ”字的形狀；圖3示出的降低表面電場區120則是實質位於閘極結構300與汲極區108之間而埋入於雙重擴散區110中；圖4示出的降低表面電場區120則在水平方向上(與基底100的法線方向垂直的方向)延伸，且將雙重擴散區110所截斷，使得雙重擴散區110可包括有第一雙重擴散區與第二雙重擴散區。值得說明的是，圖1至圖4各自示出的實施例皆有可降低位於汲極區108至閘極304之間的第三隔離結構200c下方的電場而使電子碰撞機率下降，使得汲極區108至閘極304的崩潰電壓提高的效果。 Please refer to FIG. 1 to FIG. 4 at the same time, each of which shows a variant embodiment of the arrangement of the REDSURF region 120 . In detail, FIG. 1 to FIG. 4 all show that the RESURF region 120 is located below the third isolation structure 200c and at least partially overlaps with the second isolation structure 200b, and the RESURF region 120 is embedded in the double diffusion District 110. However, the RESURF region 120 shown in FIG. 1 is closer to the gate structure 300, and makes the double diffusion region 110 have a nearly "

The shape of the word "; the RESURF region 120 shown in FIG. 2 is closer to the drain region 108, and makes the double diffusion region 110 have a shape close to the word "ㄈ"; the RESURF region 120 shown in FIG. 3 is substantially Located between the gate structure 300 and the drain region 108 and buried in the double diffusion region 110; the RESURF region 120 shown in FIG. 4 extends in the horizontal direction (direction perpendicular to the normal direction of the substrate 100) , and the double diffusion region 110 is cut off, so that the double diffusion region 110 can include a first double diffusion region and a second double diffusion region. It is worth noting that the respective embodiments shown in FIGS. The electric field under the third isolation structure 200 c located between the drain region 108 and the gate 304 reduces the electron collision probability, so that the breakdown voltage from the drain region 108 to the gate 304 is improved.

To sum up, the manufacturing method of the semiconductor element provided by the present invention is to form the RESURF region after the isolation structure is formed, and can choose to perform the process of forming the dielectric layer for the medium-voltage semiconductor element and form the low-voltage semiconductor element. Semiconductor element The process of forming the dielectric layer of the component or the process of forming the source region and the drain region are formed together. Compared with the prior art, which generally forms the reduced surface electric field region before forming the isolation structure, it has process flexibility. , can also reduce the process cost.

10: Semiconductor components

100: base

102: The first well area

104: The second well area

106: source region

108: Drain area

110:Double diffusion zone

120: Reduced surface electric field area

130: matrix area

200: isolation structure

200a: first isolation structure

200b: second isolation structure

200c: The third isolation structure

300: gate structure

302: gate oxide layer

304: gate

306: gap wall

Claims (9)

A method of manufacturing a semiconductor device, comprising: providing a substrate with a first conductivity type, wherein a first well region with the first conductivity type and a second well with the first conductivity type are formed in a region of the substrate defined as a high-voltage semiconductor element region and a double diffused region having a second conductivity type, wherein the second well region and the double diffused region are located in the first well region; forming isolation structures in the substrate; performing a first oxidation process in regions of the substrate defined as medium voltage semiconductor components; performing a second oxidation process in a region of the substrate defined as a low-voltage semiconductor element; forming a gate structure on the substrate, wherein the gate structure covers a portion of the isolation structure; and forming a source region with the second conductivity type and a drain region with the second conductivity type in the substrate, wherein the source region is located in the first well region and disposed at the gate one side of the gate structure, the drain region is located in the double diffusion region and disposed on the other side of the gate structure, Wherein the manufacturing method of the semiconductor device further includes forming a RESURF region in the first well region after forming the isolation structure in the substrate, Wherein the RESURF region is embedded in the double diffusion region, and the RESURF region is formed when the first oxidation process is performed, the second oxidation process is performed, or the source region and the drain are formed. The polar region is formed in the step. The method for manufacturing a semiconductor device according to claim 1, wherein the double diffusion region is formed in the first well region by sequentially performing a first ion implantation process and a second ion implantation process. The method for manufacturing a semiconductor element according to claim 2, wherein the implantation dose in the first ion implantation process is 4.8E12cm ^-2 ~ 7.2E12cm ^-2 , and the implantation energy is 960keV ~ 1440keV; The implantation dose in the second ion implantation process is 5.92E12cm ^-2 ~8.88E12cm ^-2 , and the implantation energy is 280keV~420keV. The method for manufacturing a semiconductor element according to claim 1, wherein the method for forming the RESURF region includes performing a third ion implantation process, and the implanted dose in the third ion implantation process is 2.8E12cm ^{− 2} ~4.2E12cm ^-2 , and the implanted energy is 240keV~360keV. The method for manufacturing a semiconductor element according to claim 1, wherein the isolation structure includes a first isolation structure, a second isolation structure, and a third isolation structure, and the first isolation structure covers part of the second well region and Located on one side of the gate structure, the second isolation structure covers part of the double diffusion region and located on the other side of the gate structure, and the third isolation structure is located on the first isolation structure Between the second isolation structure, part of the third isolation structure is covered by the gate structure. The method of manufacturing a semiconductor device as claimed in claim 5, wherein the RESURF region partially overlaps with the third isolation structure. The method for manufacturing a semiconductor element according to claim 1, wherein the RESURF region is close to the gate structure, and the double diffusion region has a U-shape. The method of manufacturing a semiconductor device according to claim 1, wherein the RESURF region is close to the drain region, and the double diffusion region has a ㄈ shape. The method of manufacturing a semiconductor device according to claim 1, wherein the RESURF region is buried in the double diffusion region.

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