TWI789549B - Memory chip, memory module and method for pseudo-accessing memory bbank thereof - Google Patents

Abstract

The present invention provides a memory chip includes a plurality of memory banks, a plurality of address pins, and a pseudo-address determining circuit. The plurality of address pins is arranged for receiving a plurality of address signals corresponding to the plurality of memory banks, respectively. The pseudo-address determining circuit has a plurality of input terminals coupled to the plurality of address pins, respectively, and a plurality of output terminals coupled to the plurality of memory banks. The pseudo-address determining circuit generates a pseudo-address table for the plurality of memory banks when the memory chip is powered-up. The pseudo-address table has a plurality of pseudo-addresses corresponding to the plurality of memory banks, respectively. The present invention also provides a memory module that incorporates said memory chip and a method for pseudo-accessing memory banks of said memory chip.

Description

Memory chip, memory module and method for falsely accessing its memory bank

The invention relates to a memory chip, in particular to a memory chip capable of falsely accessing its memory bank.

Random Access Memory (RAM) is a form of computer data storage used to store data and machine code currently in use. Random access memory devices allow data to be read or written in approximately the same amount of time regardless of the physical location of the data within the memory.

RAM contains multiplexing and demultiplexing circuits for wiring data to address memory to read or write entries. Usually, the same address can access more than one bit of storage.

To be useful, memory cells must be both readable and writable. In RAM devices, multiplexing and demultiplexing circuits are used to select memory cells. Typically, a RAM device has a set of address lines A0...An, and for each bit combination that can be applied to these address lines, a corresponding set of memory cells can be enabled. Because of this addressing, RAM devices almost always have a power-of-two memory capacity.

Many RAM systems have a hierarchy of memory cells, banks, ranks, modules, and channels. Please refer to FIG. 1 , which shows a block diagram of a hierarchical structure of a RAM system. A central processing unit (CPU) 1 is coupled to one or more memory channels 2a-2b. Each memory channel in the memory channels 2a~2b can include multiple memory modules 3. Each memory module 3 may have one or two memory columns 4 including several memory chips 5 . Each memory chip 5 includes several memory banks 6 . The memory bank 6 is formed by a number of memory cells 7 arranged in an array.

Manufacturers of memory devices are used to guaranteeing their products with a limited number of years or even a lifetime warranty. Warranty years are usually estimated based on the concept that the total number of access operations that can be performed by the memory device can be evenly distributed among all banks of the memory device. In some oversimplified implementations, an application may have very low memory requirements (much less than the system is equipped with) but require very frequent memory accesses, such applications may access certain memory banks more frequently than others. Ultimately, this will lead to premature decay of heavily accessed memory banks.

Therefore, the object of the present invention is to provide a memory chip which can falsely access its memory bank to prevent premature failure of the memory bank.

In order to achieve the above object, according to one aspect of the present invention, a memory chip is provided. The memory chip includes: a plurality of memory banks; a plurality of address pins, which are used to receive a plurality of address signals respectively corresponding to the memory banks; and a virtual address determination circuit, which has a plurality of input interfaces Pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, the output pins are coupled to the memory banks, when the memory chip is powered on, the dummy bit The address determination circuit generates a virtual address table for the memory banks, wherein the virtual address table has a plurality of virtual addresses respectively corresponding to the memory banks, and each of the memory banks is set are accessed according to the corresponding virtual address.

In order to achieve the above object, according to another aspect of the present invention, a memory module is proposed. The memory module includes: a printed circuit board; a control circuit disposed on the printed circuit board; and a plurality of memory chips disposed on the printed circuit board and coupled to the control circuit, wherein the memories Each memory chip in the chip includes: a plurality of memory banks; a plurality of address pins, which are used to receive a plurality of address signals respectively corresponding to the memory banks; and a virtual address, which determines the circuit which has A plurality of input pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, and the output pins are coupled to the memory banks, when the memory chip is powered on , the virtual address determining circuit generates a virtual address table for the memory banks, wherein the virtual address table has a plurality of virtual addresses respectively corresponding to the memory banks, and each of the memory banks Banks are configured to be accessed according to corresponding virtual addresses.

In order to achieve the above object, according to another aspect of the present invention, a method for falsely accessing multiple memory banks of a memory chip is proposed. The method includes: generating a virtual address table for the memory banks when the memory chip is powered on, wherein the virtual address table is stored in a memory, and each of the memory banks is Corresponding to a virtual address in the virtual address table; receiving a control signal having an address signal indicating the destination memory bank to which the control signal is to be sent; according to the destination memory bank indicating the destination The address signal and the virtual address table determine a virtual address; and redirect the control signal to a pseudo memory bank indicated by the virtual address.

Through these configurations, the memory chip, the memory module and the method for falsely accessing the memory banks of a memory chip can change the virtual bits of the memory banks every time the memory chip is powered on address table. In this way, the frequency of accessing each bank can be evenly distributed among all banks, regardless of the design or implementation of the application. In other words, the present invention can prevent premature decay of the memory bank caused by heavy access.

1: CPU

2a, 2b: memory channel

3: Memory module

4: Memory column

5: Memory chip

6: Memory bank

7: Memory unit

10: Memory chip

11, 12, 13, 14: memory bank

15: Virtual address decision circuit

26, 36: Controller

20, 30: memory chip

40, 50, 60: memory modules

41: Printed circuit board

42: Control circuit

P1, P2: Pins

S11, S12, S13, S14, S_C: signal

1100: method

1101, 1102, 1104, 1106: steps

The structure and technical means adopted by the present invention to achieve the above and other objects can be best understood by referring to the detailed description and drawings of the following preferred embodiments, wherein FIG. 1 is a block diagram of a traditional RAM system hierarchy.

FIG. 2 is a block diagram of a memory chip according to an embodiment of the present invention.

FIG. 3 is an address table of a memory chip according to an embodiment of the present invention.

FIG. 4 is a virtual address table of a memory chip according to different embodiments of the present invention.

FIG. 5 is a virtual address table of a memory chip according to different embodiments of the present invention.

FIG. 6 is a block diagram and exemplary virtual address table of a memory chip according to another embodiment of the present invention.

FIG. 7 is a block diagram and exemplary virtual address table of a memory chip according to yet another embodiment of the present invention.

FIG. 8 is a memory module according to different embodiments of the present invention.

FIG. 9 is a memory module according to different embodiments of the present invention.

FIG. 10 is a memory module according to different embodiments of the present invention.

FIG. 11 is a flowchart of a method for falsely accessing a bank of a memory chip according to an exemplary embodiment of the present invention.

The invention will now be described by way of some of its preferred embodiments and with reference to the accompanying drawings.

Please refer to FIG. 2 , which shows a block diagram of a memory chip according to an embodiment of the present invention. In FIG. 2 , the memory chip 10 includes a plurality of memory banks 11 - 14 , a plurality of address pins P1 - P2 and a virtual address determination circuit 15 .

The address pins P1-P2 are used to receive the address signals S11-S14 respectively corresponding to the memory banks 11-14. That is to say, the address signals S11˜S14 will constitute 4 possible results of the voltage levels of the address pins P1˜P2. Please refer to FIG. 3 , which is an address table of the memory chip 10 according to an embodiment of the present invention. In FIG. 3, the address signal S11 makes the voltage levels of both the position pins P1 and P2 relatively high (indicated by the number "1"), and the address signal S12 makes the voltage levels of the address pin P1 relatively high. High and the voltage level of the address pin P2 is relatively low (indicated by the number "0"), the address signal S13 makes the voltage level of the address pin P1 relatively low and the voltage level of the address pin P2 is relatively low High, the address signal S14 makes the voltage levels of both the position pins P1 and P2 relatively low. In this embodiment, if an address signal is received and the voltage levels of both address pins P1 ˜ P2 are relatively high, it means that the address signal S11 is received. Then the memory chip 10 will determine that the bank 11 is a target bank for an upcoming operation. In the previous embodiments, it is also helpful to think of the position pin P1 as the row address and the address pin P2 as the column pin. In other words, the address pins P1 are set to receive the voltage level used to determine which row of the array of the memory banks 11-14 the target bank is located in, and the address pin P2 is set to To receive the voltage level used to determine which column in the array of the memory banks 11-14 the target memory bank is located in. Please note that the number of address pins in this embodiment is for illustration purposes only, and does not mean to limit the present invention. Without departing from the spirit of the present invention, those skilled in the art may make modifications and changes according to the actual design and requirements of the application.

Please refer to FIG. 2 again. In FIG. 2 , the virtual address determining circuit 15 has a plurality of input pins and a plurality of output pins. The input pins of the virtual address determining circuit 15 are respectively coupled Connect to these address pins P1~P2. The output pins of the virtual address determining circuit 15 are coupled to the memory banks 11 - 14 . In another design, the output pins of the virtual address determining circuit 15 may be coupled to the memory banks 11 - 14 through a row of address controllers and a row of address controllers. In this way, the output pin coupled to the row address controller will send a row select signal to the row address controller to determine which row of the array of memory banks 11-14 the target bank is located in , and the output pin coupled to the column address controller will send a column selection signal to the column address controller to determine which column of the array of the memory banks 11-14 the target memory bank is located in . In any of the above designs, the signal output from the output interface of the virtual address determining circuit 15 will determine the address of the memory bank to be operated on.

In addition, whenever the memory chip 10 is powered on, the virtual address determination circuit 15 will generate a virtual address table for the memory banks 11-14. The virtual address table can then be stored in a register and looked up in the register. For example, please refer to Figure 3, Figure 4 and Figure 5 together. 4 and 5 illustrate virtual address tables of the memory chip 10 according to different embodiments of the present invention. In the virtual address table of FIG. 4, the virtual address table is generated such that the memory banks 11-14 correspond to the address signals S11-S14, and the address signals S11-S14 correspond to the bits in FIG. For the address table, these memory banks 11-14 represent different column addresses through shifting. In FIG. 4, the address signal S11 now corresponds to memory bank 12, the address signal S12 now corresponds to memory bank 13, the address signal S13 now corresponds to memory bank 14, and the address signal S14 now corresponds to memory bank 14. Library 11. To be precise, the corresponding positions of the memory banks 11-14 in FIG. 4 are the corresponding positions of the memory banks 11-14 in FIG. 3 by "circularly shifting" one step downward. In other words, in the embodiment of FIG. 4, the memory bank 12 can only be accessed through the address signal S13. When the developer intends to access the memory bank 13, he will change to "false access" to the memory bank 12. In applications where the memory bank 13 is severely over-accessed, the above-mentioned virtual address table decision circuit 15 generated by the virtual address will secretly transfer some of the operational burden of the memory bank 13 to the memory bank 12 without any further configuration, so that this approach can prevent the memory bank 13 from decaying in advance. Whenever the memory chip 10 is powered on, the virtual The virtual address determination circuit 15 will generate a new virtual address table. This will distribute the load of bank 13, which would otherwise be heavily accessed, to another bank.

In FIG. 5 , the virtual address table is randomly generated by the virtual address determining circuit 15 . For example, the virtual address is generated by first copying the address table and then replacing the column addresses of the banks 11-14 indicating the copied address table with the randomly ordered column addresses of the banks 11-14 surface. Statistically speaking, the reliability of the memory chip 10 will increase if the virtual address is randomly generated during the iterative growth of the virtual address.

Please refer to FIG. 6 , which shows a block diagram of a memory chip and an exemplary virtual address table according to another embodiment of the present invention. Please note that the memory chip 20 shares some elements with the memory chip 10 . If the components in the memory chip 20 are substantially the same as the components in the memory chip 10, they will be denoted by the same symbols to avoid confusion. In FIG. 6 , the memory chip 20 further includes a controller 26 . The controller 26 is coupled to the virtual address determining circuit 15 and is used for sending a control signal S_C having an address signal indicating the destination memory bank to which the control signal S_C is to be sent. For example, the controller 26 is about to write data into the storage bank 11 . The controller 26 sends out the control signal S_C indicating the write operation and the address signal S11 indicating that the target memory bank is the memory bank 11 . In this embodiment, the virtual address determining circuit 15 then determines the virtual address of the memory bank 11 , that is, the memory bank 13 according to the position signal S11 and the virtual address table in FIG. 6 . The virtual address determining circuit 15 then redirects the control signal S_C to the memory bank 13 .

Please refer to FIG. 7 , which shows a block diagram of a memory chip and an exemplary virtual address table according to another embodiment of the present invention. Please note that a memory chip 30 shares some elements with the memory chip 10 and the memory chip 20 . If the components in the memory chip 30 are substantially the same as those in the memory chip 10 and the memory chip 20 , they are denoted by the same symbols to avoid confusion. In FIG. 7 , the memory chip 30 further includes a controller 36 . The controller 36 is coupled to the virtual address determining circuit 15 and the memory banks 11 - 14 . The controller 36 is used to send a control signal The number S_C has an address signal indicating the destination memory bank to which the control signal S_C will be sent. In this embodiment, the address signal indicating the destination bank is sent to the virtual address determination circuit 15 . The virtual address determining circuit 15 determines a virtual address according to the received address signal and the virtual address table, and sends back the address signal corresponding to the virtual address to the controller 36 . The controller 36 then redirects the control signal S_C to the dummy bank indicated by the virtual address. For example, the controller 26 is about to write data into the storage bank 11 . The controller 36 sends out a control signal S_C indicating a write operation and an address signal S11 indicating that the destination bank is the bank 11 . In this embodiment, the virtual address determining circuit 15 then determines the virtual address of the memory bank 11 , that is, the memory bank 14 according to the position signal S11 and the virtual address table in FIG. 7 . The virtual address determining circuit 15 then sends the address signal S14 back to the controller 36 . The controller 36 then redirects the control signal S_C to the memory bank 14 .

The above memory chips 10, 20 and 30 can be further combined into a memory module. Please refer to FIG. 8 , which shows a memory module according to an embodiment of the present invention. In FIG. 8 , the memory module 40 includes a printed circuit board 41 , a control circuit 42 and a plurality of memory chips 10 . The control circuit 42 is disposed on the printed circuit board 41 and is used for selecting a target memory chip 10 . The memory chips 10 are disposed on the printed circuit board 41 and connected to the control circuit 42 . The structure and operation of the memory chips 10 can refer to the above paragraphs. For brevity, a detailed description will be omitted here.

Please refer to FIG. 9 , which shows a memory module according to an embodiment of the present invention. Please note that the memory module 50 shares some components with the memory module 40 . If the components in memory module 40 are substantially the same as those in memory module 50, they will be denoted by the same symbols to avoid confusion. In FIG. 9 , the memory module 50 includes a printed circuit board 41 , a control circuit 42 and a plurality of memory chips 20 . The structure and operation of the memory chips 20 can refer to the above paragraphs. For brevity, a detailed description will be omitted here.

Please refer to FIG. 10 , which shows a memory module according to an embodiment of the present invention. Please note that the memory module 60 shares some components with the memory module 40 and the memory module 50 . If the components in the memory module 60 are substantially the same as those in the memory module 40 and the memory module 50, they will be denoted by the same symbols to avoid confusion. In FIG. 10 , the memory module 60 includes a printed circuit board 41 , a control circuit 42 and a plurality of memory chips 30 . The structure and operation of the memory chips 30 can refer to the above paragraphs. For brevity, a detailed description will be omitted here.

The virtual address determining circuit 15 can also be disabled by a test mode enable signal. When testing the reliability of the memory chip 10, it is very important for the tester to be able to test the actual target memory bank without false access. Disabling the virtual address determination circuit 15 using the test mode enable signal provides flexibility in the application of the memory chip 10 , 20 or 30 .

Please refer to FIG. 11 , which is a flow chart of a method for falsely accessing a bank of a memory chip according to an exemplary embodiment of the present invention. If the results are essentially the same, the steps do not need to be performed in the exact order shown in Figure 11. The exemplary method can be composed of the memory chip 10 shown in FIG. 2 , the memory chip 20 shown in FIG. 6 , the memory chip 30 shown in FIG. 7 , and the memory module 40 in FIG. 8 , the module 50 in FIG. 9 and the memory module 60 in FIG. 10 are implemented. The steps of the method can be summarized as follows.

Step 1101: Generate a virtual address table for the memory when the memory chip is powered on.

Step 1102: Receive a control signal with an address signal indicating the destination bank to which the control signal is to be sent.

Step 1104: Determine a virtual address indicating the destination memory bank and the virtual address table according to the address signal.

Step 1106: Redirect the control signal to the pseudo memory bank indicated by the virtual address.

In the method 1100, the virtual address table is stored in a memory, and each of the memory banks corresponds to a virtual address in the virtual address table. Step 1101 can be performed by the virtual address determining circuit 15 of the memory chip 10 , 20 or 30 . Step 1102 can be performed by the virtual address determining circuit 15 . The address signal is sent by the controller 26 , or step 1104 can be executed by the virtual address determining circuit 15 of the memory chip 10 , 20 or 30 . Step 1106 can be performed by the virtual address determining circuit 15 or the controller 26 or 36 .

The invention has been described above in terms of some preferred embodiments of the invention, and it should be understood that the preferred embodiments are illustrative only and are not intended to limit the invention in any way, and may be modified without departing from the invention. Many changes and modifications are made in the case of the embodiment. It is intended that the scope and spirit of the invention be limited only by the appended claims.

10: Memory chip

11, 12, 13, 14: memory bank

15: Virtual address decision circuit

P1, P2: Pins

S11, S12, S13, S14: signal

Claims (9)

A memory chip, including: a plurality of memory banks; a plurality of address pins, which are used to receive a plurality of address signals respectively corresponding to the memory banks; and a virtual address determination circuit, which has a plurality of inputs Pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, the output pins are coupled to the memory banks, when the memory chip is powered on, the virtual The address determination circuit alternates a virtual address table for the memory banks, wherein the virtual address table has a plurality of virtual addresses respectively corresponding to the memory banks, and each of the memory banks is set be accessed according to the corresponding virtual address, wherein the virtual address determination circuit is based on one of the address signals corresponding to the address indicating a destination memory bank in the memory banks and the virtual bit An address table is used to determine the virtual address for access, and the virtual address indicates the address of a pseudo-memory bank, and the target memory bank and the pseudo-memory bank are different memory banks. The memory chip as described in claim 1, further comprising: a controller coupled to the virtual address determination circuit and used to send a control signal having an address signal corresponding to the target memory bank, the address signal Indicating the destination memory bank to which the control signal is to be sent, wherein the virtual address determining circuit redirects the control signal to the pseudo memory bank indicated by the virtual address. The memory chip as described in claim 1, further comprising: a controller coupled to the virtual address determination circuit and used to send a control signal having an address signal corresponding to the target memory bank, the address signal indicating the destination bank to which the control signal is to be sent, Wherein the controller redirects the control signal to the pseudo memory bank indicated by the virtual address. The memory chip as claimed in claim 1, wherein the virtual address determining circuit is disabled in response to a test mode enable signal. A memory module includes: a printed circuit board; a control circuit disposed on the printed circuit board; and a plurality of memory chips disposed on the printed circuit board and coupled to the control circuit, wherein the memories Each memory chip in the body chip includes: a plurality of memory banks; a plurality of address pins, which are used to receive a plurality of address signals respectively corresponding to the memory banks; and a virtual address, which determines the circuit There are a plurality of input pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, and the output pins are coupled to the memory banks, when the memory chip is powered on , the virtual address determining circuit alternates a virtual address table for the memory banks, wherein the virtual address table has a plurality of virtual addresses respectively corresponding to the memory banks, and each of the memory banks A memory bank is configured to be accessed according to corresponding virtual addresses, wherein the virtual address determining circuit randomly generates the virtual address table for the memory banks, wherein the virtual address determining circuit and according to instructions for the memory banks One of the address signals corresponding to the address of a target memory bank in the bank and the virtual address table to determine the virtual address for access, and the virtual address indicates a pseudo memory bank The address of the target memory bank and the pseudo memory bank are different memory banks. The memory module as described in claim 5, wherein each of the memory chips further comprises: a controller coupled to the virtual address determination circuit and used to send a control signal having an address signal corresponding to the destination memory bank, the address signal indicating the destination memory bank to which the control signal is to be sent, Wherein the virtual address determining circuit redirects the control signal to the pseudo memory bank indicated by the virtual address. The memory module as described in claim 5, wherein each memory chip in the memory chips further includes: a controller coupled to the virtual address determination circuit and used to issue a memory bank with the target a control signal corresponding to an address signal indicating the destination bank to which the control signal is to be sent, wherein the controller redirects the control signal to the pseudo memory indicated by the virtual address library. The memory module as claimed in claim 5, wherein the virtual address determining circuit is disabled in response to a test mode enabling signal. A method for falsely accessing memory banks of a memory chip, comprising: switching a virtual address table for the memory banks when the memory chip is powered on, wherein the virtual address table is stored in in a memory, and each of the memory banks corresponds to a virtual address in the virtual address table; receiving a control signal having an address signal instructing the control the destination memory bank to which the signal is to be sent; determine a virtual address based on the address signal indicating the destination memory bank and the virtual address table; and redirect the control signal to a virtual address indicated by the virtual address A pseudo-memory bank, the pseudo-memory bank is different from the target memory bank.

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