TWI786855B - Anti-fuse strucutre - Google Patents

Abstract

An anti-fuse structure including a substrate, a conductive layer, an anti-fuse material layer, a dielectric layer, and first contacts is provided. The conductive layer is disposed on the substrate. The anti-fuse material layer is disposed on the conductive layer. The dielectric layer is disposed on the anti-fuse material layer. The first contacts are disposed in the dielectric layer. The anti-fuse material layer is located between the first contacts the conductive layer.

Description

antifuse structure

Embodiments of the present invention relate to a semiconductor structure, and more particularly to an antifuse structure.

Currently, an antifuse element has been developed, which has an antifuse material layer. In an initial state, the anti-fuse material layer has a high resistance value, and the anti-fuse element is in an open state. When the anti-fuse element is operated, the anti-fuse material layer will break down to form a conductive path, and the anti-fuse element is in a short circuit state. However, how to reduce the area of the anti-fuse element and improve the flexibility of the design and application of the anti-fuse element is the goal of ongoing efforts.

The present invention provides an antifuse structure, which can have a smaller device area and be more flexible in design and application.

The invention provides an antifuse structure, which includes a substrate, a conductive layer, an antifuse material layer, a dielectric layer and a plurality of first contact windows. The conductive layer is disposed on the substrate. A layer of antifuse material is disposed on the conductive layer. A dielectric layer is disposed on the antifuse material layer. A plurality of first contact windows are disposed in the dielectric layer. The antifuse material layer is located between the plurality of first contact holes and the conductive layer.

According to an embodiment of the present invention, the above antifuse structure may further include a second contact window. The second contact window is disposed in the dielectric layer and electrically connected to the conductive layer.

According to an embodiment of the present invention, in the above antifuse structure, the second contact window may pass through the antifuse material layer.

According to an embodiment of the present invention, the antifuse structure may further include wires. The wire is electrically connected to the second contact window.

According to an embodiment of the present invention, in the above antifuse structure, the conductive layer can be a doped region, a metal silicide layer, a dummy gate or a wire.

According to an embodiment of the present invention, in the aforementioned antifuse structure, the antifuse structure may be a one-time programmable (OTP) memory or a physically unclonable function (PUF) generator .

According to an embodiment of the present invention, in the above antifuse structure, the antifuse structure may be a physically non-replicable function generator, and the antifuse structure may include a plurality of contact window groups. Each contact group may include any two first contacts among the plurality of first contacts.

According to an embodiment of the present invention, in the above antifuse structure, the plurality of contact window groups do not share the same first contact window.

According to an embodiment of the present invention, in the above antifuse structure, the material of the antifuse material layer is, for example, silicon nitride (SiN), silicon oxynitride (SiON) or silicon carbide nitride (SiCN).

According to an embodiment of the present invention, the antifuse structure may further include a plurality of wires. The wire is electrically connected to the first contact window.

Based on the above, since the antifuse structure proposed by the present invention is operated by applying a voltage to the first contact window and the conductive layer, the antifuse structure can have a smaller device area, thereby increasing the device density. In addition, the antifuse material layer is located between the plurality of first contact windows and the same conductive layer, so that a plurality of OTP memory cells can be formed, and the design and application of the antifuse structure can be more flexible. In addition, the manufacturing process of the antifuse structure can be integrated with other semiconductor manufacturing processes, thereby reducing the complexity of the manufacturing process.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

1A to 1F are cross-sectional views of the manufacturing process of the antifuse structure according to an embodiment of the present invention.

Referring to FIG. 1A , a substrate 100 is provided. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 100 may have a first conductivity type (eg, P-type). Herein, the first conductivity type and the second conductivity type are different conductivity types. That is, the first conductivity type and the second conductivity type may be one and the other of the P-type conductivity and the N-type conductivity, respectively. In this embodiment, the first conductivity type is an example of a P-type conductivity type, and the second conductivity type is an example of an N-type conductivity type, but the invention is not limited thereto. In other embodiments, the first conductivity type may be N-type conductivity, and the second conductivity type may be P-type conductivity.

In addition, an isolation structure 102 may be formed in the substrate 100 . The isolation structure 102 may be a shallow trench isolation (STI) structure. The material of the isolation structure 102 is, for example, silicon oxide. In some embodiments, a well region 104 may be formed in the substrate 100 . The well region 104 may have a second conductivity type (eg, N type). Next, a conductive layer 106 is formed in the substrate 100 . Conductive layer 106 may be located in well region 104 . In this embodiment, the conductive layer 106 can be a doped region, and the doped region can have a second conductivity type (eg, N type).

Additionally, a transistor 108 may be formed on the substrate 100 . The conductive layer 106 can be located on one side of the isolation structure 102 , and the transistor 108 can be located on the other side of the isolation structure 102 . In some embodiments, the transistor 108 may be a metal oxide semiconductor (MOS) transistor. For example, the transistor 108 may include a gate 110 , a gate dielectric layer 112 , a doped region 114 and a doped region 116 . The gate 110 is located on the substrate 100 . The gate dielectric layer 112 is located between the gate 110 and the substrate 100 . The doped region 114 and the doped region 116 are located in the substrate 100 on both sides of the gate 110 . The doped region 114 and the doped region 116 can have a second conductivity type (eg, N type). In addition, the conductive layer 106 , the doped region 114 and the doped region 116 can be formed simultaneously by the same process (eg, ion implantation process). In some embodiments, the transistor 108 may further include a spacer 118 . The spacer 118 is located on the sidewall of the gate 110 .

Referring to FIG. 1B , an antifuse material layer 120 is formed on the conductive layer 106 . In some embodiments, the layer of antifuse material 120 may be conformally formed on the conductive layer 106 . Additionally, a layer of antifuse material 120 may cover the transistor 108 . The antifuse material layer 120 may be an etch stop layer. The material of the antifuse material layer 120 is, for example, silicon nitride, silicon oxynitride, silicon carbide nitride or a combination thereof, but the invention is not limited thereto. A method for forming the antifuse material layer 120 is, for example, chemical vapor deposition.

Next, a dielectric layer 122 is formed on the antifuse material layer 120 . The material of the dielectric layer 122 is, for example, silicon oxide, but the invention is not limited thereto. As long as the material of the dielectric layer 122 and the material of the antifuse material layer 120 have a high etching selectivity in the etching process, it falls within the scope of the present invention. The dielectric layer 122 is formed by chemical vapor deposition, physical vapor deposition or spin coating, for example.

Referring to FIG. 1C , a patterned photoresist layer 124 may be formed on the dielectric layer 122 . The patterned photoresist layer 124 can be formed by a photolithography process. Next, a portion of the dielectric layer 122 can be removed by using the patterned photoresist layer 124 as a mask. Thereby, a plurality of openings OP1 can be formed in the dielectric layer 122 . The opening OP1 can expose a portion of the antifuse material layer 120 . A method for removing part of the dielectric layer 122 is, for example, a dry etching method.

Referring to FIG. 1D , the patterned photoresist layer 124 can be removed. The removal method of the patterned photoresist layer 124 is, for example, dry stripping or wet stripping.

Next, a patterned photoresist layer 126 may be formed on the dielectric layer 122 . The patterned photoresist layer 126 can be filled into the opening OP1. The patterned photoresist layer 124 can be formed by a photolithography process. Then, a portion of the dielectric layer 122 and a portion of the antifuse material layer 120 can be removed by using the patterned photoresist layer 126 as a mask. Thereby, the openings OP2 - OP5 can be formed in the dielectric layer 122 . The opening OP2 can expose part of the conductive layer 106 . In this embodiment, one opening OP2 is taken as an example, but the present invention is not limited thereto. In other embodiments, the number of openings OP2 may be multiple. The opening OP3 can expose a part of the gate 110 . The opening OP4 can expose part of the doped region 114 . The opening OP4 can expose a portion of the doped region 116 . The removal method of a part of the dielectric layer 122 and a part of the antifuse material layer 120 is, for example, a dry etching method.

Referring to FIG. 1E , the patterned photoresist layer 126 can be removed. The removal method of the patterned photoresist layer 126 is, for example, a dry stripping method or a wet stripping method. In this embodiment, the opening OP1 is formed first, and then the openings OP2 - OP5 are formed, but the invention is not limited thereto. In other embodiments, the openings OP2 - OP5 may be formed first, and then the opening OP1 may be formed.

Next, the contact windows CT1 - CT5 may be formed in the openings OP1 - OP5 respectively. Thereby, the contact windows CT1 -CT5 can be formed in the dielectric layer 122 . The contact window CT1 may directly contact the antifuse material layer 120 . The number of contact windows CT1 is multiple. In addition, a contact window CT1, the antifuse material layer 120 and the conductive layer 106 can form an OTP memory cell. The contact window CT2 can pass through the antifuse material layer 120 and can be electrically connected to the conductive layer 106 . The contact window CT2 may directly contact the conductive layer 106 . In this embodiment, one contact window CT2 is taken as an example, but the present invention is not limited thereto. In other embodiments, the number of contact windows CT2 may be multiple. The contact window CT3 can pass through the antifuse material layer 120 and can be electrically connected to the gate 110 . The contact window CT3 can directly contact the gate 110 . The contact window CT4 can pass through the antifuse material layer 120 and can be electrically connected to the doped region 114 . The contact window CT4 can directly contact the doped region 114 . The contact window CT5 can pass through the antifuse material layer 120 and can be electrically connected to the doped region 116 . The contact window CT5 may directly contact the doped region 116 .

The contact windows CT1 -CT5 may respectively have a single-layer structure or a multi-layer structure. In this embodiment, the contact windows CT1 -CT5 are multi-layer structures as an example. For example, the contact window CT1 may include a conductive layer 128a and a barrier layer 130a. The conductive layer 128 a is located in the dielectric layer 122 . The barrier layer 130 a is located between the conductive layer 128 a and the antifuse material layer 120 and between the conductive layer 128 a and the dielectric layer 122 . The contact window CT2 may include a conductive layer 128b and a barrier layer 130b. The conductive layer 128b is located in the dielectric layer 122 . The barrier layer 130b is located between the conductive layer 128b and the conductive layer 106 and between the conductive layer 128b and the dielectric layer 122 . The contact window CT3 may include a conductive layer 128c and a barrier layer 130c. The conductive layer 128c is located in the dielectric layer 122 . The barrier layer 130c is located between the conductive layer 128c and the gate 110 and between the conductive layer 128c and the dielectric layer 122 . The contact window CT4 may include a conductive layer 128d and a barrier layer 130d. The conductive layer 128d is located in the dielectric layer 122 . The barrier layer 130d is located between the conductive layer 128d and the doped region 114 and between the conductive layer 128d and the dielectric layer 122 . The contact window CT5 may include a conductive layer 128e and a barrier layer 130e. The conductive layer 128e is located in the dielectric layer 122 . The barrier layer 130 e is located between the conductive layer 128 e and the doped region 116 and between the conductive layer 128 e and the dielectric layer 122 . The material of the conductive layer 128 a - the conductive layer 128 e is, for example, metal such as tungsten. Materials of the barrier layers 130 a - 130 e are, for example, titanium, titanium nitride or a combination thereof.

In this embodiment, the contact windows CT1 -CT5 can be formed simultaneously through the same manufacturing process, but the invention is not limited thereto. For example, a conductive material layer (not shown) and a barrier material layer (not shown) can be sequentially formed in the openings OP1-OP5, and then the positions in the openings OP1-OP5 are removed by a chemical mechanical polishing process. The outer conductive material layer and the barrier material layer form the contact windows CT1-CT5. In other embodiments, the opening OP1 and the contact window CT1 may be formed first, and then the openings OP2 - OP5 and the contact windows CT2 - CT5 are formed. In other embodiments, the openings OP2 - OP5 and the contact windows CT2 - CT5 may be formed first, and then the opening OP1 and the contact window CT1 are formed.

Referring to FIG. 1F , wires L1 ˜ L5 can be formed. The wires L1˜L5 can be electrically connected to the contact windows CT1˜CT5 respectively. The material of the wires L1 to L5 is, for example, metal such as aluminum. The wires L1 -L5 can be formed by a deposition process and a patterning process.

Hereinafter, the antifuse structure 10 of this embodiment will be described with reference to FIG. 1F . In addition, although the method for forming the anti-fuse element 10 is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIG. 1F , the antifuse structure 10 includes a substrate 100 , a conductive layer 106 , an antifuse material layer 120 , a dielectric layer 122 and a plurality of contact windows CT1 . In some embodiments, the antifuse structure can be an OTP memory or a PUF generator. The conductive layer 106 is disposed on the substrate 100 . In detail, since part of the substrate 100 is located under the conductive layer 106 , the conductive layer 106 can be regarded as disposed on the substrate 100 . A layer 120 of antifuse material is disposed on the conductive layer 106 . A dielectric layer 122 is disposed on the antifuse material layer 120 . A plurality of contact windows CT1 are disposed in the dielectric layer 122 . The antifuse material layer 120 is located between the contact windows CT1 and the conductive layer 106 . In addition, the antifuse structure 10 may further include at least one of the contact window CT2 , the wire L1 , and the wire L2 . The contact window CT2 is disposed in the dielectric layer 122 and electrically connected to the conductive layer 106 . The contact window CT2 may pass through the antifuse material layer 120 . The wire L1 is electrically connected to the contact window CT1. The number of wires L1 can be multiple. The wire L2 is electrically connected to the contact window CT2.

In addition, the transistor structure 12 may include a transistor 108 , contact windows CT3 ˜ CT5 , and wires L3 ˜ L5 . The contact window CT3 is located between the wire L3 and the gate 110 . The contact window CT4 is located between the wire L4 and the doped region 114 . The contact window CT5 is located between the wire L5 and the doped region 116 .

In addition, the materials, arrangement and formation methods of the components in the antifuse structure 10 and the transistor structure 12 have been described in detail in the above-mentioned embodiments, and will not be further described here.

In some embodiments, the antifuse structure 10 can be an OTP memory, and the programming method of the OTP memory is described as follows. For example, a high voltage is applied to the selected contact window CT1 and the conductive layer 106 is grounded, whereby the generated current can cause the antifuse material layer 120 located between the selected contact window CT1 and the conductive layer 106 to generate Crash (breakdown). In this way, the collapsed portion of the antifuse material layer 120 can be changed from a high resistance state (considered as a data “0”) to a low resistance state (considered as a data “1”), whereby the selected OTP memory cell can be controlled. stylized. In some embodiments, a high voltage can be applied to the selected contact window CT1 through the wire L1 corresponding to the selected contact window CT1 . In some embodiments, the conductive layer 106 can be grounded through the wire L2 and the contact window CT2.

In some embodiments, the antifuse structure 10 may be a PUF generator, and the antifuse structure 10 may include a plurality of contact groups CG. Each contact group CG may include any two contacts CT1 among the plurality of contacts CT1. In this embodiment, the two contacts CT1 in the contact group CG are two adjacent CT1s, but the invention is not limited thereto. In some other embodiments, the two contacts CT1 in the contact group CG may be two non-adjacent contacts CT1, that is, there are other contacts between the two contacts CT1 in the contact group CG CT1. In addition, multiple contact groups CG do not share the same contact CT1.

In the case that the antifuse structure 10 is a PUF generator, the operation method of the PUF generator is described as follows. For example, a high voltage is applied to the two contact windows CT1 in the selected contact window group CG to be electrically connected, and the conductive layer 106 is grounded, so that the generated current can make random ones of the two contact windows CT1 The antifuse material layer 120 between one and the conductive layer 106 collapses. In this way, the collapsed part of the antifuse material layer 120 can be changed from a high resistance state (as a data "0") to a low resistance state (as a data "1"), whereby the above two contacts can be randomly connected. One of the two OTP memory cells corresponding to window CT1 is programmed. That is, after the above operations are performed, the programmed one of the two OTP memory cells corresponding to the above two contact windows CT1 can be regarded as storing data "1", and the two corresponding to the above two contact windows CT1 The unprogrammed one of the OTP memory cells can be regarded as storing data "0". In some other embodiments, the above operation may also program the two OTP memory cells corresponding to the two contact windows CT1 at the same time. Therefore, after performing the above operations on all contact groups CG, a set of random digital fingerprints can be generated. In some embodiments, a high voltage can be electrically connected and applied to the two contact windows CT1 through the two wires L1 corresponding to the two contact windows CT1 . In some embodiments, the conductive layer 106 can be grounded through the wire L2 and the contact window CT2.

Based on the above embodiments, since the antifuse structure 10 is operated by applying a voltage to the contact window CT1 and the conductive layer 106 , the antifuse structure 10 can have a smaller device area, thereby increasing the device density. In addition, the antifuse material layer 120 is located between the plurality of contact windows CT1 and the same conductive layer 106, thereby forming a plurality of OTP memory cells, and the design and application of the antifuse structure 10 can be more flexible. . In addition, the manufacturing process of the antifuse structure 10 can be integrated with the manufacturing process of the transistor structure 12 , thus reducing the complexity of the manufacturing process.

FIG. 2 is a cross-sectional view of an antifuse structure according to another embodiment of the present invention.

Please refer to FIG. 1F and FIG. 2 , the differences between the antifuse structure 20 in FIG. 2 and the antifuse structure 10 in FIG. 1F are as follows. The antifuse structure 20 further includes a conductive layer 200 . The conductive layer 200 is disposed on the substrate 100 . In this embodiment, the conductive layer 200 can be disposed on the conductive layer 106 . The conductive layer 200 can be a metal silicide layer. The material of the conductive layer 200 is, for example, tungsten silicide, cobalt silicide or nickel silicide. The antifuse material layer 120 is disposed on the conductive layer 200 . The antifuse material layer 120 is located between the contact windows CT1 and the conductive layer 200 . The contact window CT2 is electrically connected to the conductive layer 200 .

In addition, the differences between the transistor structure 22 of FIG. 2 and the transistor structure 12 of FIG. 1F are as follows. The transistor 208 may further include a metal silicide layer 202 , a metal silicide layer 204 and a metal silicide layer 206 . The metal silicide layer 202 , the metal silicide layer 204 and the metal silicide layer 206 are respectively disposed on the gate 110 , the doped region 114 and the doped region 116 . The metal silicide layer 202 is located between the contact window CT3 and the gate 110 . The metal silicide layer 204 is located between the contact window CT4 and the doped region 114 . The metal silicide layer 206 is located between the contact window CT5 and the doped region 116 . In addition, the conductive layer 200 , the metal silicide layer 202 , the metal silicide layer 204 and the metal silicide layer 206 can be formed simultaneously by the same process.

In addition, the same or similar components in FIG. 2 and FIG. 1F are represented by the same or similar symbols, and the antifuse structure 20 in FIG. 2 is similar to the antifuse structure 10 in FIG. 1F . The description of the antifuse structure 10 is omitted here.

Based on the above embodiments, since the antifuse structure 20 is operated by applying a voltage to the contact window CT1 and the conductive layer 200 , the antifuse structure 20 can have a smaller device area, thereby increasing the device density. In addition, the antifuse material layer 120 is located between the plurality of contact windows CT1 and the same conductive layer 200, thereby forming a plurality of OTP memory cells, and the design and application of the antifuse structure 20 can be more flexible. . In addition, the manufacturing process of the antifuse structure 20 can be integrated with the manufacturing process of the transistor structure 22 , thus reducing the complexity of the manufacturing process.

FIG. 3 is a cross-sectional view of an antifuse structure according to another embodiment of the present invention.

Please refer to FIG. 1F and FIG. 3 , the differences between the antifuse structure 30 in FIG. 3 and the antifuse structure 10 in FIG. 1F are as follows. In the antifuse structure 30, the conductive layer 306 is a dummy gate. That is, in FIG. 3 , the conductive layer 306 of the dummy gate type replaces the conductive layer 106 of the doped region type in FIG. 1F . The material of the dummy gate is, for example, doped polysilicon. In this embodiment, the conductive layer 306 may be located directly above the isolation structure 102 , but the invention is not limited thereto. In other embodiments, the conductive layer 306 may be located directly above the active region. In some embodiments, the conductive layer 306 and the gate 110 can be formed simultaneously by the same process. In addition, the antifuse structure 30 may further include a gate dielectric layer 312 and a spacer 318 . The gate dielectric layer 312 is located between the conductive layer 306 and the substrate 100 . In this embodiment, the gate dielectric layer 312 may be located between the conductive layer 306 and the isolation structure 102 . In some embodiments, the gate dielectric layer 312 and the gate dielectric layer 112 can be formed simultaneously by the same process. The spacer 318 is located on the sidewall of the conductive layer 306 . In some embodiments, the spacer 318 and the spacer 118 can be formed simultaneously by the same process. In addition, in the antifuse structure 30, the well region 104 in FIG. 1F may be omitted.

In addition, the same or similar components in FIG. 3 and FIG. 1F are represented by the same or similar symbols, and the similar content between the antifuse structure 30 in FIG. 3 and the antifuse structure 10 in FIG. The description of the antifuse structure 10 is omitted here.

Based on the above-mentioned embodiments, since the antifuse structure 30 is operated by applying a voltage to the contact window CT1 and the conductive layer 306 , the antifuse structure 30 can have a smaller device area, thereby increasing the device density. In addition, the antifuse material layer 120 is located between the plurality of contact windows CT1 and the same conductive layer 306, thereby forming a plurality of OTP memory cells, and the design and application of the antifuse structure 30 can be more flexible. . In addition, the manufacturing process of the antifuse structure 30 can be integrated with the manufacturing process of the transistor structure 12 , thus reducing the complexity of the manufacturing process.

FIG. 4 is a cross-sectional view of an antifuse structure according to another embodiment of the present invention.

Please refer to FIG. 3 and FIG. 4 , the differences between the antifuse structure 40 in FIG. 4 and the antifuse structure 30 in FIG. 3 are as follows. The antifuse structure 40 further includes a conductive layer 400 . The conductive layer 400 can be a metal silicide layer. The material of the conductive layer 400 is, for example, tungsten silicide, cobalt silicide or nickel silicide. The conductive layer 400 is disposed on the substrate 100 . In this embodiment, the conductive layer 400 may be disposed on the conductive layer 306 . The antifuse material layer 120 is disposed on the conductive layer 400 . The antifuse material layer 120 is located between the plurality of contact windows CT1 and the conductive layer 400 . The contact window CT2 is electrically connected to the conductive layer 400 .

In addition, the differences between the transistor structure 42 of FIG. 4 and the transistor structure 12 of FIG. 3 are as follows. The transistor 408 may further include a metal silicide layer 402 , a metal silicide layer 404 and a metal silicide layer 406 . The metal silicide layer 402 , the metal silicide layer 404 and the metal silicide layer 406 are respectively disposed on the gate 110 , the doped region 114 and the doped region 116 . The metal silicide layer 402 is located between the contact window CT3 and the gate 110 . The metal silicide layer 404 is located between the contact window CT4 and the doped region 114 . The metal silicide layer 406 is located between the contact window CT5 and the doped region 116 . In addition, the conductive layer 400 , the metal silicide layer 402 , the metal silicide layer 404 and the metal silicide layer 406 can be formed simultaneously through the same process.

In addition, the same or similar components in FIG. 4 and FIG. 3 are represented by the same or similar symbols, and the antifuse structure 40 in FIG. 4 is similar to the antifuse structure 30 in FIG. 3 . The description of the antifuse structure 30 is omitted here.

Based on the above embodiments, since the antifuse structure 40 is operated by applying a voltage to the contact window CT1 and the conductive layer 400 , the antifuse structure 40 can have a smaller device area, thereby increasing the device density. In addition, the antifuse material layer 120 is located between the plurality of contact windows CT1 and the same conductive layer 400, thereby forming a plurality of OTP memory cells, and the design and application of the antifuse structure 40 can be more flexible. . In addition, the manufacturing process of the antifuse structure 40 can be integrated with the manufacturing process of the transistor structure 42 , thus reducing the complexity of the manufacturing process.

FIG. 5 is a cross-sectional view of an antifuse structure according to another embodiment of the present invention.

Although not shown in FIG. 5 , there may be required components such as doped regions and/or isolation structures in the substrate 500, and there may be active elements, passive elements, dielectric layers, and interconnection structures on the substrate 500. and other required components, and their descriptions are omitted here. The conductive layer 506 is disposed on the substrate 500 .

Please refer to FIG. 1F and FIG. 5 , the differences between the antifuse structure 50 in FIG. 5 and the antifuse structure 10 in FIG. 1F are as follows. The antifuse structure 10 of FIG. 1 is integrated with the transistor structure 12 , while the antifuse structure 50 of FIG. 5 is integrated with the interconnect structure 52 . In the antifuse structure 50, the conductive layer 506 is a wire. That is, in FIG. 5 , the conductive layer 506 in the form of wires replaces the conductive layer 106 in the form of doped regions in FIG. 1F .

In some embodiments, when the antifuse structure 50 is operated, in addition to applying a voltage (such as grounding) to the conductive layer 506 through the wire L2 and the contact window CT2, other interconnection structures can also be used. (not shown) A voltage (eg, ground) is applied to the conductive layer 506 . In some other embodiments, when the antifuse structure 50 is operated, a voltage (eg, ground) may be applied to the conductive layer 506 through other interconnection structures (not shown), and the antifuse structure 50 may not Including the contact window CT2 and the wire L2.

In addition, the interconnection structure 52 may include a wire 502 , a contact window CT6 and a wire L6 . The wire 502 can be disposed on the substrate 500 . The conductive layer 506 and the wire 502 can be formed simultaneously by the same process. In FIG. 5 , the antifuse material layer 120 on the wire 502 and the antifuse material layer 120 on the conductive layer 506 can be separated from each other. In this embodiment, the conductive layer 506 and the wire 502 can be aluminum wires. The contact CT6 is located between the wire L6 and the wire 502 and can pass through the antifuse material layer 120 . For example, the contact window CT6 may include a conductive layer 128f and a barrier layer 130f. The conductive layer 128f is located in the dielectric layer 122 . The barrier layer 130f is located between the conductive layer 128f and the wire 502 and between the conductive layer 128f and the dielectric layer 122 . The wire L6 can be electrically connected to the contact window CT6.

In addition, the same or similar components in FIG. 5 and FIG. 1F are represented by the same or similar symbols, and the similar content between the antifuse structure 50 in FIG. 5 and the antifuse structure 10 in FIG. 1F can be referred to the above-mentioned embodiment The description of the antifuse structure 10 is omitted here.

Based on the above embodiments, since the antifuse structure 50 is operated by applying a voltage to the contact window CT1 and the conductive layer 506 , the antifuse structure 50 can have a smaller device area, thereby increasing the device density. In addition, the antifuse material layer 120 is located between the plurality of contact windows CT1 and the same conductive layer 506, thereby forming a plurality of OTP memory cells, and the design and application of the antifuse structure 50 can be more flexible. . In addition, the manufacturing process of the antifuse structure 50 can be integrated with the manufacturing process of the interconnection structure 52 , thus reducing the complexity of the manufacturing process.

FIG. 6 is a cross-sectional view of an antifuse structure according to another embodiment of the present invention.

Please refer to FIG. 5 and FIG. 6 , the differences between the antifuse structure 60 in FIG. 6 and the antifuse structure 50 in FIG. 5 are as follows. The conductive layer 506 in the antifuse structure 50 is an aluminum wire, and the conductive layer 606 in the antifuse structure 60 is a copper wire. The differences between the interconnect structure 62 of FIG. 6 and the interconnect structure 52 of FIG. 5 are as follows. The wires 502 in the interconnection structure 52 are aluminum wires, and the wires 602 in the interconnection structure 62 are copper wires. The wire 602 and the conductive layer 606 can be a single damascene structure or a dual damascene structure. In addition, in FIG. 6 , the antifuse material layer 120 on the wire 602 and the antifuse material layer 120 on the conductive layer 606 can be integrally formed. In addition, the conductive layer 602 and the conductive layer 606 may be formed in the dielectric layer 604 .

In addition, the same or similar components in FIG. 6 and FIG. 5 are represented by the same or similar symbols, and the content similar to the antifuse structure 60 in FIG. 6 and the antifuse structure 50 in FIG. The description of the antifuse structure 50 is omitted here.

Based on the above embodiments, since the antifuse structure 60 is operated by applying a voltage to the contact window CT1 and the conductive layer 606 , the antifuse structure 60 can have a smaller device area, thereby increasing the device density. In addition, the antifuse material layer 120 is located between the plurality of contact windows CT1 and the same conductive layer 606, thereby forming a plurality of OTP memory cells, and the design and application of the antifuse structure 60 can be more flexible. . In addition, the manufacturing process of the antifuse structure 60 can be integrated with the manufacturing process of the interconnection structure 62 , thus reducing the complexity of the manufacturing process.

In summary, the antifuse structure of the above embodiments can increase device density and be more flexible in design and application. In addition, the manufacturing process of the antifuse structure of the above embodiments can be integrated with other semiconductor manufacturing processes, thus reducing the complexity of the manufacturing process.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10,20,30,40,50,60: antifuse structure 12,22,42: Transistor structure 52,62: Interconnect structure 100,500: Base 102: Isolation structure 104: well area 106, 128a~128f, 200, 306, 400, 506, 606: conductive layer 108,208,408: Transistor 110: Gate 112,312: gate dielectric layer 114,116: doped area 118,318: gap wall 120: Antifuse material layer 122,604: dielectric layer 124,126: Patterned photoresist layer 130a~130f: barrier layer 202, 204, 206, 402, 404, 406: metal silicide layers 502,602,L1~L6: Wire CG: Contact window group CT1~CT6: Contact window OP1~OP5: opening

1A to 1F are cross-sectional views of the manufacturing process of the antifuse structure according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of an antifuse structure according to another embodiment of the present invention. FIG. 3 is a cross-sectional view of an antifuse structure according to another embodiment of the present invention. FIG. 4 is a cross-sectional view of an antifuse structure according to another embodiment of the present invention. FIG. 5 is a cross-sectional view of an antifuse structure according to another embodiment of the present invention. FIG. 6 is a cross-sectional view of an antifuse structure according to another embodiment of the present invention.

10: Antifuse structure

12: Transistor structure

100: base

102: Isolation structure

104: well area

106, 128a~128e: conductive layer

108: Transistor

110: Gate

112: gate dielectric layer

114,116: doped area

118: gap wall

120: Antifuse material layer

122: dielectric layer

130a~130e: barrier layer

CG: Contact window group

CT1~CT5: Contact window

L1~L5: wire

Claims (10)

An antifuse structure comprising: base; a conductive layer disposed on the substrate; an antifuse material layer disposed on the conductive layer; a dielectric layer disposed on the layer of antifuse material; and A plurality of first contact windows are disposed in the dielectric layer, wherein the antifuse material layer is located between the plurality of first contact windows and the conductive layer. The antifuse structure as described in Claim 1 further includes: The second contact window is disposed in the dielectric layer and electrically connected to the conductive layer. The antifuse structure according to claim 2, wherein the second contact window passes through the antifuse material layer. The antifuse structure as described in claim item 2 further includes: The wire is electrically connected to the second contact window. The antifuse structure according to claim 1, wherein the conductive layer includes a doped region, a metal silicide layer, a dummy gate or a wire. The antifuse structure according to claim 1, wherein the antifuse structure comprises a one-time programmable memory or a physically non-replicable function generator. The antifuse structure according to claim 6, wherein the antifuse structure is the physical non-replicable function generator, the antifuse structure includes a plurality of contact window groups, and each of the contact window groups Any two first contact windows among the plurality of first contact windows are included. The antifuse structure according to claim 7, wherein the plurality of contact window groups do not share the same first contact window. The antifuse structure according to claim 1, wherein the material of the antifuse material layer includes silicon nitride, silicon oxynitride or silicon carbide nitride. The antifuse structure as described in Claim 1 further includes: A plurality of wires are electrically connected to the plurality of first contact windows.

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