TWI785371B - Electronic packaging and manufacturing method thereof - Google Patents

Abstract

This invention provides an electronic package which arranges an electronic component on a carrying structure, and then forms an encapsulation layer on a part of a surface of the carrying structure to cover the electronic component, so as to regulate a stress distribution of the carrying structure and avoid a problem of cracking of the electronic component due to stress concentration.

Description

Electronic package and its manufacturing method

The present invention relates to a semiconductor device, especially an electronic package that can improve product reliability and its manufacturing method.

With the evolution of technology, the demand trend of electronic products is moving towards heterogeneous integration. For this reason, multi-chip module (multi-chip module, MCM) / (multi-chip package, MCP) is gradually emerging.

The package structure 1 shown in FIG. 1 is to combine a plurality of semiconductor chips 11 onto a package substrate 10 via a plurality of solder bumps 13 , and then form a package layer 14 covering the plurality of semiconductor chips 11 . By packaging multiple semiconductor chips into a single structure, it has a large number of I/Os, and can greatly increase the computing power of the processor and reduce the delay time of signal transmission, so it can be applied to high-density circuits/ High-end products with high transmission speed/high stack count/large size design.

However, in the packaging process of the conventional packaging structure 1, the packaging substrate 10 is the entire layout (ie, mass production size), and when the temperature cycle (temperature cycle) or stress changes, such as passing through a reflow oven, or experiencing drop During the manufacturing process or testing, the package substrate 10 is likely to be warped due to the Coefficient of Thermal Expansion (CTE) difference (Mismatch) between the package substrate 10 and the semiconductor chip 11 (or package layer 14 ). (warpage) (as shown in the dotted line in Figure 1), so in the case of warpage Under such circumstances, it is easy to cause a crack k to occur between the semiconductor wafer 11 and the encapsulation layer 14, and even cause the semiconductor wafer 11 to break, resulting in a decrease in product yield.

Therefore, how to overcome the various problems of the above-mentioned conventional technologies has become an urgent problem to be solved at present.

In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: a carrying structure; The electronic component is electrically connected to the carrying structure through the conductive bump; and an encapsulation layer is formed on a part of the surface of the carrying structure to cover the electronic component.

The present invention further provides a method for manufacturing an electronic package, which includes: providing at least one electronic component with a plurality of conductive bumps formed thereon; placing the electronic component on a carrier structure, wherein the electronic component is formed with the conductive bumps a block is electrically connected to the carrying structure; and an encapsulation layer is formed on a part of the surface of the carrying structure to cover the electronic component.

In the aforementioned electronic package and its manufacturing method, a plurality of the electronic components are arranged horizontally on the carrier structure, so that a gap is formed between any two adjacent electronic components, and the encapsulation layer fills up the gap. For example, the distance between the gaps is at most 300 microns.

In the aforementioned electronic package and its manufacturing method, one surface of the electronic component is exposed on one surface of the package layer. Further, a reinforcement is formed at the junction between the surface of the electronic component and the surface of the encapsulation layer, for example, an insulating block formed by dispensing the reinforcement system. Even the metal layer is formed on the surface of the electronic component, the reinforcing body and the surface of the encapsulation layer.

In the aforementioned electronic package and its manufacturing method, after forming the package layer, roughening a surface of the electronic component to make it a concave-convex surface.

In the aforementioned electronic package and its manufacturing method, the Young's modulus of the package layer is at least 20 GPa.

In the aforementioned electronic package and its manufacturing method, after forming the package layer, roughening a surface of the package layer to make it a concave-convex surface.

It can be seen from the above that in the electronic package and its manufacturing method of the present invention, the strength of the junction between the electronic component and the packaging layer can be strengthened mainly through the design of the reinforcing body, so when the carrying structure warps , can still avoid the occurrence of cracks between the electronic component and the encapsulation layer, thus avoiding the problem of cracking of the electronic component.

1: Package structure

10: Package substrate

11: Semiconductor wafer

13: Solder bumps

14,24: encapsulation layer

2: Electronic package

2a: Full-page substrate structure

20: Bearing structure

200: line layer

21: Electronic components

21a: Action surface

21b: Non-active surface

210: electrode pad

22: Conductive bump

24b: upper surface

25: Reinforcement body

26: metal layer

k: crack

L, S: cutting path

M: uneven surface

t: gap

X: horizontal direction

FIG. 1 is a schematic cross-sectional view of a conventional packaging structure.

2A to 2E are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

FIG. 3 is a partially enlarged cross-sectional schematic diagram of another aspect of FIG. 2E .

The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for the understanding and reading of those familiar with this technology, and are not used to limit the implementation of the present invention Therefore, it has no technical substantive meaning. Any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of this invention without affecting the effect and purpose of the present invention. The technical content disclosed by the invention must be within the scope covered. At the same time, terms such as "above" quoted in this specification are only for the convenience of description, and are not used to limit the practicality of the present invention. The scope of implementation, the change or adjustment of its relative relationship, without substantial change in technical content, should also be regarded as the scope of the present invention that can be implemented.

2A to 2E are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A , a full-page substrate structure 2 a is provided, which includes a plurality of electronic components 21 arranged in an array, and a plurality of conductive bumps 22 are arranged on each of the electronic components 21 .

The electronic component 21 can be an active component, a passive component, a packaging structure or a combination thereof, and the active component is such as a semiconductor chip, and the passive component is such as a resistor, capacitor and inductor. In this embodiment, the electronic component 21 is a semiconductor chip, and has an opposite active surface 21a and a non-active surface 21b. There are a plurality of electrode pads 210 on the active surface 21a, and conductive bumps are formed on each of the electrode pads 210. Block 22.

Furthermore, the conductive bump 22 is a solder material, a metal post (such as a copper post) or a combination thereof.

As shown in FIG. 2B, the full-page substrate structure 2a is subjected to a singulation process along the cutting path L shown in FIG. 2A to separate the electronic components 21, and then spaced on a carrier structure 20 along the horizontal direction X. At least two electronic components 21 are arranged.

The carrying structure 20 can be a packaging substrate (substrate) with a core layer and a circuit structure or a circuit structure without a core layer (coreless), and its composition is to form a plurality of circuit layers 200 on a dielectric material, such as circuit redistribution Layer (redistribution layer, RDL for short).

In this embodiment, the carrying structure 20 is a circuit structure without a core layer (coreless). However, in other embodiments, the carrier structure 20 can also be a semiconductor substrate with a plurality of conductive through-silicon vias (TSV for short), serving as a through silicon interposer (TSI for short). It should be understood that the carrying structure 20 can also be other carrying units capable of carrying electronic components such as chips, such as a lead frame, but is not limited to the above.

Furthermore, when the electronic component 21 is flip-chip, the conductive bumps 22 are electrically connected to the circuit layer 200 of the carrying structure 20 .

In addition, in this embodiment, although the electronic components 21 are of the same type (ie active components), their internal structures may be the same or different. It should be understood that the electronic components 21 can also be different types of electronic components.

As shown in FIG. 2C , an encapsulation layer 24 is formed on a part of the surface of the carrying structure 20 to cover the electronic components 21 and the conductive bumps 22 .

The encapsulation layer 24 can be an insulating material, such as polyimide (PI for short), dry film, epoxy, molding compound or other suitable materials.

In this embodiment, the encapsulation layer 24 is formed on the carrying structure 20 by lamination or molding, so that the encapsulation layer 24 does not fill any two adjacent electronic components 21 Between, thus forming a gap t.

Furthermore, the Young's modulus of the encapsulation layer 24 is above 20 GPa.

In addition, the non-active surface 21b of the electronic component 21 can be coplanar with the upper surface 24b of the packaging layer 24 through a flattening process or a thinning process, so that the non-active surface 21b of the electronic component 21 is exposed to the package Layer 24. For example, when forming the encapsulation layer 24 on the carrying structure 20, the encapsulation layer 24 covers the non-active surface 21b of the electronic component 21, and then removes part of the material of the encapsulation layer 24 by grinding or cutting (also can be At the same time, part of the material of the non-active surface 21b of the electronic component 21 is removed as required, so that the non-active surface 21b of the electronic component 21 is flush with the upper surface 24b of the encapsulation layer 24 .

As shown in FIG. 2D , a reinforcement 25 is formed at the junction between the non-active surface 21 b of the electronic component 21 and the encapsulation layer 24 .

In this embodiment, the reinforcing body 25 is an insulating block formed by dispensing glue, so as to be pressed on the junction between the non-active surface 21 b of the electronic component 21 and the encapsulation layer 24 . For example, a copper foil can be formed on the non-active surface 21b of the electronic component 21, the reinforcing body 25 and the upper surface 24b of the packaging layer 24. The metal layer 26 of the material is used to further suppress the electronic component 21 and the encapsulation layer 24 . The metal layer 26 can be understood as an EMI shielding for the chip 21 .

As shown in FIG. 2E , a singulation process is performed along the cutting path S (such as the gap t) shown in FIG. 2D to obtain the electronic package 2 .

In this embodiment, the non-active surface 21b of the electronic component 21 and the upper surface 24b of the encapsulation layer 24 can be roughened first as required, so that the inactive surface 21b of the electronic component 21 and the upper surface 24b of the encapsulation layer 24 Form the concave-convex surface M, as shown in Figure 3, and then form the reinforcement 25 and the metal layer 26 to increase the contact area of the reinforcement 25 and the contact area of the metal layer 26, thereby strengthening the bonding of the reinforcement 25 And the combination of the metal layer 26.

In the subsequent process (that is, after the packaging layer 24 is formed), a plurality of solder balls (not shown) can be formed on the lower side (or ball-planting side) of the carrier structure 20 for the electronic package 2 to be connected to a Such as the electronic device on the circuit board (not shown).

Therefore, the manufacturing method of the present invention mainly controls the stress distribution on the supporting structure 20 by forming the encapsulation layer 24 on a part of the surface of the supporting structure 20. Therefore, compared with the prior art, the manufacturing method of the present invention can be used in When the supporting structure 20 is warped, the electronic component 21 can still disperse the stress it receives, so as to avoid the cracking of the electronic component 21 due to stress concentration, thereby improving the reliability of the electronic package 2 .

Moreover, by the design of the reinforcing body 25 (and the metal layer 26), to suppress the junction between the non-active surface 21b of the electronic component 21 and the encapsulation layer 24, so when the carrier structure 20 warps During warpage, cracks can be avoided between the electronic component 21 and the encapsulation layer 24, thereby avoiding the cracking of the electronic component 21, so as to effectively improve product yield.

The present invention further provides an electronic package 2 , which includes: a carrying structure 20 , at least one electronic component 21 , and a packaging layer 24 .

The electronic component 21 is disposed on the carrying structure 20 , wherein the electronic component 21 has a plurality of conductive bumps 22 , so that the electronic component 21 is electrically connected to the carrying structure 20 through the conductive bumps 22 .

The encapsulation layer 24 is formed on a part of the surface of the carrying structure 20 to cover the electronic component 21 and the conductive bump 22 .

In one embodiment, a plurality of electronic components 21 are arranged in the horizontal direction X on the carrier structure 20, so that a gap t is formed between any two adjacent electronic components 21, so that the encapsulation layer 24 is not filled The gap t. For example, the distance between the gaps t is at most 300 micrometers.

In one embodiment, the non-active surface 21 b of the electronic component 21 is exposed on the upper surface 24 b of the encapsulation layer 24 . Further, the junction between the non-active surface 21b of the electronic component 21 and the upper surface 24b of the encapsulation layer 24 is formed with a reinforcement 25, such as an insulating block, and even the non-active surface 21b of the electronic component 21, the reinforced A metal layer 26 is formed on the body 25 and the upper surface 24 b of the encapsulation layer 24 .

In one embodiment, the non-active surface 21b of the electronic component 21 is a concave-convex surface or roughened.

In one embodiment, the Young's modulus of the encapsulation layer 24 is at least 20 GPa.

In one embodiment, the upper surface 24b of the encapsulation layer 24 is a concave-convex surface or roughened.

In summary, the electronic package and its manufacturing method of the present invention can strengthen the strength of the junction between the electronic component and the packaging layer through the design of the reinforcing body, so when the carrying structure warps , can avoid cracks between the electronic component and the encapsulation layer, and thus can avoid the problem of cracking of the electronic component.

The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the right of the present invention should be as stated in the scope of patent application mentioned later.

20: Bearing structure

21: Electronic components

21b: Non-active surface

22: Conductive bump

24: encapsulation layer

t: gap

Claims (14)

An electronic package, comprising: a carrying structure; an electronic component is provided on the carrying structure in a flip-chip manner, wherein a plurality of conductive bumps are formed on the electronic component, so that the electronic component can pass through the conductive bump electrically connecting the carrying structure; an encapsulation layer formed on a part of the surface of the carrying structure to cover the electronic component, wherein one surface of the electronic component is exposed on one surface of the encapsulation layer; and a reinforcing body, An insulating block is formed only at the interface between the surface of the electronic component and the surface of the encapsulation layer. The electronic package as claimed in claim 1, wherein a plurality of electronic components are horizontally arranged on the supporting structure, so that a gap is formed between any two adjacent electronic components, so that the packaging layer does not fill the gap. The electronic package as claimed in claim 2, wherein the distance between the gaps is at most 300 microns. The electronic package as claimed in claim 1, wherein a metal layer is formed on the surface of the electronic component, the reinforcing body and the surface of the encapsulation layer. The electronic package according to claim 1, wherein one surface of the electronic component is a concave-convex surface. The electronic package as claimed in claim 1, wherein the Young's modulus of the packaging layer is at least 20 GPa. The electronic package according to claim 1, wherein one surface of the packaging layer is a concave-convex surface. A method for manufacturing an electronic package, comprising: providing at least one electronic component with a plurality of conductive bumps formed thereon; setting the electronic component on a carrier structure in a flip-chip manner through the plurality of conductive bumps, wherein the The electronic component is electrically connected to the carrying structure by the conductive bump; forming a packaging layer on a part of the surface of the carrying structure to cover the electronic component, and making one surface of the electronic component exposed on one of the packaging layers the surface; and forming a reinforcing body as an insulating block by dispensing, and forming the reinforcing body only at the junction between the surface of the electronic component and the surface of the encapsulation layer. The method for manufacturing an electronic package as claimed in claim 8, wherein a plurality of the electronic components are horizontally arranged on the supporting structure, so that a gap is formed between any two adjacent electronic components, so that the packaging layer is not filled fill the gap. The method for manufacturing an electronic package as claimed in claim 9, wherein the distance between the gaps is at most 300 micrometers. The method for manufacturing an electronic package according to claim 8, wherein a metal layer is formed on the surface of the electronic component, the reinforcing body, and the surface of the packaging layer. The method for manufacturing an electronic package as claimed in claim 8 further includes roughening a surface of the electronic component after forming the packaging layer. The method for manufacturing an electronic package as claimed in claim 8, wherein the Young's modulus of the packaging layer is at least 20 GPa. The method for manufacturing an electronic package as claimed in claim 8 further includes roughening a surface of the package layer after forming the package layer.

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