TWI782569B - Reset source monitoring circuit, touch chip and information processing device - Google Patents

Abstract

The present invention mainly discloses a reset source monitoring circuit, which is applied in a touch chip and coupled between a reset source and a microcontroller of the touch chip. After the reset source sends a reset signal, the reset source monitoring circuit of the present invention records a first bit to represent a reset state according to the reset signal, and simultaneously transmits a reset enabling signal to the microcontroller, so that After the microcontroller reads the first bit from the reset source monitoring circuit, it modifies the first bit into a second bit, and then correspondingly executes a start-up process according to the reset state.

Description

Reset source monitoring circuit, touch chip and information processing device

The invention relates to the related field of touch chip, especially a reset source monitoring circuit with improved protection ability of chip abnormality.

Currently, touch devices have been widely used in various electronic devices that require touch control. FIG. 1 shows a block diagram of a conventional touch device. As shown in FIG. 1 , a conventional touch device 1 a includes: a touch panel 11 a and at least one touch chip 12 a. FIG. 2 is a block diagram of a microcontroller 121 a , a SRAM 122 a and a flash memory 123 a included in the touch chip shown in FIG. 1 . Electronic engineers who are familiar with the design and manufacture of touch devices must know that the touch chip 12a will perform self-resetting and restarting under the trigger of a reset signal.

It is known that the reset signal is transmitted by a reset source, and the reset source can be a reset circuit, reset software, ESD circuit, watchdog circuit and the like. Electronic engineers who are familiar with the design and manufacture of the touch chip 12a must know that the reset circuit, ESD circuit and watchdog (watchdog) circuit are integrated in the touch chip 12a, and the reset software is installed in a host computer. Of course, the power supply voltage used to power on the touch chip 12a is also a reset source.

Practical experience shows that it is really necessary to track and record the reasons for the reset and restart of the touch chip 12a (that is, the type of reset source), so that the microcontroller 121a can take corresponding startup steps when it is reset and restarted, thereby improving the reliability of the touch control chip 12a. The abnormality protection capability of the touch chip 12a.

It can be seen from the above description that there is an urgent need in the art for a chip soft failure prevention capability enhancement circuit.

The main purpose of the present invention is to provide a reset source monitoring circuit, which is applied to a touch chip containing a microcontroller, so that the touch chip can record the reset reason during the reset and restart process, such as on the chip Electricity or ESD impact, so that the microcontroller inside the touch chip can adopt a corresponding start-up process, which helps to improve the abnormal protection capability of the chip.

In order to achieve the above object, the present invention proposes an embodiment of the reset source monitoring circuit, which is applied in a touch chip and is coupled between a reset source and a microcontroller of the touch chip for use in To receive a reset signal transmitted by the reset source, so as to record a first bit to represent a reset state corresponding to the reset source; at the same time, the reset source monitoring circuit transmits a reset enable signal to the A microcontroller, after the microcontroller reads the first bit from the reset source monitoring circuit, modifies the first bit to a second bit, and then performs a start correspondingly according to the reset state process.

In one embodiment, the reset source includes a plurality of reset signal generating units, and the plurality of reset signal generating units include: a reset circuit, a reset control pin, an electrostatic discharge protection circuit, and a watchdog circuit.

In one embodiment, the reset source monitoring circuit of the present invention includes:

A reset enabling unit, with its plurality of signal input terminals coupled to the plurality of reset signal generation units, and with its signal output terminal coupled to the microcontroller;

A plurality of registers, wherein each of the registers is coupled to one of the reset signal generation units with a first control terminal; and

an access bus, coupled to a data output end of each of the registers, and simultaneously coupled to a data input end of each of the registers and the microcontroller;

Wherein, after receiving the reset signal transmitted by any one of the reset signal generating units, the reset enabling unit sends the reset enabling signal to the microcontroller, so that the microcontroller can transfer from the microcontroller through the access bus The first bit used to represent the reset state is read from the register; after reading the first bit, the microcontroller modifies the first bit to a second bit.

In one embodiment, the first control terminals of the multiple registers are also coupled to a power-on reset signal transmitted by a power-on reset source, and at least one of the signal input terminals of the reset enabling unit The system is coupled to the power-on reset signal at the same time.

In one embodiment, the first control terminal is a data clear terminal or a reset terminal of the register, and a clock signal is sent to the register when the microcontroller accesses the register through the access bus. A second control terminal of the register; the first bit is 0, and the second bit is 1.

Moreover, the present invention also proposes a touch control chip, which contains a microcontroller; the feature is that the touch control chip has a reset source monitoring circuit, and the reset source monitoring circuit is coupled to a reset source and the touch control chip between a microcontroller, to receive a reset signal transmitted by the reset source, so as to record a first bit to represent a reset state corresponding to the reset source; at the same time, the reset source monitors The circuit sends a reset enable signal to the microcontroller, so that the microcontroller reads the first bit from the reset source monitoring circuit, modifies the first bit to a second bit, and then according to the According to the above reset state, a start-up process is correspondingly executed.

In one embodiment, the reset source includes a plurality of reset signal generating units, and the plurality of reset signal generating units include: a reset circuit, a reset control pin, an electrostatic discharge protection circuit, and a watchdog circuit.

In one embodiment, the reset source monitoring circuit included in the touch chip includes:

A reset enabling unit, with its plurality of signal input terminals coupled to the plurality of reset signal generation units, and with its signal output terminal coupled to the microcontroller;

A plurality of registers, wherein each of the registers is coupled to one of the reset signal generation units with a first control terminal; and

an access bus, coupled to a data output end of each of the registers, and simultaneously coupled to a data input end of each of the registers and the microcontroller;

Wherein, after receiving the reset signal transmitted by any one of the reset signal generating units, the reset enabling unit sends the reset enabling signal to the microcontroller, so that the microcontroller can transfer from the microcontroller through the access bus reading the first bit representing the reset state from the register; after completing the reading of the first bit, the microcontroller modifies the first bit to a second bit;

Wherein, the plurality of said registers are also coupled with a power-on reset signal transmitted by a power-on reset source with said first control terminals thereof, and at least one of said signal input terminals of said reset enabling unit is simultaneously coupled to the power-on reset signal.

In one embodiment, the first control terminal is a data clear terminal or a reset terminal of the register, and a clock signal is sent to the register when the microcontroller accesses the register through the access bus. A second control terminal of the register; the first bit is 0, and the second bit is 1.

The present invention also discloses an information processing device, which is characterized in that it has a touch panel and the touch chip of the present invention as mentioned above. In a feasible embodiment, the information processing device is selected from the group consisting of a touch device, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, and an access control device an electronic device.

In order to enable your examiners to further understand the structure, features, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred specific embodiments are hereby attached.

The purpose of the present invention is to propose a reset source monitoring circuit, which is applied to a touch chip containing a microcontroller, so that the touch chip can record the reset reason during the process of reset and restart, such as chip power-on or Due to the impact of ESD, the microcontroller inside the touch chip can adopt a corresponding start-up process, which helps to improve the abnormal protection capability of the chip.

FIG. 3 shows a block diagram of a touch device including a touch chip of the present invention. As shown in FIG. 3 , the touch device 1 includes: a touch panel 11 and at least one touch chip 12 of the present invention. FIG. 4 is a block diagram of internal units of the touch chip 12 of the present invention. As shown in FIG. 4 , the touch chip 12 of the present invention includes: a microcontroller 121 , a SRAM 122 , a flash memory 123 , a reset source monitoring unit 124 and a reset source 120a. In a feasible embodiment, the reset source 120a includes a plurality of reset signal generating units, such as a reset circuit 1201 , a reset control pin 1202 , an ESD circuit 1203 and a watchdog circuit 1204 shown in FIG. 4 . According to the design of the present invention, the reset source monitoring circuit 124 is coupled between the reset source 120 and the microcontroller 121 to receive a reset signal transmitted by the reset source 120, thereby recording a first bit It is used to represent a reset state corresponding to the reset source 120; at the same time, the reset source monitoring circuit 124 transmits a reset enable signal to the microcontroller 121, so that the microcontroller 121 can start from the reset source monitoring circuit. After the 124 reads out the first bit, it modifies the first bit into a second bit, and then executes a startup process correspondingly according to the reset state.

Continue to refer to FIG. 4 , and please refer to FIG. 5 at the same time, which shows a block diagram of internal units of the reset source monitoring unit 124 of the present invention. In one embodiment, the reset source monitoring circuit 124 includes: a reset enabling unit 1241 and a plurality of registers 1242 . As shown in FIG. 5, the reset enabling unit 1241 can be, for example, an OR gate with multiple input terminals, and its multiple signal input terminals are respectively coupled to a plurality of the reset signal generating units (1201~1204). One signal output end is coupled to the microcontroller 121 . It should be understood that after receiving the reset signal transmitted by any one of the reset signal generating units (1201~1204), the reset enabling unit 1241 (that is, the OR gate) sends a reset enabling signal to the microcontroller 121.

In more detail, each of the registers 1242 is coupled to a reset signal generating unit with a first control terminal thereof, and the access bus 1243 is coupled to a data output terminal of each of the registers 1242, and is also coupled to A data input terminal of each of the registers 1242 and the microcontroller 121 . As shown in FIG. 5, the register 1242 can be, for example, a D flip-flop, and the first control terminal is a data clearing terminal (CLR) or a reset terminal (or reset terminal) of the D flip-flop. And a second control terminal of the D flip-flop is used to receive a clock signal.

For example, the four registers 1242 shown in FIG. 5 all store bit 1. At this time, a reset signal generated by the reset source 120a is transmitted to the first control terminal (that is, the CLR terminal) of the second register 1242, and the bit 1 stored in the second register 1242 will be cleared ( That is, it becomes bit 0). At the same time, the reset enabling unit 1241 also sends a reset enabling signal to the microcontroller 121 according to the reset signal, so that the microcontroller 121 reads the registered bits from the four registers 1242 . After the bit reading is completed, the microcontroller 121 can know that the reset signal is generated by the reset circuit 1201, the reset control pin 1202, the ESD circuit 1203, or the gatekeeper in the reset source 120a according to the result of the bit reading. issued by dog circuit 1204. Therefore, the microcontroller 121 can adopt a corresponding reset activation process according to different reset reasons.

To explain in more detail, therefore, after each bit reading is completed, the microcontroller 121 must replace the first bit originally used to represent a reset state corresponding to the reset signal generating unit (i.e., Bit 0) is modified to the second bit (ie, bit 1). Further, FIG. 4 and FIG. 5 also show that a plurality of the registers 1242 are simultaneously connected to a power-on reset signal transmitted by a power-on reset source 120b with the first control terminal thereof, and the reset enabling unit At least one of the signal input terminals of 1241 is coupled to the power-on reset signal at the same time. In short, after the touch chip 12 receives a power-on voltage, the power-on reset source 120 b sends a power-on reset signal to each of the registers 1242 and the reset enabling unit 1241 . After receiving the power-on reset signal, each register 1242 is cleared. At this time, the microcontroller 121 reads bit 0 from each register 1242, which means that the touch chip 12 is currently performing a power-on reset procedure. It is supplemented that the second control terminal (ie, CLK terminal) of each of the registers 1242 is used to receive a clock signal, and the clock signal is used to access the registers by the microcontroller 121 through the access bus 1243 1242 is transmitted to the CLK terminal, so that additional power consumption can be avoided.

Thus, the above has completely and clearly described a reset source monitoring circuit of the present invention; and, through the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a reset source monitoring circuit, which is applied to a touch chip containing a microcontroller, so that the touch chip can record the reset reason during the reset and restart process, such as the chip is powered on or ESD impact, so that the microcontroller inside the touch chip can adopt a corresponding start-up process, which helps to improve the abnormal protection capability of the chip.

(2) The present invention also discloses a touch control chip, which contains a microcontroller; the feature is that the touch control chip has the reset source monitoring circuit of the present invention as mentioned above.

(3) The present invention also provides an information processing device, which is characterized by having a touch panel and the touch chip of the present invention as mentioned above. In a feasible embodiment, the information processing device is selected from the group consisting of a touch device, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, and an access control device an electronic device.

It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment, and all partial changes or modifications derived from the technical ideas of this case and easily deduced by those familiar with the technology are all inseparable from the patent of this case. category of rights.

To sum up, the purpose, means and efficacy of this case all show that it is very different from the conventional technology, and its first invention is practical, and indeed meets the patent requirements of the invention. I implore your review committee to be aware and grant a patent as soon as possible to benefit you. Society is for the Most Prayer.

1a: Touch device 11a: Touch panel 12a: Touch chip 121a: Microcontroller 122a: Static Random Access Memory 123a: Flash memory 1: Touch device 11: Touch panel 12: Touch chip 121: Microcontroller 122: static random access memory 123: Flash memory 124: Reset source monitoring unit 1241: reset enabling unit 1242: Register 120a: reset source 120b: power-on reset source 1201: reset circuit 1202: reset control pin 1203:ESD circuit 1204: Watchdog circuit

FIG. 1 is a block diagram of a known touch device; FIG. 2 is a block diagram of a microcontroller, a static random access memory and a flash memory included in the touch chip shown in FIG. 1; 3 is a block diagram of a touch device including a touch chip of the present invention; FIG. 4 is a block diagram of an internal unit of the touch chip of the present invention; and FIG. 5 is a block diagram of an internal unit of a reset source monitoring unit of the present invention.

12: Touch chip

121: Microcontroller

122: static random access memory

123: Flash memory

124: Reset source monitoring unit

120a: reset source

120b: power-on reset source

1201: reset circuit

1202: reset control pin

1203:ESD circuit

1204: Watchdog circuit

Claims (9)

A reset source monitoring circuit applied to a touch chip, characterized in that: the reset source monitoring circuit is coupled between a reset source and a microcontroller to receive a reset signal transmitted by the reset source, and record a first bit to represent a reset state corresponding to the reset source; and the reset source monitoring circuit sends a reset enabling signal to the microcontroller, so that the microcontroller monitors the reset source from the reset source After the circuit reads the first bit, it modifies the first bit into a second bit, and then correspondingly executes a start-up process according to the reset state; wherein, the reset source monitoring circuit includes: a reset enabling unit A plurality of signal input terminals are correspondingly coupled to a plurality of reset signal generation units, and a signal output terminal is coupled to the microcontroller; a plurality of registers are each coupled to a reset signal with a first control terminal thereof a signal generating unit; and an access bus, coupled to a data output end of each of the registers, and simultaneously coupled to a data input end of each of the registers and the microcontroller; wherein, upon receiving any one of the reset After a reset signal sent by the signal generating unit, the reset enabling unit sends a reset enabling signal to the microcontroller, so that the microcontroller reads the registers through the access bus to represent the The first bit of the reset state; after completing the reading of the first bit, the microcontroller modifies the first bit to the second bit. The reset source monitoring circuit as described in Claim 1, wherein the reset source includes the reset signal generating units, and the reset signal generating units include: a reset circuit, a reset control pin, an electrostatic discharge protection circuit, and a watchdog circuit. The reset source monitoring circuit as described in claim 1, wherein the first control terminals of these registers are also coupled to a power-on reset signal transmitted by a power-on reset source, and at least the reset enable unit One of the signal input terminals is coupled to the power-on reset signal at the same time. The reset source monitoring circuit as described in claim 3, wherein the first control terminal is a data clearing terminal or a reset terminal of the register, and a clock signal is accessed by the microcontroller through the access bus The register is then transferred to a second control terminal of the register; the first bit is 0, and the second bit is 1. A touch chip, which contains a microcontroller; it is characterized in that the touch chip has a reset source monitoring circuit, and the reset source monitor circuit is coupled between a reset source and a microcontroller of the touch chip During the interval, it is used to receive a reset signal transmitted by the reset source, so as to record a first bit to represent a reset state corresponding to the reset source; at the same time, the reset source monitoring circuit transmits a reset enable signal to the microcontroller, so that the microcontroller reads the first bit from the reset source monitoring circuit, modifies the first bit into a second bit, and then correspondingly according to the reset state Executing a start-up process; wherein, the reset source monitoring circuit includes: a reset enabling unit, with its multiple signal input terminals correspondingly coupled to multiple reset signal generation units, and its signal output terminal coupled with the microcontroller a plurality of registers, each with a first control terminal coupled to one of the reset signal generating units; and an access bus, coupled to a data output terminal of each of the registers, and simultaneously coupled to each of the registers A data input terminal and the microcontroller; wherein, after receiving a reset signal transmitted by any one of the reset signal generating units, the reset enabling unit sends a reset enabling signal to the microcontroller, so that the microcontroller The controller reads the first bit used to represent the reset state from the registers through the access bus; after completing the reading of the first bit, the microcontroller sets the first bit The element is modified to the second bit. The touch chip according to claim 5, wherein the reset source includes the reset signal generating units, and the reset signal generating units include: a reset circuit, a reset control pin, an electrostatic discharge protection circuit, and a watchdog circuit . The touch chip according to claim 5, wherein, the first control terminals of these registers are also coupled to a power-on reset signal transmitted by a power-on reset source, and at least one of the reset enabling units The signal input end is coupled to the power-on reset signal at the same time. The touch chip as described in claim 7, the first control terminal is the register A data clear terminal or a reset terminal, and a clock signal is sent to a second control terminal of the register when the microcontroller accesses the register through the access bus; the first bit is 0, and the second bit is 1. An information processing device, characterized by having a touch panel and at least one touch chip according to any one of claim 5 to claim 8.

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