TWI779617B - Method for manufacturing semiconductor stack structure with ultra thin die - Google Patents

Abstract

A method for manufacturing a semiconductor stack structure with ultra thin die includes forming a stop-layer structure in a semiconductor substrate by ion implantation, and then disposing an electrical component and interconnecting layer on the active surface of the semiconductor substrate to form a semiconductor wafer. The interconnection layers of the two semiconductor wafers are face to face and bonded together up and down. Then, a backside grinding process and a thinning process are used to sequentially remove part of the semiconductor substrate and the stop-layer structure of the upper semiconductor wafer from the backside of the upper semiconductor wafer, so that the upper semiconductor wafer is formed into a thinned semiconductor wafer. Then, the bonding, back grinding and thinning process of another semiconductor wafer are performed one by one on the thinned semiconductor wafer, so that other thinned semiconductor wafers are sequentially stacked upwards, and finally the bottom semiconductor wafer is back-grinded and thinned. This manufacturing method can stack many layers of thinned semiconductor wafers to meet the requirements of high integration.

Description

Manufacturing method of semiconductor ultra-thin stack structure

The invention relates to a method for manufacturing a semiconductor structure, in particular to a method for manufacturing an ultra-thin semiconductor stack structure.

With the vigorous development of the electronic industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. Among them, semiconductor technology has been widely used in the manufacture of chipsets such as memories and central processing units. In order to achieve high integration and high speed, the size of semiconductor integrated circuits continues to shrink. At present, a variety of different materials and technologies have been developed to meet the above integration and speed requirements, and have also been developed. A stacked structure including multiple substrates is provided to improve the operation speed of the circuit. When the technology related to semiconductor planar packaging has reached its limit, the need for miniaturization can be met through integration. The technology of stacking wafers will greatly help future technology, and it has also become a goal that needs to be improved in current related fields.

The invention provides a method for manufacturing a semiconductor ultra-thin stack structure, which enables the semiconductor ultra-thin stack structure to meet the requirements of high accumulation degree and speed, and has better electrical characteristics and efficiency.

The method for manufacturing a semiconductor ultra-thin stack structure provided by the present invention includes: manufacturing a plurality of semiconductor wafers, selecting one of the semiconductor wafers as the first semiconductor wafer at the bottom, and part of the semiconductor wafers as the second semiconductor wafer to be stacked. A semiconductor wafer and a third semiconductor wafer, the manufacturing steps of each semiconductor wafer include: providing a semiconductor substrate having an opposite active surface and a back surface; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first part of the substrate and The second part of the substrate, wherein the first part of the substrate is located between the stop layer structure and the active surface, the second part of the substrate is located between the stop layer structure and the back surface, the stop layer structure includes at least a silicon nitride layer, and the manufacture of the silicon nitride layer includes a prior Nitrogen ion implantation process is performed on the first depth of the semiconductor substrate, followed by high temperature treatment process, so that the nitrogen ion implanted area forms a silicon nitride layer; and multiple electrical components and interconnection layers are arranged on the active surface, and the interconnection layer It includes a plurality of interconnection points, and a plurality of conductive structures are arranged on the first part of the substrate to connect the interconnection layer and the stop layer structure. Flip-chip the second semiconductor wafer relative to the first semiconductor wafer, make the interconnection layer of the first semiconductor wafer and the interconnection layer of the second semiconductor wafer face each other and bond them together by hybrid bonding technology; perform the first backside grinding process, grinding from the backside of the second semiconductor wafer to remove a part of the second portion of the substrate of the second semiconductor wafer; performing a first thinning process to form a thinned second semiconductor wafer; performing a second Two backside grinding processes, grinding from the backside of the first semiconductor wafer to remove a portion of the second portion of the substrate of the first semiconductor wafer; and performing a second thinning process to form a thinned first semiconductor wafer, Wherein, the first thinning process and the second thinning process include a substrate removal step and a stop layer removal step, wherein the substrate removal step removes the remaining second part of the substrate to reveal the stop layer structure; the stop layer removal step removes the stop layer structure to expose the first portion of the substrate and the conductive structure.

In an embodiment of the present invention, before performing the above-mentioned second back grinding process, a plurality of thinned third semiconductor wafers can be stacked sequentially on the thinned second semiconductor wafer, wherein each thinned The stacking step of the third semiconductor wafer includes: flipping the third semiconductor wafer relative to the first semiconductor wafer, so that the interconnection layer of the third semiconductor wafer and the first part of the substrate of the thinned second semiconductor wafer are opposite and bonding together; performing a third backside grinding process, grinding from the backside of the third semiconductor wafer to remove a portion of the second portion of the substrate of the third semiconductor wafer; and performing a third thinning process, including a substrate removal step and stop layer removal steps.

In an embodiment of the present invention, the above stop layer structure further includes a silicon dioxide layer, and the silicon dioxide layer is disposed on the silicon nitride layer so as to be between the silicon nitride layer and the active surface.

In one embodiment of the present invention, the step of forming the above-mentioned silicon dioxide layer includes: after the nitrogen ion implantation process, performing an oxygen ion implantation process at a second depth of the semiconductor substrate, and the second depth is smaller than the first Depth, followed by a high temperature treatment process to form a silicon dioxide layer in the region implanted with oxygen ions.

In an embodiment of the present invention, the above step of removing the stopper layer includes: removing the silicon nitride layer first, and then removing the silicon dioxide layer.

In an embodiment of the present invention, the substrate removal step is selected from one of chemical mechanical polishing, wet etching and plasma dry etching, wherein the selectivity ratio of silicon and silicon nitride is between 20 and 80.

In an embodiment of the present invention, the removal method of the silicon nitride layer and the silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching, wherein the selectivity of silicon nitride and silicon dioxide is relatively low. Between 10 and 20, the selectivity ratio of silicon dioxide and silicon is about 5.

In an embodiment of the present invention, the distance between the stop layer structure and the active surface is between 1 micron and 5 microns, and the thickness of the thinned second semiconductor wafer is not greater than 12 microns.

In one embodiment of the present invention, after forming the above-mentioned thinned first semiconductor wafer, the following steps are further included: arranging a plurality of Solder balls are used to electrically connect the conductive structures respectively; and electrical testing and singulation are performed.

The method for manufacturing a semiconductor ultra-thin stack structure provided by the present invention includes manufacturing a plurality of semiconductor wafers, and the manufacturing steps of each semiconductor wafer include: providing a semiconductor substrate with a relative active surface and a back surface; forming a stop layer structure on the semiconductor In the substrate, the semiconductor substrate is divided into a first part of the substrate and a second part of the substrate, wherein the first part of the substrate is located between the stop layer structure and the active surface, and the second part of the substrate is located between the stop layer structure and the back surface, and the stop layer structure contains at least nitrogen The manufacture of the silicon nitride layer and the silicon nitride layer includes a nitrogen ion implantation process at the first depth of the semiconductor substrate, followed by a high temperature treatment process to form a silicon nitride layer in the area implanted with nitrogen ions; A plurality of electrical components and an interconnection layer, the interconnection layer includes a plurality of interconnection points, and a plurality of conductive structures are arranged on the first part of the substrate to connect the interconnection layer and the stop layer structure. One of the semiconductor wafers is selected as the first semiconductor wafer of the bottom layer, and part of the semiconductor wafers are then singulated as the first batch of semiconductor wafers to be stacked and at least one second batch of semiconductor wafers; Flip-chip on the first semiconductor wafer, make the interconnection layer of the first batch of semiconductor wafers and the interconnection layer of the first semiconductor wafer face each other and bond them together by hybrid bonding technology; perform the first molding process, in order to A first encapsulant is formed on a semiconductor wafer to cover the first batch of semiconductor wafers; a first back grinding process is performed to remove part of the first encapsulant and remove the first encapsulant from the side of the first encapsulant away from the first semiconductor wafer. Part of the second portion of the substrate of the batch of semiconductor wafers; a first thinning process is performed to form a first semiconductor wafer layer; a second back grinding process is performed to grind from the back of the first semiconductor wafer to remove the first semiconductor a portion of the second portion of the substrate of the wafer; and performing a second thinning process to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process include a substrate removal step and a stop layer removal step , wherein the substrate removing step removes the remaining second portion of the substrate to expose the stop layer structure, and the stop layer removing step removes the stop layer structure to expose the first portion of the substrate and the conductive structure.

In an embodiment of the present invention, before performing the second back grinding process, at least one second semiconductor wafer layer can be stacked sequentially on the first semiconductor wafer layer, wherein each second semiconductor wafer layer The stacking step includes: flipping the second batch of semiconductor wafers relative to the first semiconductor wafer, so that the interconnection layer of the second batch of semiconductor wafers and the first part of the substrate of the first semiconductor wafer layer are opposite and bonded together; A molding process to form a second encapsulant on the first semiconductor wafer layer to cover the second batch of semiconductor wafers; perform a third back grinding process to remove part of the second encapsulant from the side of the second encapsulant away from the first semiconductor wafer layer. encapsulating colloid and removing a part of the second portion of the substrate of the second batch of semiconductor chips; and performing a third thinning process, including a substrate removal step and a stopper layer removal step.

The manufacturing method of the semiconductor ultra-thin stack structure provided by the present invention includes: providing a carrier board, and forming a plurality of first conductive pillars on the carrier board. A plurality of semiconductor wafers are provided, and the manufacturing steps of each semiconductor wafer include: providing a semiconductor substrate having an opposite active surface and a back surface; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first part of the substrate and a second part of the substrate, The first part of the substrate is located between the stop layer structure and the active surface, the second part of the substrate is located between the stop layer structure and the back surface, the stop layer structure includes at least a silicon nitride layer, and the manufacture of the silicon nitride layer includes the first step prior to the semiconductor substrate. A nitrogen ion implantation process is carried out in depth, and then a high temperature treatment process is performed to form a silicon nitride layer in the area implanted with nitrogen ions; multiple electrical components and interconnection layers are arranged on the active surface, and the interconnection layer includes multiple interconnection points , and disposing a plurality of conductive structures on the first part of the substrate to connect the interconnection layer and the stop layer structure; and performing singulation. A first batch of semiconductor chips and at least one second batch of semiconductor chips are sorted out from the semiconductor chips. The first batch of semiconductor chips includes a plurality of first semiconductor chips, and the second batch of semiconductor chips includes a plurality of second semiconductor chips. The first batch of semiconductor chips is flip-chip disposed on the carrier board, and the first conductive pillars are interposed between adjacent first semiconductor chips, wherein the interconnection layer of the first batch of semiconductor chips is adjacent to the carrier board and the semiconductor substrate is away from the carrier board. A first molding process is performed to form a first encapsulant encapsulating the first batch of semiconductor chips and the first conductive pillars on the carrier board. A first back grinding process is performed to remove part of the first encapsulant from the side of the first encapsulant away from the carrier plate and remove a part of the second portion of the substrate of the first batch of semiconductor chips. performing a first thinning process to form a first semiconductor wafer layer, the first thinning process includes sequentially removing the remaining second portion of the substrate and the stop layer structure of the first batch of semiconductor wafers to expose the first portion of the substrate, the conductive structure and the first conductive column. A plurality of second conductive pillars are provided to electrically connect part of the conductive structures of the first semiconductor wafer layer. The second batch of semiconductor chips is flip-chip arranged on the first semiconductor chip layer, wherein the second semiconductor chips are respectively bridged between the adjacent first semiconductor chips, so that the interconnection layers of the second semiconductor chips are electrically connected to the exposed first semiconductor chips. A conductive column and a part of the conductive structure of the first semiconductor chip layer, and a part of the second conductive column is interposed between adjacent second semiconductor chips. A second molding process is performed to form a second encapsulant on the first semiconductor chip layer to cover the second batch of semiconductor chips and the second conductive pillars. A second back grinding process is performed to remove part of the second encapsulant from the side of the second encapsulant away from the layer of the first semiconductor chip and remove a part of the second part of the substrate of the second batch of semiconductor chips. performing a second thinning process to form a second semiconductor wafer layer, the second thinning process includes sequentially removing the remaining second portion of the substrate and the stop layer structure of the second batch of semiconductor wafers to expose the first portion of the substrate, the conductive structure and the second conductive column. The carrier board is removed to expose the interconnection layer and the first conductive column of the first semiconductor chip layer.

In one embodiment of the present invention, after removing the above-mentioned carrier plate, the following steps are further included: setting a plurality of solder balls on the side of the first semiconductor chip layer far away from the second semiconductor chip layer to electrically connect them respectively the interconnection layer and the first conductive column; and performing singulation.

In an embodiment of the present invention, the plurality of first semiconductor chips in the above-mentioned first batch of semiconductor chips have different electrical functions.

In an embodiment of the present invention, the second semiconductor chips of the above-mentioned second batch of semiconductor chips have different electrical functions.

When the present invention manufactures semiconductor wafers, the ion implantation process is used to form a stop layer structure in the semiconductor substrate first, and then electrical components and interconnection layers are arranged on the active surface of the semiconductor substrate; after that, the two semiconductor wafers are bonded up and down, also Or after the semiconductor wafer is diced to form a plurality of semiconductor wafers, the batch of semiconductor wafers is combined with the bottom semiconductor wafer. After each semiconductor wafer/chip is bonded (and molded encapsulant), the backside grinding and thinning process is used to remove part of the semiconductor substrate and stop layer structure of the upper semiconductor wafer/chip from the back of the upper semiconductor wafer/chip Make the upper semiconductor wafer/chip form a thinned semiconductor wafer/semiconductor chip layer, and then carry out bonding (and molding encapsulant) of another semiconductor wafer/chip on the thinned semiconductor wafer/chip one by one, back grinding and Thinning process, and another thinned semiconductor wafer/semiconductor wafer layer is stacked on top, and finally the bottom semiconductor wafer is subjected to back grinding and thinning process. Since the thickness of each thinned semiconductor wafer/semiconductor wafer layer is not greater than 12 microns, it can be stacked to 57 wafer layers under the limit of the total wafer thickness of 700 microns, thereby meeting the requirements of high integration and speed.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

1A to 1S are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a first embodiment of the present invention. First, manufacture a plurality of semiconductor wafers 10 (marked in FIG. 1E ), select one of the semiconductor wafers 10 as the first semiconductor wafer 10a (marked in FIG. 1F ) at the bottom of the stack, and the other semiconductor wafers 10 are used as the first semiconductor wafer 10a to be stacked. The second semiconductor wafer 10b (indicated in FIG. 1F) and the third semiconductor wafer 10c (indicated in FIG. 1L ), the manufacturing process of a plurality of semiconductor wafers 10 is the same or similar, as shown in FIGS. 1A to 1E. A schematic cross-sectional view of the semiconductor wafer 10 . As shown in FIG. 1A, a semiconductor substrate 12 is provided. The semiconductor substrate 12 is, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or Silicon on insulation (SOI) substrate, in one embodiment, the thickness of the semiconductor substrate is, for example, 700 to 800 microns (um), preferably 775 microns, and the semiconductor substrate 12 has an active surface 121 and a back surface opposite 122.

Next, a stop layer structure is formed in the semiconductor substrate 12 . In one embodiment, manufacturing the stop layer structure includes performing at least one ion implantation process and high temperature treatment process. In one embodiment, the ion implantation process includes nitrogen ion implantation first, and then oxygen ion implantation. As shown in FIG. 1B and FIG. 1C, the nitrogen ion implantation process 14 is first performed at the first depth D1 of the semiconductor substrate 12, and then the oxygen ion implantation process 16 is performed at the second depth D2 of the semiconductor substrate 12. In one embodiment The first depth D1 of the nitrogen ion implantation region 14' is, for example, a depth of about 1 to 5 microns from the active surface 121, and the second depth D2 of the oxygen ion implantation region 16' is deeper than the first depth D2 of the nitrogen ion implantation region 14. The depth D1 is small, that is, the oxygen ion implantation region 16 ′ is closer to the active surface 121 .

Afterwards, a high-temperature treatment is performed, as shown in FIG. 1D, a silicon nitride (Si3N4) layer 14a is formed in the nitrogen ion implantation region 14', and a silicon dioxide (SiO2) layer 16a is formed in the oxygen ion implantation region 16', wherein two The silicon oxide layer 16a is relatively close to the active surface 121, and the silicon nitride layer 14a is relatively close to the back surface 122. In this embodiment, the silicon nitride layer 14a and the silicon dioxide layer 16a constitute the above-mentioned stop layer structure 18, wherein the silicon dioxide The silicon layer 16 a is located on the silicon nitride layer 14 and between the silicon nitride layer 14 a and the active surface 121 . In one embodiment, the thickness of the silicon nitride layer 14 a and the silicon dioxide layer 16 a is, for example, 500 nanometers (nm). For ease of description, the semiconductor substrate 12 between the silicon dioxide layer 16a of the stop layer structure 18 and the active surface 121 is called the first part 123 of the substrate, and the semiconductor substrate between the silicon nitride layer 14a of the stop layer structure 18 and the back surface 122 12 is referred to as the second substrate portion 124 . In one embodiment, when the semiconductor wafer 10 is subsequently applied in the manufacture of metal oxide semiconductor field effect transistors (MOSFETs), the depth of the general N well (N well) is about 2 microns, so the substrate The thickness of the first part 123 should be kept at not less than 2 microns, that is, when the nitrogen ion implantation process 14 and the oxygen ion implantation process 16 are performed, the first depth D1 and The second depth of the oxygen ion implantation region 16 ′ should be slightly greater than 2 μm.

Continuing the above description, as shown in FIG. 1E , a plurality of electrical components 20 and an interconnection layer 22 having interconnection points 221 are provided on the active surface 121. The electrical components 20 include metal oxide semiconductor (MOS), for example, and are placed on the first substrate of the substrate. A portion 123 is provided with a plurality of conductive structures. In one embodiment, the conductive structure includes, for example, a through silicon via (TSV) 24 , and the through silicon via 24 vertically connects the interconnection layer 22 and the silicon dioxide layer 16 a of the stop layer structure 18 . The manufacturing process of electrical components 20, interconnection layer 22 and TSV 24 includes front-end-of-line (FEOL) and back-end-of-line (BEOL) of general semiconductor manufacturing process. The manufacturing process, for example, makes elements such as resistors, capacitors, diodes, and transistors on the semiconductor substrate 12, and the back-end process, for example, makes metal wiring for connection between each element and interconnection points 221; in one embodiment, the interconnection points 221 For example copper contacts. FIG. 1E is a schematic diagram of a semiconductor wafer 10 according to an embodiment of the present invention. The first semiconductor wafer 10a, the second semiconductor wafer 10b, and the third semiconductor wafer 10c described below follow the semiconductor wafer 10 to describe the components used. symbol. Wherein the position of the TSV 24 of the first semiconductor wafer 10a corresponds, for example, to the installation position of the solder ball in the subsequent process, and the position of the TSV 24 of the second semiconductor wafer 10b, for example, corresponds to the interconnection layer 22 of the third semiconductor wafer 10c. The interconnection point 221 corresponds to.

As shown in FIG. 1F, the second semiconductor wafer 10b is flipped relative to the first semiconductor wafer 10a, so that the interconnection layers 22 of the first semiconductor wafer 10a and the second semiconductor wafer 10b are opposite and the interconnection points 221 are respectively Corresponding; then use hybrid bonding technology (Hybrid bonding), as shown in Figure 1G, make the first semiconductor wafer 10a and the second semiconductor wafer 10b stack together up and down, wherein the hybrid bonding technology includes copper-to-copper bonding and back Fire and other processes.

Then, use a first backside grinding (Grind) process to grind from the backside 122 of the second semiconductor wafer 10b to remove a part of the second portion 124 of the substrate of the second semiconductor wafer 10b, as shown in FIG. The second substrate portion 124 is thin. In one embodiment, the remaining second portion 124 of the substrate has a thickness of about 20.

Afterwards, a first thinning process is performed to form a thinned second semiconductor wafer. The first thinning process includes a substrate removal step and a stopper layer removal step, as shown in FIGS. 1I to 1K. schematic diagram. The substrate removal step is used to remove the remaining second portion 124 of the substrate, as shown in FIG. 1I, to reveal the stop layer structure 18, for example, to expose the silicon nitride layer 14a. Chemical mechanical polishing (CMP) process, wherein, the selection ratio of silicon and silicon nitride is, for example, 20, that is, Si/Si3N4 is 20; the stop layer removal step is used to remove the stop layer structure 18, that is, sequentially remove The silicon nitride layer 14a and the silicon dioxide layer 16a are used to expose the first portion 123 of the substrate and the TSV 24; in one embodiment, the silicon nitride layer 14a is first removed by the second chemical mechanical polishing process, as shown in FIG. 1J , to expose the silicon dioxide layer 16a, wherein the selection ratio of silicon nitride and silicon dioxide is, for example, 10, that is, Si3N4/SiO2 is 10; then the silicon dioxide layer 16a is removed by the third chemical mechanical polishing process, as shown in the figure As shown in 1K, the first part 123 of the substrate and the TSV 24 are exposed, wherein the selection ratio of silicon dioxide and silicon is, for example, 5, that is, SiO2/Si is 5. By exposing the first portion 123 of the substrate and the TSV 24, a thinned second semiconductor wafer 10b' is formed.

Continuing the above description, the stacking of the first semiconductor wafer 10a and the thinned second semiconductor wafer 10b' has been completed; then, as shown in FIG. 1L, the third semiconductor wafer 10c is inverted relative to the first semiconductor wafer 10a installed so that the interconnection layer 22 of the third semiconductor wafer 10c faces the substrate first portion 123 of the thinned second semiconductor wafer 10b', in one embodiment, the interconnection layer 22 of the third semiconductor wafer 10c The connection points 221 respectively correspond to the TSVs 24 of the thinned second semiconductor wafer 10 b ′. Afterwards, the above-mentioned first back grinding process and first thinning process are repeated to complete the stacking of the thinned third semiconductor wafer 10c' and the thinned second semiconductor wafer 10b'. In one embodiment, the thinned third semiconductor wafer 10b' is stacked. The thickness of the second semiconductor wafer 10b' or the thinned third semiconductor wafer 10c' is, for example, 12 microns. In this way, on the premise of having a plurality of semiconductor wafers 10, the above-mentioned bonding process, the first back grinding process and the first thinning process are repeated one by one to complete the multi-layer thinned semiconductor wafer 10' The stacking with the first semiconductor wafer 10a, as shown in FIG. 1M , in one embodiment, as the uppermost thinned semiconductor wafer 10 ′, the first portion 123 of the substrate does not need to be formed with TSVs 24 .

After completing the stacking of a predetermined number of thinned semiconductor wafers 10', a second backside grinding process is used to grind from the backside 122 of the first semiconductor wafer 10a, as shown in FIG. 1N, to remove the first semiconductor wafer. 10a, a part of the second part 124 of the substrate, and the second part 124 of the substrate with an extremely thin thickness is left; then, the second thinning process is performed, as shown in FIG. 1O to FIG. 1Q, using the above-mentioned substrate removal step and stop layer removal step , to sequentially remove the remaining substrate second portion 124, silicon nitride layer 14a and silicon dioxide layer 16a of the first semiconductor wafer 10a, thereby revealing the thinned first substrate portion 123 and silicon dioxide layer 123 of the first semiconductor wafer 10a'. Through the holes 24 , the stacking of multiple thinned semiconductor wafers 10 ′ such as the thinned first semiconductor wafer 10 a ′, the thinned second semiconductor wafer 10 b ′, the thinned third semiconductor wafer 10 c ′ . . . is completed.

Afterwards, as shown in FIG. 1R , a plurality of solder balls 26 are provided on the side of the thinned first semiconductor wafer 10 a ′ away from the thinned second semiconductor wafer 10 b ′ to electrically connect the exposed TSVs 24 ; And after carrying out chip probing (CP) to carry out electrical function test (Test), carry out singulation (die saw) to complete the semiconductor ultra-thin stack structure 28 as shown in FIG. 1S, Wherein each thinned semiconductor wafer 10' is singulated as a semiconductor wafer layer 10", since the thickness of each thinned semiconductor wafer 10' can be, for example, 12 microns, the total thickness of the wafer is limited to 700 microns According to the embodiment of the present invention, up to 57 thinned semiconductor wafer layers 10" can be stacked in the semiconductor ultra-thin stack structure 28, which can meet the requirements of high density and speed, and has better electrical characteristics and efficiency.

In the first thinning process and the second thinning process above, the substrate removal step and the stop layer removal step include three chemical mechanical polishing processes as an example for illustration, but it is not limited thereto. In another embodiment , the first/second thinning process includes a wet etching process and two chemical mechanical polishing processes, that is, in the substrate removal step, the wet etching process is used to replace the first chemical mechanical polishing process, and the cross-sectional schematic diagram of the thinning process Still refer to FIG. 1H to FIG. 1K or FIG. 1N to FIG. 1Q, the remaining second part 124 of the substrate is removed by a wet etching process to expose the silicon nitride layer 14a, and silicon and nitrogen in the wet etching process The selection ratio of silicon oxide is, for example, 40, that is, Si/Si3N4 is 40; and then the second chemical mechanical polishing process and the third chemical mechanical polishing process are sequentially performed to sequentially remove the silicon nitride layer 14a and the silicon dioxide layer 16a remove.

In yet another embodiment, the first/second thinning process can also be replaced by three plasma dry etching (plasma dry etching) processes. The schematic cross-sectional view of the thinning process can still refer to FIG. 1H As shown in FIG. 1K or FIG. 1N to FIG. 1Q, the remaining second portion 124 of the substrate is removed by the first plasma dry etching process to reveal the silicon nitride layer 14a. In one embodiment, the first plasma The selectivity ratio of silicon and silicon nitride in dry etching is, for example, 80, that is, Si/Si3N4 is 80; then, the silicon nitride layer 14a is removed by the second plasma dry etching process to expose the silicon dioxide layer 16a, and then In one embodiment, the selection ratio of silicon nitride and silicon dioxide in the second plasma dry etching process is, for example, 20, that is, Si3N4/SiO2 is 20; then, the third plasma dry etching process is used to remove silicon dioxide layer 16a to expose the first portion 123 of the substrate and the TSV 24. In one embodiment, the selection ratio of silicon dioxide and silicon in the third plasma dry etching process is, for example, 5, that is, SiO2/Si is 5.

In the above-mentioned first embodiment, it is carried out in the way of stacking wafers on wafers (Wafer on Wafer, WoW), but it is not limited to this. Figure 2A to Figure 2K show a second embodiment of semiconductor ultra-thin stacking of the present invention. Schematic cross-sectional illustration of the fabrication method of the structure. In this second embodiment, a plurality of semiconductor wafers 10 are firstly provided, the manufacturing steps of which have been disclosed in the above-mentioned FIG. 1A to FIG. The first semiconductor wafer 10a (marked in FIG. 2B ), another part of the semiconductor wafer 10 is subjected to an electrical function test, and the crystal grains with good electrical properties are selected for singulation, as shown in FIG. 2A , to obtain multiple semiconductor wafers. 30. Each semiconductor wafer 30 still includes electrical components 20, an interconnection layer 22, and a semiconductor substrate 12. A stop layer structure 18 is formed in the semiconductor substrate 12. The stop layer structure 18 divides the semiconductor substrate 12 into a first part 123 of the substrate and a second part of the substrate. The second part 124 is the first part 123 of the substrate, and TSVs 24 are formed to connect the stop layer structure 18 and the interconnection layer 22 . For the convenience of description, the plurality of semiconductor wafers 30 are divided into the first batch of semiconductor wafers 30 a and the second batch of semiconductor wafers 30 b according to the sequence of the subsequent manufacturing process, and each batch includes a plurality of semiconductor wafers 30 .

As shown in FIG. 2B, the first batch of semiconductor wafers 30a are flipped relative to the first semiconductor wafer 10a, so that the interconnection layer 22 of the first batch of semiconductor wafers 30a and the interconnection layer 22 of the first semiconductor wafer 10a are opposite and The interconnection points 221 correspond to each other; then, the first semiconductor wafer 10 a and the first batch of semiconductor wafers 30 a are bonded together up and down by hybrid bonding technology, as shown in FIG. 2C .

Next, a first molding (molding) process is carried out, as shown in FIG. 2D, a first packaging compound (molding compound) 32a is formed on the first semiconductor wafer 10a to cover the first batch of semiconductor wafers 30a; after that, use the first The backside grinding process removes part of the first encapsulant 32a and a part of the second portion 124 of the substrate of the first batch of semiconductor wafers 30a from the side of the first encapsulant 32a away from the first semiconductor wafer 10a, as shown in FIG. 2E, the first In the batch of semiconductor wafers 30a, the second substrate portion 124 with an extremely thin thickness and the first encapsulant 32a flush with the second substrate portion 124 remain.

Afterwards, the first thinning process is carried out, including the substrate removal step and the stop layer removal step described in the first embodiment, so as to remove the remaining second substrate portion 124, stop layer structure 18 and part of the first batch of semiconductor wafers 30a The encapsulant 32, as shown in FIG. 2F, exposes the first portion 123 of the substrate of the first batch of semiconductor chips 30a and the through-silicon vias 24, so that a thinned first semiconductor chip layer 30a' is formed, and the first semiconductor chip layer 30a' is stacked. on the first semiconductor wafer 10a.

Next, the second batch of semiconductor wafers 30b are still flipped relative to the first semiconductor wafer 10a, so that the interconnection layers 22 of the second batch of semiconductor wafers 30b correspond to the substrate first portion 123 of the first semiconductor wafer layer 30a' respectively, and Bonding the second batch of semiconductor wafers 30b to the first semiconductor wafer layer 30a'; performing a second molding process to form a second encapsulant 32b on the first semiconductor wafer layer 30a' to cover the second batch of semiconductor wafers 30b; Carry out the back grinding process and the thinning process, so as to remove part of the second encapsulant 32b and the second part of the substrate of the second batch of semiconductor chips 30b (not shown) from the side of the second encapsulant 32b away from the first semiconductor chip layer 30a' ) and stop layer structure (not shown), as shown in FIG. 2G , revealing the substrate first portion 123 and TSVs 24 of the second batch of semiconductor wafers 30b to form a thinned second semiconductor wafer layer 30b'. In this way, the bonding process, molding process, back grinding process and first thinning process of the above-mentioned batches of semiconductor wafers 30 are repeated batch by batch to complete the first semiconductor wafer layer 30a' and the multi-layer second semiconductor wafer layer 30b' Stacking with the first semiconductor wafer 10a, as shown in FIG. 2H , in one embodiment, as the uppermost second semiconductor wafer layer 30b ′, the first portion 123 of the substrate does not need to be formed with TSVs 24 .

Next, similar to the first embodiment, after completing the stacking of a predetermined number of second semiconductor wafer layers 30b', a second back grinding process and a second thinning process are sequentially applied from the back surface 122 of the first semiconductor wafer 10a. Remove the second substrate portion 124 and the stop layer structure 18 of the first semiconductor wafer 10a, as shown in FIG. A stack of semiconductor wafers 30.

The above-mentioned first and second thinning processes include the substrate removal step and the stop layer removal step described in the first embodiment, wherein the process selection for the substrate removal step and the stop layer removal step is, for example, three chemical mechanical polishing processes, or Whether it is a wet etching process combined with a chemical mechanical polishing process, or both are plasma dry etching processes, and the selection ratio between materials such as silicon, silicon nitride, and silicon dioxide has been described in the first embodiment, here No longer.

Afterwards, as shown in FIG. 2J , solder balls are placed on the exposed through-silicon vias 24 of the thinned first semiconductor wafer 10 a ′, and after performing an electrical function test, along the first encapsulant 32 a and the second The dicing line 321 of the encapsulant 32b is singulated to complete the semiconductor ultra-thin stack structure 34 as shown in FIG. 2K . In the semiconductor ultra-thin stack structure 34 of this embodiment, since the semiconductor wafers 30 to be stacked have been tested and sorted for electrical functions, the yield rate of the semiconductor ultra-thin stack structure 34 is relatively high.

3A to 3L are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a third embodiment of the present invention. In the third embodiment, firstly, a carrier board 40 is provided, and a plurality of first conductive pillars 42 are formed on the carrier board 40, as shown in FIG. ) glass, the first conductive pillar 42 is, for example, a copper pillar.

Then, pick a plurality of semiconductor wafers 44 (marked in FIG. 3B ) through the electrical function test. The semiconductor wafers 44 can have the same or different electrical functions. The various semiconductor wafers 44 are separated by cutting the various semiconductor wafers 10 respectively. However, the manufacturing steps of each semiconductor wafer 10 have been disclosed in the aforementioned FIGS. 1A to 1E , and will not be repeated here. Each semiconductor wafer 44 still includes electrical components 20, an interconnection layer 22, and a semiconductor substrate 12. A stop layer structure 18 is formed in the semiconductor substrate 12. The stop layer structure 18 divides the semiconductor substrate 12 into a first substrate portion 123 and a second substrate portion. 124 , the first portion 123 of the substrate is formed with TSVs 24 to connect the stop layer structure 18 and the interconnection layer 22 . In one embodiment, the thickness of the semiconductor substrate 12 is, for example, 775 microns, and the thickness of the interconnection layer 22 is, for example, 10 microns.

The first batch of semiconductor chips picked are flip-chip bonded on the carrier plate 40, as shown in FIG. have the same or different electrical functions, and the first conductive pillars 42 are interposed between adjacent first semiconductor chips 44a. 22 is adjacent to the carrier board 40 and the semiconductor substrate 12 is away from the carrier board 10 for flip-chip bonding.

Afterwards, a first molding process is performed. As shown in FIG. 3C , a first encapsulant 46 a is formed on the carrier board 40 to cover the three first semiconductor chips 44 a and the first conductive pillars 42 . Next, a part of the first encapsulant 46a and the second substrate portion 124 and stop layer of the first semiconductor chip 44a are removed from the side of the first encapsulant 46a away from the carrier plate 40 by using the first back grinding process and the first thinning process. The structure 18, as shown in FIG. 3D, exposes the first portion 123 of the substrate, the TSVs 24, and the first conductive pillars 44, thus forming a thinned first semiconductor wafer layer 44a'.

Afterwards, the setting of the second conductive column 48 is carried out. For example, the second conductive column 48 is vertically arranged on part of the TSV 24, as shown in FIG. 3E, on at least one TSV 24 of each thinned first semiconductor wafer 44a A second conductive pillar 48 is provided, and the second conductive pillar 48 is, for example, a copper pillar. Afterwards, the second batch of semiconductor wafers selected are flip-chip-connected between two adjacent thinned first semiconductor wafers 44a, as shown in FIG. , the two semiconductor wafers 44b may have the same or different electrical functions. In one embodiment, the interconnection layer 22 of the second semiconductor wafer 44b is opposite to the substrate first portion 123 of the first semiconductor wafer layer 44a', and the second semiconductor wafer 44b The interconnection point 221 of the chip 44b forms an electrical connection with a part of the TSV 24 and the first conductive pillar 42, and a part of the second conductive pillar 48 is interposed between the adjacent second semiconductor chips 44b.

Then, the second molding process, the second back grinding process and the second thinning process are performed in order to form a second encapsulant 46b on the first semiconductor chip layer 44a' to cover the second semiconductor chip 44b and the second conductive After the post 48, the second substrate portion 124 of the second semiconductor wafer 44b, the stop structure layer 18, and part of the second encapsulant 46b are removed by a second back grinding process and a second thinning process, as shown in FIG. 3G , exposing the first portion 123 of the substrate, the TSVs 124, and the second conductive pillars 48, thus forming a thinned second semiconductor wafer layer 44b'.

In this way, the arrangement of the third conductive pillar 50, the flip-chip arrangement of the third semiconductor chip 44c on the second semiconductor chip layer 44b', the encapsulation molding process, the back grinding process and the thinning process are repeated to complete the third semiconductor chip. The stacking of wafer layers 44c' is shown in FIG. 3H, and the stacking of successively more semiconductor wafer layers is shown in FIG. 3I.

Afterwards, remove the carrier board 40, as shown in FIG. ) and the first conductive pillars are provided with solder balls 26, as shown in FIG. 3K, and singulated to complete the semiconductor ultra-thin stack structure 52 shown in FIG. 3L.

In the manufacturing method of the semiconductor ultra-thin stacked structure of the first/second/third embodiment above, the manufacture of the stop layer structure is to implant nitrogen ions and oxygen ions successively, and perform high temperature treatment to form a silicon nitride layer and The silicon dioxide layer is described as an example, but it is not limited thereto. In one embodiment, the stop layer structure may only include a silicon nitride layer, that is, a high-temperature treatment process is performed after the nitrogen ion implantation process is performed in the semiconductor substrate, In order to form a silicon nitride layer at a depth of 1 to 5 microns from the active surface; correspondingly, only the silicon nitride layer needs to be removed in the stop layer removal step of the subsequent first/second thinning process, and the other subsequent processes The same, and will not be repeated here.

In the embodiment of the present invention, the semiconductor substrate can be polished or etched to only Retain the first part of the substrate, that is, only retain the thickness of the substrate from 1 to 5 microns, so that the overall thickness of each semiconductor wafer layer is not greater than 12 microns. Under the limitation of the total thickness of the wafer to 700 microns, the semiconductor superconductor of the embodiment of the present invention Up to 50 layers of thinned semiconductor wafers can be stacked in the thin stack structure 28 , which can meet the requirements of high density and speed, and has better electrical characteristics and efficiency.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

10, 10': semiconductor wafer 10a, 10a': the first semiconductor wafer 10b, 10b': the second semiconductor wafer 10c: the third semiconductor wafer 10": semiconductor wafer layer 12: Semiconductor substrate 121: active side 122: back 123: Substrate Part 1 124: Substrate Part II D1: first depth D2: second depth 14: Nitrogen ion implantation process 14': Nitrogen ion implantation area 14a: silicon nitride layer 16: Oxygen ion implantation process 16': Oxygen ion implantation area 16a: Silicon dioxide layer 18: Stop layer structure 20: Electrical components 22: Inner layer 221: interconnection point 24: TSV 26: solder ball 28, 34, 52: Semiconductor ultra-thin stack structure 30: Semiconductor wafer 30a: First batch of semiconductor wafers 30a': first semiconductor wafer layer 30b: Second batch of semiconductor wafers 30b': second semiconductor wafer layer 32a: the first packaging colloid 32b: the second packaging colloid 321: cutting road 40: Loading board 42: The first conductive column 44: Semiconductor wafer 44a: first semiconductor wafer 44a': first semiconductor wafer layer 44b: second semiconductor wafer 44b': second semiconductor wafer layer 44c: the third semiconductor wafer 44c': the third semiconductor wafer layer 46a: the first packaging colloid 46b: Second encapsulation colloid 48: The second conductive column 50: The third conductive column

1A to 1S are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a first embodiment of the present invention. 2A to 2K are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a second embodiment of the present invention. 3A to 3L are schematic cross-sectional views of a method for manufacturing an ultra-thin semiconductor stack structure according to a third embodiment of the present invention.

10: Semiconductor wafer

123: Substrate Part 1

124: Substrate Part II

14a: silicon nitride layer

16a: Silicon dioxide layer

18: Stop layer structure

20: Electrical components

22: Inner layer

221: interconnection point

24: TSV

Claims (16)

A method for manufacturing a semiconductor ultra-thin stack structure, comprising: manufacturing a plurality of semiconductor wafers, selecting one of the semiconductor wafers as the first semiconductor wafer as one of the bottom layers, and part of the semiconductor wafers as the first semiconductor wafer to be stacked A second semiconductor wafer and at least one third semiconductor wafer, the manufacturing steps of each of the semiconductor wafers include: providing a semiconductor substrate with an active surface and a back surface opposite to each other; forming a stop layer structure on the semiconductor substrate Inside, the semiconductor substrate is divided into a substrate first part and a substrate second part, wherein the substrate first part is located between the stop layer structure and the active surface, and the substrate second part is located between the stop layer structure and the back surface Between, the stop layer structure at least includes a silicon nitride layer, the manufacture of the silicon nitride layer includes performing a nitrogen ion implantation process at a first depth of the semiconductor substrate, and then performing a high temperature treatment process to make the nitrogen The silicon nitride layer is formed in the region of ion implantation; and a plurality of electrical elements and an interconnection layer are arranged on the active surface, the interconnection layer includes a plurality of interconnection points, and a plurality of conductive structures are arranged in the first part of the substrate Connecting the interconnection layer and the stop layer structure; flipping the second semiconductor wafer relative to the first semiconductor wafer, so that the interconnection layer of the first semiconductor wafer and the interconnection layer of the second semiconductor wafer The interconnection layers are opposite and bonded together by a hybrid bonding technique; a first backside grinding process is performed to grind from the backside of the second semiconductor wafer to remove the second substrate of the second semiconductor wafer A portion of the portion; performing a first thinning process to form a thinned second semiconductor wafer; performing a second back grinding process from the back of the first semiconductor wafer to remove a portion of the second portion of the substrate of the first semiconductor wafer; and performing a second thinning process to form a Thinning the first semiconductor wafer, wherein the first thinning process and the second thinning process include: a substrate removal step, removing the remaining second portion of the substrate to reveal the stop layer structure; and a stop In the layer removing step, the stop layer structure is removed to reveal the first part of the substrate and the conductive structures. The method for manufacturing an ultra-thin semiconductor stack structure according to Claim 1, wherein, before performing the second back grinding process, a plurality of thinned third semiconductor wafers can be sequentially performed on the thinned second semiconductor wafer The stacking of wafers, wherein the stacking step of each thinned third semiconductor wafer includes: flipping the third semiconductor wafer relative to the first semiconductor wafer, making the interconnection of the third semiconductor wafer layer and the first portion of the substrate of the thinned second semiconductor wafer are opposed and bonded together; a third backside grinding process is performed to remove the third semiconductor wafer from the backside of the third semiconductor wafer. rounding a portion of the second portion of the substrate; and performing a third thinning process including the substrate removal step and the stop layer removal step. The method for manufacturing an ultra-thin semiconductor stack structure as claimed in claim 1, wherein the stop layer structure further includes a silicon dioxide layer, and the silicon dioxide layer is disposed on the silicon nitride layer to interpose the silicon nitride layer. between the silicon layer and the active surface. The method for manufacturing an ultra-thin semiconductor stack structure according to Claim 3, wherein the step of forming the silicon dioxide layer includes: after the nitrogen ion implantation process, firstly forming a layer on a first layer of the semiconductor substrate An oxygen ion implantation process is performed at two depths, and the second depth is smaller than the first depth, and then the high temperature treatment process is performed, so that the oxygen ion implanted area forms the silicon dioxide layer. The method for manufacturing an ultra-thin semiconductor stack structure according to Claim 4, wherein the step of removing the stopper layer includes: removing the silicon nitride layer first, and then removing the silicon dioxide layer. The method for manufacturing an ultra-thin semiconductor stack structure as described in claim 5, wherein the substrate removal step is selected from one of chemical mechanical polishing, wet etching, and plasma dry etching, wherein the selectivity of silicon and silicon nitride is higher than that of Between 20 and 80. The manufacturing method of the semiconductor ultra-thin stack structure as described in Claim 5, wherein the removal method of the silicon nitride layer and the silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching, wherein the silicon nitride layer The selectivity ratio of silicon dioxide to silicon dioxide is between 10 and 20, and the selectivity ratio of silicon dioxide to silicon is about 5. The method for manufacturing an ultra-thin semiconductor stack structure as claimed in Claim 1, wherein the distance between the stop layer structure and the active surface is between 1 micron and 5 microns, and the thickness of the thinned second semiconductor wafer is not more than 12 microns. The method for manufacturing an ultra-thin semiconductor stack structure according to Claim 1, wherein, after forming the thinned first semiconductor wafer, the following step is further included: A plurality of solder balls are arranged on one side of the two semiconductor wafers to electrically connect the conductive structures respectively; and electrical testing and singulation are performed. A method of manufacturing a semiconductor ultra-thin stack structure, comprising: manufacturing a plurality of semiconductor wafers, the manufacturing steps of each of the semiconductor wafers include: providing a semiconductor substrate with an active surface and a back surface opposite; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first part of the substrate and a second part of the substrate, wherein the first part of the substrate is located between the stop layer structure and the active surface, and the second part of the substrate Located between the stop layer structure and the back surface, the stop layer structure includes at least a silicon nitride layer, and the manufacture of the silicon nitride layer includes performing a nitrogen ion implantation process prior to a first depth of the semiconductor substrate, and then performing a high-temperature treatment process to form the silicon nitride layer in the region implanted with nitrogen ions; The first part of the substrate is provided with a plurality of conductive structures connected to the interconnection layer and the stop layer structure; one of the semiconductor wafers is selected as the first semiconductor wafer of the bottom layer, and part of the semiconductor wafers are singulated As a first batch of semiconductor chips and at least one second batch of semiconductor chips to be stacked; and the interconnection layer of the first semiconductor wafer are opposite and bonded together by a hybrid bonding technique; a first molding process is performed to form a first encapsulant covering the first semiconductor wafer on the first semiconductor wafer The first batch of semiconductor wafers; performing a first back grinding process, removing part of the first encapsulant from the side of the first encapsulant away from the first semiconductor wafer and removing the substrate of the first batch of semiconductor wafers A part of the second part; performing a first thinning process to form a first semiconductor wafer layer; performing a second backside grinding process from the backside of the first semiconductor wafer to remove a portion of the second portion of the substrate of the first semiconductor wafer; and performing a second thinning process to form A thinning of the first semiconductor wafer, wherein the first thinning process and the second thinning process include: a substrate removal step, removing the remaining second portion of the substrate to reveal the stop layer structure; and a The stop layer removing step is to remove the stop layer structure to reveal the first part of the substrate and the conductive structures. The method for manufacturing an ultra-thin semiconductor stack structure according to claim 10, wherein, before performing the second back grinding process, at least one second semiconductor wafer layer can be sequentially stacked on the first semiconductor wafer layer , wherein the stacking step of each of the second semiconductor wafer layers includes: flipping the at least one second batch of semiconductor wafers relative to the first semiconductor wafer, so that the interconnection layer of the at least one second batch of semiconductor wafers and the first part of the substrate of the first semiconductor chip layer are opposite and bonded together; performing a second molding process to form a second encapsulant on the first semiconductor chip layer to cover the second batch of semiconductor chips; performing a third back grinding process, removing a portion of the second encapsulant from a side of the second encapsulant away from the layer of the first semiconductor wafer and removing a portion of the second portion of the substrate of the second batch of semiconductor wafers; and A third thinning process is performed, including the substrate removal step and the stop layer removal step. The method for manufacturing an ultra-thin semiconductor stack structure according to Claim 10, further comprising the following steps after forming the thinned first semiconductor wafer: A plurality of solder balls are arranged on the side of the thinned first semiconductor wafer far away from the first semiconductor wafer layer, so as to respectively electrically connect the conductive structures; and conduct electrical testing and singulation. A method for manufacturing a semiconductor ultra-thin stack structure, comprising: providing a carrier plate, and forming a plurality of first conductive columns on the carrier plate; providing a plurality of semiconductor wafers, and the manufacturing steps of each semiconductor wafer include: providing a semiconductor The substrate has an opposite active surface and a back surface; a stop layer structure is formed in the semiconductor substrate, and the semiconductor substrate is divided into a first part of the substrate and a second part of the substrate, wherein the first part of the substrate is located in the stop layer structure and the active surface, the second part of the substrate is located between the stop layer structure and the back surface, the stop layer structure includes at least a silicon nitride layer, and the manufacture of the silicon nitride layer includes a A nitrogen ion implantation process is performed at the first depth, and then a high temperature treatment process is performed to form the silicon nitride layer in the area implanted with nitrogen ions; a plurality of electrical components and an interconnection layer are arranged on the active surface, and the inner layer is formed. The connection layer includes a plurality of interconnection points, and a plurality of conductive structures are arranged on the first part of the substrate to connect the interconnection layer and the stop layer structure; and singulation is performed; a first batch of semiconductor chips is selected from the semiconductor chips and At least one second batch of semiconductor chips, the first batch of semiconductor chips includes a plurality of first semiconductor chips, the at least one second batch of semiconductor chips includes a plurality of second semiconductor chips; on the board, and the first conductive pillars are interposed between the adjacent first semiconductor chips, wherein the interconnection layer of the first batch of semiconductor chips is adjacent to the carrier board and the semiconductor substrate is away from the carrier board; Carrying out a first molding process to form a first encapsulant on the carrier board to cover the first batch of semiconductor chips and the first conductive pillars; performing a first back grinding process to form a first encapsulant removing a part of the first encapsulant and a part of the second portion of the substrate of the first batch of semiconductor chips away from the side of the carrier plate; performing a first thinning process to form a first semiconductor chip layer, the first semiconductor chip A thinning process includes sequentially removing the remaining second portion of the substrate and the stop layer structure of the first batch of semiconductor wafers to expose the first portion of the substrate, the conductive structures, and the first conductive pillars; a second conductive column to electrically connect some of the conductive structures of the first semiconductor chip layer; the second batch of semiconductor chips are flip-chip disposed on the first semiconductor chip layer, wherein the second semiconductor chips span respectively across the first semiconductor chip layer connected between the adjacent first semiconductor wafers, so that the interconnection layers of the second semiconductor wafers are electrically connected to the exposed first conductive pillars and parts of the first semiconductor wafer layers. structure, and some of the second conductive pillars are interposed between the adjacent second semiconductor chips; a second molding process is performed to form a second encapsulant on the first semiconductor chip layer to cover the The second batch of semiconductor wafers and the second conductive pillars; perform a second back grinding process to remove part of the second encapsulant from the side of the second encapsulant away from the first semiconductor chip layer and remove the second encapsulant A portion of the second portion of the substrate of a batch of semiconductor wafers; subjected to a second thinning process to form a second semiconductor wafer layer, the second thinning process comprising sequentially removing the remaining portions of the substrate of the second batch of semiconductor wafers the second part and the stop layer structure to expose the first part of the substrate, the conductive structures and the second conductive pillars; and remove the carrier board to expose the interconnection layer and the first semiconductor wafer layer some first conductive pillars. The manufacturing method of the semiconductor ultra-thin stack structure as described in claim 13, after removing the carrier plate, further includes the following steps: setting a plurality of Solder balls are used to electrically connect the interconnection layer and the first conductive column respectively; and perform singulation. The method for manufacturing an ultra-thin semiconductor stack structure as claimed in claim 13, wherein the first semiconductor wafers of the first batch of semiconductor wafers have different electrical functions. The method for manufacturing an ultra-thin semiconductor stack structure as claimed in claim 13, wherein the second semiconductor wafers of the second batch of semiconductor wafers have different electrical functions.

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