TWI777717B - Hydrogenation and nitridization processes for modifying effective oxide thickness of a film - Google Patents

Abstract

Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process, or a single-step plasma hydrogenation and nitridization process, is performed on a metal nitride layer in a film stack, thereby, according to some embodiments, removing oxygen atoms disposed within layers of the film stack and, in some embodiments, adding nitrogen atoms to the layers of the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift.

Description

Hydrogenation and Nitriding Processes for Improving Effective Oxide Thickness of Films

Embodiments described herein relate generally to a method and apparatus for processing semiconductor substrates, and more particularly, to hydrogenation and nitridation processes that improve the effective oxide thickness of films.

In integrated circuits, smaller transistors such as metal oxide semiconductor field effect transistors (MOSFETs) are highly desirable. First, smaller transistors enable the formation of more transistors in a given wafer area, thereby reducing wafer size. Second, smaller transistors can generally switch faster than larger transistors, thereby improving chip performance.

One method for reducing the size of MOSFETs is scaling, where important component dimensions such as transistor length, transistor width, and oxide (or dielectric) thickness are scaled down. In this method, the transistor channel resistance does not change as the size of the transistor decreases, while the gate capacitance and RC delay of the transistor decrease in proportion to the size reduction.

However, while dielectric thickness reduction in MOSFETs is critical to scaling MOSFETs to the size required for future technology nodes, there are important tradeoffs. Specifically, as the thickness of conventional oxide/oxynitride dielectric layers in MOSFETs decreases linearly, there is an exponential increase in gate leakage, resulting in increased power consumption. In addition, the thickness of the dielectric layer is now approaching a few atomic layers, creating reliability problems. Therefore, any way in which the oxide thickness or effective oxide thickness (EOT) in the transistor can be reduced without an exponential increase in gate leakage is highly desirable. This need and others are addressed in this disclosure.

Embodiments described herein relate generally to sequential hydrogenation and nitridation processes for reducing interfacial and host O atoms in conductive structures in semiconductor devices. In one embodiment, a method of forming a structure in a semiconductor element is provided, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate; depositing a capping layer on the high-k dielectric layer to form the structure In part, the deposited cap layer has an exposed surface; and the exposed surface is exposed to plasma excited hydrogen species and plasma excited nitrogen species. A portion of the substrate includes a capping layer and a high-k dielectric.

In one embodiment, a method of forming a structure in a semiconductor device includes: depositing a high-k dielectric layer on a semiconductor substrate; depositing a metal nitride layer on the high-k metal dielectric layer to form a portion of the structure , wherein the portion includes a metal nitride layer and a high-k metal dielectric layer and has a first effective oxide thickness, and wherein the deposited metal nitride layer has an exposed surface; the exposed surface is continuously exposed to non- The oxidized plasma excited hydrogen species is then exposed to plasma excited nitrogen species to reduce the first effective oxide thickness to the second effective oxide thickness.

In another embodiment, a method of forming a structure in a semiconductor device includes: depositing a high-k dielectric layer on a semiconductor substrate; depositing a metal nitride layer on the high-k metal dielectric layer; The surface was continuously exposed to plasmonic excited hydrogen species, followed by plasmonic excited nitrogen species; after the exposed surface was continuously exposed to plasmonic excited hydrogen species, followed by plasmonic excited nitrogen species, the The exposed surface is exposed to air; and after exposing the exposed surface to air, a thermal annealing process is performed on the high-k dielectric layer and the metal nitride layer at a specified temperature for a specified time.

In another embodiment, a method of forming a structure in a semiconductor device includes: depositing a high-k dielectric layer on a semiconductor substrate; depositing a metal nitride layer on the high-k metal dielectric layer to form a a portion, wherein the portion includes a metal nitride layer and a high-k metal dielectric layer and has a first effective oxide thickness, and wherein the deposited metal nitride layer has an exposed surface; by connecting the exposed surface continuously Exposure to non-oxidizing plasma-excited hydrogen species, followed by exposure to plasma-excited nitrogen species, reduces the first effective oxide thickness to a second effective oxide thickness.

In another embodiment, a method of forming a structure in a semiconductor element is provided, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate; depositing a capping layer on the high-k metal dielectric layer; exposing the exposed surface of the capping layer to plasmonic excited hydrogen species and plasma excited nitrogen species; exposing the exposed surface to air; and performing heat on the high-k dielectric layer and capping layer at a specified temperature The annealing process is for a specific time.

In another embodiment, a method of forming a structure in a semiconductor element is provided, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate; depositing a capping layer on the high-k dielectric layer to form a portion of a structure wherein the deposited cap layer has an exposed surface; and the exposed surface is exposed to a plasma excited hydrogen species and a plasma excited nitrogen species, wherein the plasma excited hydrogen species includes ammonia and the plasma excited The nitrogen species include nitrogen (N ₂ ). Portions of the structure include capping layers and high-k dielectrics.

In another embodiment, a method of forming a structure in a semiconductor device is provided, comprising: depositing a metal nitride capping layer on a high-k dielectric layer formed over a surface of a substrate; and depositing the deposited metal nitride The exposed surface of the capping layer is exposed to a plasma including a first gas including a hydrogen-containing species and a second gas including a nitrogen-containing species, wherein the hydrogen-containing species in the first gas includes nitrogen.

In another embodiment, a method of forming a structure in a semiconductor element is provided, comprising: depositing a high-k dielectric layer on a semiconductor substrate; depositing a capping layer on the high-k dielectric layer; depositing the capping layer exposure of the exposed surface to plasma-excited hydrogen species and plasma-excited nitrogen species; exposing the exposed surface to air; and performing a thermal annealing process at a specified temperature on the high-k dielectric layer and capping layer for specific time.

In another embodiment, a method of forming a structure in a semiconductor element is provided, comprising: depositing a high-k dielectric layer on a semiconductor substrate; depositing a capping layer on the high-k dielectric layer to form a structure a portion, wherein the portion includes a capping layer and a high-k dielectric layer, and wherein the deposited capping layer has an exposed surface; and exposing the exposed surface to plasma-excited hydrogen species and plasma-excited nitrogen species, Wherein the plasma excited hydrogen species includes ammonia, and the plasma excited nitrogen species includes nitrogen gas (N ₂ ).

Embodiments described herein generally relate to methods and apparatus for nitriding layers in structures within semiconductor elements formed on substrates. The single-step plasma hydrogenation and nitridation process can be performed on metal layers or stacks of metal layers included in conductive structures, such as metal layers that are thermally annealed prior to deposition of a metal capping layer. In various embodiments, a single-step plasma hydrogenation and nitridation process may be performed before the thermal annealing process, after the thermal annealing process, or both before and after the thermal annealing process. In various embodiments, the concentration of nitrogen atoms in the conductive structure is advantageously increased, thereby reducing the resistance in the conductive structure. One such conductive structure is shown in Figure 1 . Conductive structures with reduced interfacial and host oxygen

FIG. 1 shows a cross-sectional view of a conductive structure 100 or a contact structure formed as part of a semiconductor element on a semiconductor substrate 110 according to an embodiment of the present disclosure. The conductive structure 100 may be any portion of a semiconductor element that is configured to conduct electrical current and thereby benefit from reduced electrical resistance. In the embodiment shown in Figure 1, the conductive structure 100 is shown as a contact structure for providing electrical contact to the source or drain structure 101, and is shown after the conductive structure 100 has been formed, and such as chemical The planarization process of chemical-mechanical polishing (CMP) has been completed on the semiconductor substrate 110 . For example, the conductive structure 100 may be a contact structure for a field-effect transistor (FET).

Conductive structures 100 are provided in contact wells 109 or holes, which are cavities formed in insulating material 120 . The insulating material 120 (or referred to as shallow trench isolation (STI)) may include one or more dielectric materials, such as silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or multiple layers of each of the above. The insulating material 120 can be formed by high-density plasma (HDP), flowable chemical vapor deposition (FCVD), tetraethyl orthosilicate (TEOS), or the like form. The conductive structure 100 may include a stack of multiple metal layers, eg, a first metal layer 102 , a metal nitride layer 103 , and at least one conductive portion disposed over the first metal layer 102 and the metal nitride layer 103 . The conductive portion may include capping layer 104 and/or conductive layer 106 .

The source or drain structure 101 may be formed from the semiconductor substrate 110 or from different semiconductor materials deposited on the semiconductor substrate 110 . In the latter case, the different semiconductor materials may include germanium silicon, group III-V compound semiconductor materials, or the like. For example, in some embodiments, an epitaxial process may be performed to grow the source or drain structure 101 .

A first metal layer 102 is formed on the source or drain structure 101 and includes one or more metals selected to be at the interface with the source or drain structure 101 after a suitable thermal annealing process Silicide 105 is formed. For example, in some embodiments, the first metal layer 102 includes titanium (Ti) or consists entirely of Ti, and may have a thickness of about 40 Å to about 50 Å. A metal nitride layer 103 is formed on the first metal layer 102 and includes a metal nitride, eg, for use as a diffusion barrier layer in the conductive structure 100 . In some embodiments, the metal nitride layer 103 includes titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (W ₃ N ₂ ), and may have a thickness of about 10 Å to 20 Å. Cap layer 104 is typically formed on metal nitride layer 103 after a thermal annealing process by which silicide 105 is formed in conductive structure 100 and includes one or more metals. In some embodiments, conductive structure 100 may include a separately formed conductive layer 106, which may include a metal such as cobalt, copper, ruthenium, nickel, tungsten, aluminum, or other useful metals, or combinations thereof. In some embodiments, the capping layer 104 includes Co and can have a thickness of about 10 Å to 20 Å. In other embodiments, capping layer 104 includes a metal (eg, cobalt) that completely fills the remainder of contact well 109 .

As previously mentioned, the presence of O atoms in the first metal layer 102 and/or the metal nitride layer 103 adversely affects the effective conductivity of the conductive structure 100 . First, oxides in any metal layer increase the bulk conductivity of the formed metal layer. Second, the interfacial oxide (ie, the metal oxide formed at the interface between the metal nitride layer 103 and the capping layer 104) exacerbates poor adhesion between the metal nitride layer 103 and the capping layer 104, potentially The ground results in voids that significantly reduce the effective cross-sectional area of the conductive structure 100 . Unfortunately, there is almost always some low concentration of O atoms in the bulk portion of the metal layer of the conductive structure 100 . Furthermore, in many cases, oxides may form at relatively high concentrations on metal surfaces that are exposed to air between fabrication steps. According to embodiments of the present disclosure, the presence of bulk and interfacial O atoms in conductive structure 100 can be reduced through sequential hydrogenation and plasma nitridation processes. Figures 2A to 2E and 3A to 3D illustrate physical models of the extent to which the bulk and interface O atoms in the conductive structure 100 are reduced for a continuous process. Solid model for reducing interface and bulk oxygen

FIGS. 2A-2E are schematic diagrams of the metal nitride layer 103 within the contact structure 100 at various stages of fabricating the contact structure 100 according to an embodiment of the present disclosure. It should be noted that Figures 2A to 2E show only one possible surface end of the metal nitride layer 103 and only represent the common TiN structure. In some embodiments, the metal nitride layer 103 may have any other possible surface termination or crystal structure associated with the TiN layer.

In Figure 2A, the portion 200 of the metal nitride layer 103 is schematically shown immediately after the metal nitride layer 103 has been deposited on the first metal layer 102 and before the portion 200 is exposed to air. Portion 200 includes a surface 201 of portion 200 on which capping layer 104 will ultimately be deposited. As shown, the portion 200 has a NACl cubic structure and is mainly composed of Ti and N atoms. In addition, portion 200 includes a low concentration of bulk O atoms 211 (cross-hatched) disposed generally in the bulk region of portion 200 below surface 201 . The bulk O atoms 211 may be brought in by contamination found in the processing environment during the deposition process used to form the portion 200 . Additionally, portion 200 typically includes vacancies 213, which are sites within the crystal lattice of portion 200 where atoms are being lost. Vacancies 213 are locations where additional oxidation can occur within portion 200 when nitride layer 103 is exposed to air. It is noted that when the metal nitride layer 103 is formed by an atomic layer deposition (ALD) process, due to the film nucleation and growth mechanisms found in the ALD process, compared to conventional chemical vapor deposition (chemical vapor deposition) Vapor deposition; CVD) or physical vapor deposition (physical vapor deposition; PVD) process, the vacancies 213 are relatively common. Accordingly, one or more embodiments of the disclosure provided herein may provide significant benefits when used on films formed by ALD processes relative to conventional PVD or CVD type processes.

In Figure 2B, portion 200 is shown after removal from the processing system in which metal nitride layer 103 is deposited. For example, in preparation for the thermal annealing process, the semiconductor substrate 110 on which the portion 200 is formed may be exposed to air. Typically, conventional thermal processing chambers (eg, annealing process chambers) are not as common as those used to form the first thermal processing chamber due to differences in the required cleanliness, thermal management control, and vacuum level requirements required to form most of today's advanced device node applications. A metal layer 102 and a metal nitride layer 103 are processed in different processing systems. Thus, in Figure 2B, portion 200 is shown after exposure to air. As shown, surface 201 has been partially oxidized, with surface O atoms 212 occupying most or all of the vacancies 213 provided on surface 201 . In some cases, some of the vacancies 213 provided within the portion 200 are occupied by host O atoms 211 as a result of exposing the portion 200 to air.

In Figure 2C, portion 200 is shown after undergoing a thermal anneal process to form silicide 105 (shown in Figure 1). Some or all of the remaining vacancies 213 are filled with bulk O atoms 211 or surface O atoms 212 . In some embodiments, host O atoms 211 may also displace a portion of the N atoms disposed within portion 200 . Therefore, the annealing process typically increases the number of both bulk O atoms 211 and surface O atoms 212 in portion 200 . Even when the depth of the surface O atoms 212 on the surface 201 is only one or two monolayers, the effect on the resistivity of the conductive structure 100 can be significant, especially for smaller device structures, such as with advanced device nodes ( For example, the 65 nm technology node and below) associated structures.

In Figure 2D, portion 200 is shown after exposure to hydrogen atoms with bulk O atoms 211 and/or surface O atoms 212 included in portion 200 in accordance with various embodiments of the present disclosure reaction. In some embodiments, bulk O atoms 211 and/or surface O atoms 212 react with hydrogen atoms from thermally dissociated hydrogen gas (H ₂ ) as part of the thermal hydrogenation process, and in other embodiments, as a plasma hydrogenation process As part of the process, bulk O atoms 211 and/or surface O atoms 212 react with hydrogen atoms from the hydrogen-containing plasma.

The thermal hydrogenation process may be performed in a suitable rapid thermal processing chamber under certain processing conditions, including heating portion 200 to at least about 550°C to about 650°C. The plasma hydrogenation process can be performed in a suitable plasma processing chamber under certain processing conditions. Exemplary plasma processing chambers and plasma processing conditions are each described below for a plasma hydrogenation process. As shown, the hydrogenation process reduces or otherwise removes all or substantially all surface O atoms 212 from surface 201 , leaving vacancies 213 . In addition, the plasma hydrogenation process may also remove some or all of the host O atoms 211 disposed below the surface 201 .

In Figure 2E, portion 200 is shown after undergoing a plasma nitridation process in accordance with various embodiments of the present disclosure. The plasma nitridation process can be performed in a suitable plasma processing chamber under certain processing conditions, and exemplary plasma processing chambers and plasma processing conditions are each described below for the plasma nitridation process. In some embodiments, the plasma nitridation process may be performed in the same plasma processing chamber that performs the plasma hydrogenation process. In addition, no air gap occurs between the plasma or thermal hydrogenation process and the plasma nitridation process. That is, the portion 200 is not exposed to air after the plasma or thermal hydrogenation process and before the plasma nitridation process.

As shown, the nitridation process results in filling of vacancies 213 with N atoms such that there are very few or no surface O atoms 212 disposed on surface 201 . Consequently, the surface 201 can reach saturation of N atoms, and thus, subsequent oxidation of the surface 201 is greatly reduced or eliminated, even when the surface 201 is again exposed to air before the capping layer 104 is deposited. Thus, the adhesion between the surface 201 of the metal nitride layer 103 and the capping layer 104 is improved. Additionally, some or all of the vacancies below surface 201 may be filled with N atoms in place of host O atoms 211 , thereby further improving the conductivity of metal nitride layer 103 , first metal layer 102 , and conductive structure 100 as a whole.

Figure 3 is an X-ray Photoelectron Spectroscopy (XPS) spectrum 310 for a TiN film deposited and thermally annealed prior to processing and for the same after processing, according to an embodiment of the present disclosure XPS spectrum 320 of a deposited and thermally annealed TiN film. The treatment includes a plasma or thermal hydrogenation process followed by a plasma nitridation process. The thermal annealing process is a rapid thermal process in a nitrogen ( _N2 ) or ammonia ( _NH3 ) environment at a temperature between about 550°C and 600°C. At a temperature between about 340°C and 500°C, at a process pressure between about 10 mTorr and 150 mTorr, at a plasma power between about 250 W and 2000 W, at between about 5 sccm and 100 sccm The plasma hydrogenation process was performed in an inductively coupled plasma (ICP) chamber on the substrate pedestal at a H flow rate of between about ₂₅₀ sccm and 2000 sccm and an argon (Ar) flow rate between about 250 sccm and 2000 sccm. Execute for a duration between about 30 seconds and about 200 seconds. On a substrate pedestal at a temperature between about 350°C and 500°C, at a process pressure between about 10 mTorr and 100 mTorr, at a plasma power between about 250 W and 2000 W, at about 5 sccm At NH ₃ flow rates between about 300 sccm and 500 sccm, nitrogen (N ₂ ) flow rates between about 300 sccm and 500 sccm, and argon (Ar) flow rates between about 20 sccm and 500 sccm, The plasma nitridation process can be performed in the same ICP chamber for durations between about 30 seconds and about 200 seconds.

As is well known in the art, the XPS spectra of TiN films can include multiple peaks, each indicating different relative concentrations of different titanium-containing materials. For example, a Ti-O peak with a binding energy of about 458.5 eV generally indicates the presence of Ti-O bonds, and thus, O atoms in the titanium-containing material; a Ti-O-N peak with a binding energy of about 457 eV generally indicates Ti-O-N bonds are present, and thus, indicate the presence of N atoms and O atoms in the titanium-containing material; and a Ti-N peak with a binding energy of about 454.9 eV generally indicates the presence of Ti-N bonds, and thus, indicates the presence of Ti-N bonds in the titanium-containing material. Nitrogen (N) atoms are present in the titanium-containing material.

XPS spectrum 310 is associated with the Ti 2p shell for the TiN deposited film after the thermal annealing process described above was performed thereon, and for the TiN deposited film after undergoing the above-described plasma hydrogenation process followed by the above-described plasma nitrogen TiN deposition and thermally annealed film after the chemical process, the XPS spectrum 320 correlates with the Ti 2p shell. As shown, the peaks indicating the presence of Ti-O bonds and the peaks indicating the presence of Ti-O-N bonds are significantly lower in the XPS spectrum 320 compared to the XPS spectrum 310, clearly indicating the presence of Ti-O bonds in the TiN film. O atoms decrease. Furthermore, the peak indicating the presence of Ti-N bonds is significantly higher in the XPS spectrum 320 than in the XPS spectrum 310, clearly indicating an increase in the concentration of N atoms in the TiN film. Therefore, by performing the hydrogenation and nitridation processes after the annealing process, the concentration of O atoms in the metal nitride film 103 can be significantly reduced, and the concentration of N atoms in the metal nitride film 103 can be significantly increased.

Figures 2A to 2E and Figure 3 show the effect of the continuous hydrogenation and nitridation process on the metal nitride layer 103 after annealing. In some embodiments, employing a plasma or thermal hydrogenation process on portion 200 prior to the thermal annealing process, followed by a plasma nitridation process may have similar beneficial effects. Specifically, since surface 201 may be mostly or fully saturated with N atoms due to the plasma nitridation process (shown in Figure 2E), subsequent air exposure and thermal annealing of surface 201 results in little or no oxidation. Consequently, the concentration of bulk O atoms 211 found in portion 200 and the concentration of surface O atoms 212 on surface 201 do not increase significantly. System overview for continuous hydrogenation and nitridation

4 is a schematic cross-section of a plasma processing chamber 400 configured to implement one or more aspects of the present disclosure. Plasma processing chamber 400 may be any suitable plasma processing chamber, such as an inductively coupled plasma (ICP) processing chamber. As shown in FIG. 4 , the processing chamber 400 may include a chamber wall 406 , a chamber cover 408 , and a substrate support base 404 disposed within the chamber wall 406 . Typically, chamber wall 406 is coupled to electrical ground 416 . The chamber cover 408 may be constructed of any suitable dielectric, such as quartz. For some embodiments, the dielectric cover 408 may assume a different shape (eg, a dome shape). In some embodiments, the chamber cover 408 may be coated with a ceramic coating (eg, yttrium-containing oxide) for protection against plasma species. In one embodiment, the ceramic coating is a high performance material (HPM), the high performance material is composed of Y ₄ Al ₂ O ₉ compound and solid solution Y _2-x Zr _x O ₃ (Y ₂ O ₃ - ZrO ₂ solid solution). The ceramic coating can have a thickness ranging from about 100 microns to about 300 microns, such as about 200 microns.

Above the chamber cover 408, a radio frequency (RF) antenna including at least one inductive coil element 410 may be positioned (two coaxial coil elements are shown). In some embodiments, the induction coil element 410 may be disposed around at least a portion of the chamber wall 406 . One end of the induction coil element 410 may be coupled to an RF power source 414 via a first impedance matching network 412, and the other end may be connected to an electrical ground 417 as shown. Power supply 414 is typically capable of producing up to 10 kilowatts (kW) of power at tunable frequencies ranging from 2 to 160 MHz, with 13.56 MHz being a common operating frequency. The RF power supplied to the induction coil element 410 may be pulsed (ie, switching between on and off states) or power cycling (ie, changing the power input from a high level to a low level) with a frequency ranging from 1 to 100 kHz variation range.

A shield electrode 418 may be inserted between the induction coil element 410 of the RF antenna and the chamber wall 408 . The shield electrode 418 may alternatively be electrically floating or coupled to electrical ground 419 via any suitable means for making and breaking electrical connections, such as switch 420 shown in FIG. 4 .

For some embodiments, a detector 422 may be attached to the chamber wall 406 to facilitate determining when to excite the gas mixture within the chamber 400 into plasma. For example, detector 422 may detect radiation emitted by the excited gas or use optical emission spectroscopy (OES) to measure one or more wavelengths of light associated with the generated plasma. strength.

The base 404 may be coupled to a bias power supply 426 via a second impedance matching network 424 . Similar to RF power supply 414, bias power supply 426 is typically capable of generating RF signals with tunable frequencies ranging from 2 to 160 MHz and powers between 0 and 10 kW. Alternatively, bias power supply 426 may be a direct current (DC) or pulsed DC source.

In operation, a substrate 428 , such as a semiconductor substrate, may be placed on the pedestal 404 and process gases may be supplied from the gas panel 430 via the inlet port 432 in an effort to form the gas mixture 434 . Common process gases that can be used in one or more of the processes described herein are described below. The inlet port 432 may be coated with a ceramic coating such as HPM. Gas mixture 434 can be excited into plasma 436 in process chamber 400 by applying power from RF power source 414 . The pressure within the interior volume of processing chamber 400 may be controlled using throttle valve 438 and vacuum pump 440 . In some embodiments, the temperature of the chamber wall 406 may be determined using liquid-containing tubing (not shown) running through the chamber wall 406 or embedded in the chamber wall 406 (eg, a heating cartridge or coil) or wrapped around the processing chamber Heating element controls around the chamber 400 (eg, heater packs or strips).

The temperature of the substrate 428 can be controlled by stabilizing the temperature of the base 404 . In some embodiments, helium (He) gas from gas source 442 may be provided via gas conduit 444 to a channel (not shown) formed in the base surface below substrate 428 . Helium can facilitate heat transfer between the base 404 and the substrate 428 . During processing, the pedestal 404 can be heated to a steady state temperature, and then the helium gas can promote uniform heating of the substrate 428 . The base may be so heated by a heating element (not shown), such as a resistive heater embedded within base 404, or a lamp typically aimed at base 404 or substrate 428 thereon. Using such thermal control, the substrate 428 can be maintained at a temperature between about 20 degrees Celsius and 350 degrees Celsius (°C).

To allow control of the components of processing chamber 400 as described herein, a controller 446 may be provided. The controller 446 may include a central processing unit (CPU) 448 , memory 450 , and support circuits 452 for the CPU 448 . Controller 446 may interface with RF power supply 414 , switch 420 , detector 422 , and bias power supply 426 .

Controller 446 may be any suitable type of general-purpose computer processor that can be used in an industrial setting for controlling the various chambers and sub-processors. Memory 450, or other computer-readable media for CPU 448, may be one or more of any readily available form of memory, such as random access memory (RAM), read only memory (read only memory; ROM), floppy disk, hard disk, or any other form of digital storage (local or remote). Support circuitry 452 may be coupled to CPU 448 in an effort to support the processor in a conventional manner. Such circuits may include cache memory, power supplies, clock circuits, input/output (I/O) circuitry and subsystems, and the like. For some embodiments, the techniques disclosed herein for energizing and maintaining plasma may be stored in memory 450 as software routines. Software routines may also be stored and/or executed by a second CPU (not shown) remotely located in hardware controlled by CPU 448 .

According to some embodiments of the present disclosure, the thermal or plasma hydrogenation process is followed by a plasma nitridation process, hereinafter referred to as a "continuous hydrogenation/nitridation process," on the substrate before and/or after thermal annealing is performed on the substrate implement. The continuous hydrogenation/nitridation process may include a capacitively coupled plasma process or an inductively coupled plasma process. In some embodiments, the plasma for the hydrogenation/nitridation process can be formed in a remote plasma source external to the processing chamber 400, and in other embodiments, the plasma for the plasma process can be formed in situ formed, that is, formed in the processing chamber 400 . Hydrogenation and nitridation may be performed in the same step, hereinafter referred to as "single-step plasma hydrogenation and nitridation process". In some embodiments, the plasma used for the single-step plasma hydrogenation and nitridation process can be formed in a remote plasma source outside the processing chamber 400, and in other embodiments, the plasma used for the plasma process The slurry may be formed in situ, that is, in the processing chamber 400 .

In the plasma hydrogenation process, plasma excited H radicals and/or ions react with host O atoms 211 and/or surface O atoms 212 to generate vacancies 213 . In the case of the thermal hydrogenation process, the dissociated H atoms react with host O atoms 211 and/or surface O atoms 212 to generate vacancies 213 . During the nitridation process, N radicals and/or ions occupy the vacancies 213 .

Note that during the plasma hydrogenation process, the processing environment within processing chamber 400 typically includes relatively low lower concentrations due to the presence of H atoms, such as dissociated H atoms, H radicals, and/or H ions the O atom. Thus, the processing environment within the processing chamber 400 during the plasma hydrogenation process is compared to the processing environment within the processing chamber 400 during the nitridation process or within the processing chamber during deposition of the metal nitride layer Lower concentrations of O atoms may be included. However, for both hydrogenation or nitridation, lower concentrations of O atoms are generally advantageous. Thus, in some embodiments, the processing chamber may be conditioned with a plasma process (eg, _H2 process) to remove any traces of O species prior to the plasma hydrogenation process and/or the nitridation process.

When the metal nitride layer to be treated with the hydrogenation/nitridation process described herein or the single-step plasma hydrogenation and nitridation process is a thin film with a thickness of about 200 Å or less, the ICP process is generally less prone to hydrogenation or nitridation. The metal nitride layer is destroyed during nitridation. Specifically, in ICP processes, the plasmonic sheath is typically smaller than that in a CCP chamber, and thus the ions passing through it typically have proportionally smaller energies, eg, on the order of 10 times eV , such as 10 to 20 eV. In contrast, ions in a CCP chamber typically have energies on the order of 100 times eV (eg, >200-400 eV) and can subsequently cause significant damage to the metal nitride layer. Additionally, due to higher densities of ions, radicals, and other plasma excitations typically formed in ICP processing chambers and close to the substrate relative to remote plasma sources used in CCP and other types of processing chambers Species, the ICP process can provide more oxygen removal from the metal nitride layer than by using CCP or remote plasma processes. In contrast, the concentrations of free radicals from the CCP and remote plasma sources were relatively low.

In embodiments in which the plasma for the plasma process is formed in situ, the plasma may be formed via the induction coil element 410, the first impedance matching network 412, the RF power supply 414, and in some embodiments, via the second An impedance matching network 424 and a bias power supply 426 are formed. In such an embodiment, the plasma process may include introducing into the process chamber 400 one or more process gases selected to generate certain plasma species (ie, ions, neutral atoms, and / or free radicals). More specifically, in the case of plasma hydrogenation processes, one or more process gases are selected to produce plasma excited hydrogen species, while in the case of plasma nitridation processes, one or more process gases are selected to produce plasma excited hydrogen species. Nitrogen species selected to generate plasmonic excitation. Thus, for plasma hydrogenation processes, one or more process gases may include hydrogen ( _H2 ), and/or D2, and for plasma nitridation processes, one or more process gases may include nitrogen ( _{N2 )} ) or ammonia (NH ₃ ). Alternatively or additionally, the plasma process may include introducing one or more carriers and/or inert gases, such as argon (Ar), into the processing chamber 400 . For single-step plasma hydrogenation and nitridation processes, the one or more process gases may include _hydrogen ( _H2 ), D2, nitrogen ( _{N2 )} , ammonia ( _NH3 ), or hydrazine ( _N2H4 ).

In some embodiments, the plasma hydrogenation process consists essentially of forming a plasma including a process gas consisting essentially of hydrogen (H ₂ ) that forms reactive species provided by the plasma. It will be noted that the formation of hydrogen-containing species using a plasma (eg, inductively coupled plasma ₎ formed using _H2 will have significantly more hydrogen radicals and ions, thus improving the effectiveness of the plasma hydrogenation process and reducing undesired reactions found when impure hydrogen-containing reaction gases are used.

In some embodiments, the one or more process gases are energized by an RF power source, such as RF power source 414 . The RF power can be pulsed at 2% to 70% duty cycle and can vary from about 100 W to about 2500 W. The RF power may be a continuous wave varying from about 100 W to about 2500 W. The processing chamber can have a chamber pressure that varies from about 10 mTorr to about 200 mTorr during the plasma process, while the processing temperature (eg, the temperature of the pedestal 404 ) can vary from 20°C to about 500°C.

In an exemplary embodiment, at a process temperature between about 400°C and about 500°C, at a chamber pressure between about 5 mTorr and about 20 mTorr, at an RF between about 1000 W and about 2000 W At power, and at a bias voltage of between about 175 V and about 250 V, with a H flow between about ₂₀ sccm and about 40 sccm and an Ar flow between about 400 sccm and about 500 sccm, electroporation was performed. The slurry hydrogenation process is for a duration of between about 50 seconds and about 300 seconds. Plasma-excited hydrogen species generated by the plasma inside processing chamber 400 may reduce exposed surfaces of metal nitride layers (eg, metal nitride layer 103 ) in partially formed conductive structures (eg, conductive structure 100 ) some or all oxides present on it. In some embodiments, the plasma excited hydrogen species may also reduce some or all O atoms present in the host material of the metal nitride layer of the conductive structure (eg, the first metal layer 102 of the conductive structure 100 ) or other metal layers . This reduction of O atoms is described above in connection with Figures 2D and 3B.

In another exemplary embodiment, at a process temperature between about 400°C and about 500°C, at a chamber pressure between about 5 mTorr and about 25 mTorr, between about 1000 W and about 2000 W At a RF power of about 175 V and about 250 V at a bias pressure of between about 175 V and about ₂₅₀ V, with a flow rate of NH between about ₂₀ sccm and about 40 sccm and a flow of N between about 400 sccm and about 600 sccm , and the Ar flow is between about 400 sccm and about 500 sccm, and the plasma nitridation process is performed for a duration of between about 50 seconds and about 300 seconds. Plasma-excited nitrogen species generated by the plasma inside processing chamber 400 can saturate exposed surfaces of the metal nitride layer (eg, surface 201 of metal nitride layer 103 ) of the partially formed conductive structure. In some embodiments, plasma excited nitrogen species may also fill vacancies present in the host material of the metal nitride layer or other metal layer of the conductive structure. Such nitridation is described above in connection with Figures 2E and 3C.

In some embodiments, the RF power is at about 300 W at a chamber pressure between about 10 mTorr and about 100 mTorr, at a processing temperature (eg, substrate pedestal temperature) between about 350°C and about 500°C and about 2000 W, the flow rate of _NH3 is between about 5 sccm and about 100 sccm, the flow rate of _N2 is between about 50 sccm and about 1000 sccm, and the flow rate of helium (He) is between about 1 and about 1000 sccm. Between 1000 sccm, a single-step plasma hydrogenation and nitridation process was performed for a duration of about 30 seconds and about 150 seconds, and a substrate bias was applied with a frequency from about 2 MHz to about 160 MHz and a bias power at about Between 0 kW and about 10 kW.

In some embodiments, at a chamber pressure between about 15 mTorr and about 25 mTorr, at a process temperature between about 350°C and about 500°C, wherein the RF power is between about 300 W and about 1600 W , a flow rate of NH ₃ between about 10 sccm and about 40 sccm, a flow rate of N ₂ between about 200 sccm and about 550 sccm, and a flow rate of Ar from about 200 sccm to about 550 sccm. The slurry hydrogenation and nitridation process was performed for a duration of between about 85 seconds and about 95 seconds, and no substrate bias power was applied.

In embodiments in which the plasma for the plasma process is formed remotely, the plasma may be formed via any technically feasible remote plasma source. In such an embodiment, the plasma process may include introducing one or more process gases into a remote plasma source, the process gases being selected to produce a plasma-excited hydrogen species or a plasma-excited nitrogen species. Alternatively or additionally, the remote plasma process may include introducing one or more carriers and/or inert gases, such as argon (Ar), into the remote plasma source. The remotely generated plasma species then flow into the processing chamber 400 and process the metal nitride layer of the conductive structure formed on the substrate disposed in the processing chamber 400 . As described above, depending on whether the plasmonic species is a plasmonic excited hydrogen species or a plasma excited nitrogen species, interfacial and host O atoms in the metal nitride layer are reduced or nitridation of the metal nitride layer is enhanced.

In some embodiments, as opposed to a plasma hydrogenation process, a thermal hydrogenation process may be employed to expose the metal nitride layer to hydrogen atoms. In such embodiments, the thermal hydrogenation process typically occurs at elevated temperatures (eg, between about 500°C and about 650°C). At such high temperatures, the H ₂ gas dissociates into individual atoms, which can then react with O atoms in the metal nitride layer 103 and create vacancies 213 . Furthermore, in such embodiments, the thermal hydrogenation process is typically performed in a different processing chamber than processing chamber 400 . For example, in some embodiments, the thermal hydrogenation process is performed in a rapid thermal processing chamber. In such an embodiment, the silicidation process can be performed concurrently with the thermal hydrogenation process, thereby eliminating the subsequent annealing process.

In embodiments in which a thermal annealing process is employed to expose the metal nitride layer to hydrogen atoms, the plasma nitridation process is performed without air breaks that expose the metal nitride layer 103 to air. For example, in such an embodiment, one chamber of a multi-chamber processing system may be configured to perform a thermal hydrogenation process, and another chamber of the same multi-chamber processing system may be configured to perform a plasma nitridation process . Therefore, the substrate on which the metal nitride layer 103 is formed can undergo a thermal hydrogenation process and then directly transfer to a plasma nitridation chamber without exposure to air.

5 is a top plan view of a multi-chamber processing system 500 configured to implement one or more aspects of the present disclosure. The multi-chamber processing system 500 is configured to perform one or more fabrication processes on separate substrates, such as silicon wafers, for forming semiconductor devices. Multi-chamber processing system 500 includes some or all of transfer chamber 506 , buffer chamber 508 , single wafer load gates 510 and 512 , processing chambers 514 , 516 , 518 , 520 , 522 , and 524 , preheat chamber 523 and 525, and robots 526 and 528. Single wafer load gates 510 and 512 may include heating elements 513 and be attached to buffer chamber 508 . Process chambers 514 , 516 , 518 , and 520 are attached to transfer chamber 506 . Process chambers 522 and 524 are attached to buffer chamber 508 . The operation of multi-chamber processing system 500 is controlled by computer system 530 . Computer system 530 may be configured to implement any element or combination of elements of the operations of the invention provided herein. Thus, computer system 530 may be a controller or array of controllers and/or a general-purpose computer configured with software that, when executed, performs the operations of the present invention. An example of a suitable multi-chamber processing system 500 is the Endura® RTM CL system manufactured by Applied Materials, Inc. of Santa Clara, California, USA.

Each of the processing chambers 514, 516, 518, 520, 522, and 524 may be configured to fabricate conductive structures in semiconductor devices (eg, contact structures for field-effect transistors (FETs)) to perform one or more processing steps. More specifically, processing chambers 514, 516, 518, 520, 522, and 524 may include one or more metal deposition chambers, surface cleaning and preparation chambers, thermal annealing and/or thermal hydrogenation chambers, and electrical Slurry hydrogenation/nitridation chamber.

For example, for contact structures including Ti-TiN-Co stacks formed on silicon source or drain structures, in some embodiments, the multi-chamber processing system 500 may be configured to perform the fabrication process of such conductive structures Several processing steps are performed consecutively. In such an embodiment, the processing chamber 514 may be configured to perform surface cleaning and fabrication processes on the exposed surfaces of the silicon source or drain structures, and the processing chamber 516 may be configured to perform a surface cleaning and fabrication process on the fabricated silicon source or drain structures. With successive deposition of Ti and TiN layers on the drain structure, processing chambers 522 and/or 524 may be configured by performing rapid thermal processing (RTP) or Other thermal annealing processes to form silicides, processing chamber 518 can be configured to deposit a Co capping layer on the annealed Ti/TiN layer, and processing chamber 520 can be configured to perform a hydrogenation process before or after the thermal annealing process and subsequent nitridation process. Thus, in such embodiments, complete contact structures may be formed without void breaks and undesired oxidation of the resulting one or more layers of contact structures.

In alternative embodiments, not all processing steps for forming a complete contact structure are performed on a single multi-chamber processing system 500 . For example, in some embodiments, multi-chamber processing system 500 may include metal deposition processing chambers, while thermal annealing silicidation processes may be performed on different substrate processing systems. In such embodiments, void breaks occur prior to the thermal annealing process and are known to increase the presence of O atoms at the interface surface of the metal nitride layer and in the bulk material of the metal nitride layer of the contact structure . However, since the multi-chamber processing system 500 may be configured with both a metal deposition chamber and one or more plasma processing chambers, continuous plasma (or thermal) hydrogenation/plasma nitridation may be performed prior to air break process or single-step plasma hydrogenation and nitridation process. Thus, the multi-chamber processing system 500 can be configured to perform continuous sequential operations on the substrate after depositing the first metal layer 102 and the metal nitride layer 103 but before removing the substrate from the multi-chamber processing system 500 and exposing the substrate to air Hydrogenation/nitridation process or single-step plasma hydrogenation and nitridation process. As discussed above, nitridation of the exposed surface of the metal nitride layer 103 prior to air-break can substantially reduce oxidation of the exposed surface during air-break and during subsequent thermal annealing processes.

In some embodiments, the multi-chamber processing system 500 may include one or more thermal annealing and plasma processing chambers. In such an embodiment, a continuous hydrogenation and nitridation process or a single-step plasma hydrogenation and nitridation process may be performed after the thermal annealing process, thereby removing the voids introduced by the pre-annealing process and by the thermal annealing process itself O atom. Typically, thermal annealing processes cannot maintain the desired low oxygen levels required for most advanced device nodes due to the high temperatures reached during thermal processing of process components (eg, seals, process kit components, pumps, etc.).

Alternatively or additionally, a continuous hydrogenation/nitridation process or a single-step plasma hydrogenation and nitridation process may be performed before the thermal annealing process. Therefore, in such an embodiment, even if void breaks do not occur after the deposition of the metal nitride layer 103 and before the thermal annealing process, the interfacial O atoms and the O atoms present in the bulk portion of the metal nitride layer can be performed Reduced or eliminated before the thermal annealing process. Thus, in some configurations, a continuous hydrogenation and plasma nitridation process or a single-step plasma hydrogenation and nitridation process may be performed before the thermal annealing process and also after the thermal annealing process but before voids occur.

In some embodiments, multi-chamber processing system 500 may include one or more metal deposition chambers and one or more plasma processing chambers configured to deposit capping layer 104 and/or conductive layer 106 to perform Continuous hydrogenation and nitridation process or single-step plasma hydrogenation and nitridation process. In such an embodiment, a continuous hydrogenation and nitridation process or a single-step plasma hydrogenation and nitridation process may be performed prior to depositing a capping layer in the conductive structure, thereby removing the heat from the air gap and the heat used to form the silicide 105 Interface and host O atoms introduced by the annealing process. Note that in such embodiments, no voids occur between the continuous hydrogenation and nitridation process and the deposition of capping layer 104 and/or conductive layer 106 . Thus, in such embodiments, interfacial O atoms and O atoms present in the bulk portion of the metal nitride layer may be reduced or eliminated when void breaks occur between the thermal annealing process and the deposition of capping layer 104 . Reduces bulk and interfacial oxygen in contact structures

Figure 6 illustrates a flow diagram of process steps for reducing bulk and interfacial oxygen in contact structures in accordance with some embodiments of the present disclosure. FIGS. 7A-7E are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of FIG. 6 according to various embodiments of the present disclosure. Although FIGS. 7A-7E show the first metal layer 102 , the metal nitride layer filling the hole 109 as selectively deposited (eg, the layer is not formed conformally over the hole 109 as shown in FIG. 1 ) 103 and capping layer 104, which are not intended to limit the scope of the disclosure described herein, and thus the first metal layer 102, metal nitride layer 103, and capping layer 104 may be selectively formed or non-selectively formed, and include a or more additional layers.

Prior to step 601, a cleaning process or other surface preparation process may be performed on the surface of the semiconductor substrate on which contacts will be formed, such as the exposed surface 701 of the source or drain structure 101 in Figure 7A. In some embodiments, a dry etch process may be performed to remove the original oxide of the substrate 701 . For example, conventional plasma etch, or remote plasma assisted dry etch processes, such as the SiCoNi ^™ etch process available from Applied Materials, Inc., Santa Clara, USA, may be performed. In the SiCoNi ^™ etch process, the surface of the semiconductor substrate on which contacts are to be formed is exposed to _H2 , NF3, and _/ or _NH3 plasma species, eg, plasma excited hydrogen and fluorine species. For example, in some embodiments, such surfaces may undergo simultaneous exposure to _H2 , NF3, and _{NH3 plasmas} . The SiCoNi ^™ etch process can be performed in a SiCoNi ^™ pre-clean chamber, which can be integrated into one of a variety of multiprocessing platforms, including the Producer ^™ GT, Centura ^™ AP, and Endura platforms available from Applied Materials.

As shown in FIG. 7B, method 600 begins at step 601, wherein a first metal layer 102 and a metal nitride layer 103 are deposited on a semiconductor substrate. For example, in some embodiments, a Ti layer is deposited, followed by a TiN barrier layer. Any suitable PVD, CVD, or ALD process may be employed to perform such deposition. Thus, the deposition process can be a selective process or a non-selective deposition process. In the selective deposition process, the first metal layer 102 and the metal nitride layer 103 are deposited on the surface 701, but not on other surfaces of the semiconductor substrate 110, while in the non-selective process, the first metal layer 102 and the metal The nitride layer 103 may be deposited on all unmasked surfaces of the semiconductor substrate 110 . In some embodiments, the deposition of step 601 is performed without voids after the surface preparation process described above. That is, the semiconductor substrate is not exposed to the atmosphere between the surface preparation process and the deposition of step 601 . In such an embodiment, the deposition and surface preparation processes of step 601 may each be performed by different chambers on the same multi-chamber processing system (eg, multi-chamber processing system 500).

In step 603 , a thermal annealing process is performed on the semiconductor substrate 110 , and the semiconductor substrate includes the first metal layer 102 , the metal nitride layer 103 , and the source or drain structure 101 . As shown in Figure 7C, the thermal annealing process forms silicide 105. For example, in some embodiments, a tip annealing process to reach a peak temperature between about 500°C and about 600°C may be performed in step 603 . Alternatively, any other suitable annealing process may alternatively be performed to form silicide 105 between source or drain structure 101 and first metal layer 102 deposited in step 601 .

In some embodiments, the chamber used to perform step 603 may be configured as the chamber of the same multi-chamber processing system where the metal deposition of step 601 is performed. Therefore, in such an embodiment, after the metal deposition in step 601 , the thermal annealing process in step 603 is performed without void breaks, thereby further reducing the presence of interface O on the surface 702 of the metal nitride layer 103 . However, for the reasons discussed above, such configurations of multi-chamber processing systems are uncommon, and a gap between steps 601 and 603 typically occurs.

In step 604 , a continuous hydrogenation/plasma nitridation process is performed on the surface 702 of the metal nitride layer 103 . That is, as shown in Figure 7D, surface 702 is exposed to hydrogen atoms and exposed to plasmonic excited nitrogen species 703. In some embodiments, a plasma hydrogenation process is performed in step 604, followed by a plasma nitridation process. In embodiments where the hydrogenation process is a plasma hydrogenation process, both the plasma hydrogenation process and the plasma nitridation process may be performed in the processing chamber 400 and using the processing parameters described above in connection with FIG. 4 . Alternatively, the plasma hydrogenation process may be performed in one of the processing chambers 514, 516, 518, 520, 522, and 524 of the multi-chamber processing system 500, and the plasma nitridation process may be performed in the processing chambers 514, 516, 518, 520, 522, and 524 are performed in the other.

As mentioned previously, in some embodiments, the surface 702 of the metal nitride layer 103 is exposed to hydrogen atoms via a thermal hydrogenation process. In such an embodiment, the thermal hydrogenation process of step 604 is performed in one of the processing chambers 514 , 516 , 518 , 520 , 522 , and 524 of the multi-chamber processing system 500 , eg, configured to use H ₂ gas Rapid thermal processing chamber as process gas. Furthermore, in such an embodiment, the plasma nitridation process is performed in another one of the processing chambers 514, 516, 518, 520, 522, and 524, as similar to the plasma processing chamber 400 in FIG. processing chamber. Therefore, although the thermal hydrogenation process and the plasma nitridation process are each performed in different processing chambers, no air gap occurs between these two processes.

In step 605 , as shown in FIG. 7E , a capping layer 104 is deposited on the annealed first metal layer 102 and metal nitride layer 103 . For example, in one embodiment, the metal capping layer is a Co layer or a cobalt-containing alloy layer. Because the interfacial O atoms that may exist on the surface 702 of the metal nitride layer 103 are removed in step 604, the adhesion between the capping layer 104 and the metal nitride layer 103 is improved over that formed by conventional techniques adhesion in the contact structure. Furthermore, removing O atoms within the metal nitride layer 103 reduces the resistivity of the conductive structure 100 .

In some embodiments, steps 604 and 605 are performed on the same multi-chamber processing system so that no air breaks occur after the sequential hydrogenation and nitridation processes of step 604 . Subsequently, oxidation of the metal nitride layer 103, which may occur during exposure to the atmosphere, is avoided. In other embodiments, the processing chamber used to perform the continuous hydrogenation and nitridation processing of step 604 may be configured on a different multi-chamber processing system than the processing chamber used to perform step 605 . Note that in such an embodiment, the nitridation process of step 604 completely nitrides the surface of the metal nitride layer 103, thereby minimizing or otherwise preventing the voids that may occur during the voids between steps 604 and 605 Oxidation.

8 illustrates a flow diagram of process steps for reducing bulk and interfacial oxygen in contact structures in accordance with some embodiments of the present disclosure. Before step 801, a cleaning process or other surface preparation process may be performed as described above in conjunction with FIG. 7 .

The method 800 begins at step 801 in which a metal layer 102 and a metal nitride layer 103 are deposited on the source or drain structure 101 . Step 801 may be substantially similar to step 601 in method 600 .

In step 802 , a continuous hydrogenation/plasma nitridation process is performed on the surface 702 of the metal nitride layer 103 . That is, surface 702 is exposed to hydrogen atoms and to plasmonic excited nitrogen species. Step 802 may be substantially similar to step 604 in method 600 . Note, however, that unlike step 604, the continuous hydrogenation/plasma nitridation process of step 802 is performed before the thermal annealing process. Furthermore, in some embodiments, step 802 is performed in a chamber configured as part of a multi-chamber processing system that includes a thermal annealing chamber (eg, a rapid thermal processing chamber) for performing step 803 . In such an embodiment, since such O atoms are removed before the annealing process of step 803, the influence of O atoms in the first metal layer 102 and the metal nitride layer 103 deposited in step 801 is further reduced.

In step 803 , a thermal annealing process is performed on the semiconductor substrate 110 including the first metal layer 102 , the metal nitride layer 103 , and the source or drain structure 101 . Step 803 may be substantially similar to step 603 in method 600 . Alternatively, in embodiments in which a thermal hydrogenation process occurs in step 802, a thermal annealing process is performed in step 802, and step 803 may be skipped. For example, in some embodiments, the thermal annealing process whereby silicide 105 is formed is performed in the same processing chamber as the thermal hydrogenation process of step 802 . In such an embodiment, the thermal annealing process may be performed concurrently with the thermal hydrogenation process either immediately before the thermal hydrogenation process, or immediately after the thermal hydrogenation process.

In optional step 804 , a plasma treatment process is performed on surface 702 of metal nitride layer 103 . Step 804 may be substantially similar to step 604 in method 600 . Thus, in embodiments of method 800 in which step 804 is performed, a continuous hydrogenation/nitridation process is performed before and after the thermal annealing process of step 803 . In some embodiments, the continuous hydrogenation/nitridation process performed in step 804 is substantially the same as the plasma treatment process performed in step 802 . In other embodiments, the continuous hydrogenation/nitridation process of step 804 may be different from the continuous hydrogenation/nitridation process of step 802 . For example, the processing parameters for the continuous hydrogenation/nitridation process employed in step 802 may be different from those employed in step 804 for the continuous hydrogenation/nitridation process.

In step 805 , capping layer 104 and/or conductive layer 106 are deposited over annealed first metal layer 102 and metal nitride layer 103 . Step 805 may be substantially similar to step 605 in method 600 . Similarly, in some embodiments, steps 804 and 805 may be performed on the same multi-chamber processing system so that no air-off occurs after the plasma processing process of step 804 . Subsequently, oxidation of the metal nitride layer 103, which can occur during exposure to air, is avoided, and the adhesion between the capping layer 104 and the metal nitride layer 103 is improved, which is better than that of contact structures formed by conventional techniques adhesive force in .

Figure 9 illustrates a flow diagram of process steps for reducing bulk and interfacial oxygen in contact structures in accordance with some embodiments of the present disclosure. Prior to step 901, as described above in connection with method 600, a cleaning process or other surface preparation process may be performed. As shown, method 900 begins at step 901 in which a first metal layer 102 and a metal nitride layer 103 are deposited on the source or drain structure 101 . Step 901 may be substantially similar to step 601 in method 600 . In step 902 , a continuous hydrogenation/nitridation process is performed on the surface 702 of the metal nitride layer 103 . Step 902 may be substantially similar to step 802 in method 800 . In step 903 , a thermal annealing process is performed on the semiconductor substrate 110 , and the semiconductor substrate includes the first metal layer 102 , the metal nitride layer 103 , and the source or drain structure 101 . Step 903 may be substantially similar to step 603 in method 600 . In step 905 , a capping layer 104 is deposited over the annealed first metal layer 102 and metal nitride layer 103 . Step 905 may be substantially similar to step 605 in method 600 . Therefore, in method 900, a continuous hydrogenation/nitridation process is performed before the thermal annealing process of step 903 and not after the thermal annealing process of step 903. Continuous hydrogenation/nitridation processes generally include plasma or thermal hydrogenation processes and plasma nitridation processes.

Although methods 600 and 800 are described for forming contact structures on a substrate, methods 600 and 800 may also be employed to form other conductive structures on a substrate. Accordingly, any conductive structure that includes a metal nitride layer may benefit from being formed by methods 600 or 800 . Metal gate structure with reduced EOT

According to various embodiments of the present disclosure, sequential hydrogenation and nitridation processes are employed in the fabrication of high-k dielectric/metal gate stacks to reduce the effective oxide thickness (EOT) of the stack. In such an embodiment, the EOT of the stack is reduced without loss of leakage increase and flat-band voltage shift, which are known to be in the high-k dielectric layers in the stack. The thickness is only reduced or otherwise scaled down via conventional techniques. One such stack is shown in Figure 10.

FIG. 10 shows a cross-sectional view of a metal gate structure 1000 formed in accordance with an embodiment of the present disclosure. The metal gate structure 1000 is formed on a semiconductor substrate 1001 as part of a semiconductor element such as a MOSFET or other FET. The metal gate structure 1000 is a stack of a plurality of material layers formed on a semiconductor substrate 1001, and includes, for example, an interface layer 1002 disposed on the semiconductor substrate 1001, a high-k dielectric layer 1003 disposed on the interface layer 1002, A metal nitride capping layer 1004 provided on the high-k dielectric layer 1003 , and a metal gate electrode layer 1005 provided on the metal nitride capping layer 1004 . In the embodiment shown in FIG. 10 , the various layers of the metal gate structure 1000 are shown as simple film stacks formed on the semiconductor substrate 1001 . In practice, the metal gate structure 1000 may be formed in a contact well or other cavity formed in an insulating or dielectric material similar to the insulating material 120 in FIG. 1 . Thus, one or more of the interface layer 1002, the high-k dielectric layer 1003, the metal nitride capping layer 1004, and the metal gate electrode layer 1005 may be layers of materials that are conformally deposited within the cavity.

The semiconductor substrate 1001 can be any suitable semiconductor substrate on which the metal gate structure 1000 can be formed. Accordingly, the semiconductor substrate 1001 may be formed of any suitable semiconductor material, including but not limited to Si (Si), Ge (germanium), silicon germanium (Si-Ge), silicon germanium carbon (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and all other group III/V or group II/VI compound semiconductors. Alternatively or additionally, the semiconductor substrate 1001 may be a layered semiconductor, eg, Si/Si-Ge, semiconductor-on-insulator (SOI), or Si-Ge-on-insulator (SiGOI). Furthermore, in some embodiments, the semiconductor substrate 1001 includes doped and/or undoped regions, such as n-doped or p-doped regions adjacent to the interface oxide layer 1002 .

The interface oxide layer 1002 is disposed on the semiconductor substrate 1001 between the semiconductor substrate 1001 and the high-k dielectric layer 1003 and is configured as an interface oxide layer suitable for application in the metal gate structure 1000 . In embodiments in which the semiconductor substrate 1001 includes a Si-containing material, the interface _oxide 1002 layer may include silicon _oxide ( _SiOx ), silicon oxynitride (SiNO, _Si2NO , Si2N2O), and/or nitride of silicon oxide. In embodiments where the semiconductor 1001 is not a Si-containing semiconductor material, the interface oxide layer 1002 may comprise a semiconductor oxide, a semiconductor oxynitride, and/or a nitrided semiconductor oxide.

The interface oxide layer 1002 may be formed via any suitable thermal or wet growth technique (eg, oxidation or oxynitride). For example, and without limitation, the interface oxide layer 1002 may be formed by a wet chemical oxidation process that includes treating the cleaned surface of the semiconductor substrate 1001 with a mixture of ammonium hydroxide, hydrogen peroxide and water, as above HF-treated semiconductor surface. Alternatively, the interfacial oxide layer 1002 may be formed by treating the previously HF treated semiconductor surface in an ozonated aqueous solution. Alternatively, the interface oxide layer 1002 may be formed by any suitable thermal oxidation technique.

The thickness of the interface oxide layer 1002 varies with the semiconductor device of which the metal gate structure 1000 is a part. In addition, the interface oxide layer 1002 is significantly thinner than the high-k dielectric layer 1003 , the metal nitride capping layer 1004 , and the metal gate electrode layer 1005 . Typically, the interface oxide layer 1002 has a thickness of from about 0.5 to 2.0 nm, although the interface oxide layer 1002 may be thicker in some embodiments. In some embodiments, the thermal process for device fabrication that occurs after the formation of the metal gate structure 1000 can further increase the thickness of the interface oxide layer 1002 .

The high-k dielectric layer 1003 may be a gate dielectric layer or other dielectric layers in the metal gate structure 1000, and includes so-called "high-k dielectric" materials. More specifically, high-k dielectric layer 1003 includes one or more materials having a dielectric constant greater than SiO ₂ , such as a material having a dielectric constant of at least about 4.0, or desirably at least about 10.0 . Furthermore, the high-k dielectric material included in the high-k dielectric layer 1003 is suitable for use in integrated circuits. Therefore, in addition to the high dielectric constant, the one or more high-k dielectric materials included in the high-k dielectric layer 1003 also desirably have the ability to prevent dopant diffusion, less available Electrical defects that impair breakdown performance, good thermal stability, and high recrystallization temperatures. Examples of such high-k dielectric materials suitable for use in high-k dielectric layer 1003 include, but are not limited to, silicon nitride, silicon oxynitride, metal oxides, metal nitrides, metal oxynitrides, and / or metal silicates. In some embodiments, the high-k dielectric layer 1003 includes one or more of the following: hafnium oxide (Hf _x O _y ), zirconium oxide (ZrO ₂ ), hafnium silicate oxide (Hf _x Si _{1-x )} O _y ), or other hafnium based dielectrics, lanthanum oxide (La ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), strontium titanate (SrTiO ₃ ), lanthanum aluminate ( LaAlO ₃ ), yttrium oxide (Y ₂ O ₃ ), hafnium silicate oxide (Hf _x Si _1-x O _y ), lanthanum oxide (La ₂ O ₃ ), and/or multiple layer stacks of the above.

The high-k dielectric layer 1003 may be formed by any suitable deposition method, including thermal growth processes, eg, oxidation, nitridation, or oxynitride processes. Alternatively, the high-k dielectric layer 1003 may be formed by one or more deposition processes, including but not limited to chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition) deposition; PECVD), metalorgano chemical vapor deposition (MOCVD), atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition, and/or any combination thereof.

The thickness 1003A of the high-k dielectric layer 1003 may depend on the dielectric material included therein, the process used to form the high-k dielectric layer 1003, and the geometry and operation of the semiconductor device in which the metal gate structure 1000 is included and change. In some embodiments, the thickness 1003A of the high-k dielectric layer 1003 is from about 1.0 nm to about 20 nm.

The metal nitride capping layer 1004 is a metal layer disposed on the high-k dielectric layer 1003 , which is typically configured as a conductive protective layer on the high-k dielectric layer 1003 . Accordingly, in some embodiments, metal nitride capping layer 1004 is configured to prevent undesired oxidation of semiconductor substrate 1001 and/or high-k dielectric layer 1003 . Furthermore, in such embodiments, the metal nitride capping layer 1004 may also be configured to allow oxygen to diffuse out of the high-k dielectric layer 1003 during a thermal annealing process that occurs after the deposition of the metal nitride capping layer 1004 . In such an embodiment, the metal nitride capping layer 1004 may also be configured to allow oxygen to diffuse out of the interface layer 1009 formed between the high-k dielectric layer 1003 and the metal nitride capping layer 1004 during the thermal annealing process .

In some embodiments, the metal nitride capping layer 1004 includes metal nitrides such as silicon nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), and the like. Note that, in some embodiments, depositing the nitride capping layer 1004 over the high-k dielectric layer 1003 may result in the formation of an interfacial layer 1009 between the high-k dielectric layer 1003 and the metal nitride capping layer Set at the interface between 1004. According to some embodiments, the interfacial layer 1009 is subsequently eliminated or reduced in thickness when a continuous plasma hydrogenation and nitridation process as described herein is applied to the exposed surface of the metal nitride capping layer 1004 .

The metal nitride capping layer 1004 may be formed by any suitable deposition method, including but not limited to PVD processes, CVD processes, PECVD processes, MOCVD processes, ALD evaporation processes, reactive sputtering, chemical solution deposition, and/or any combination thereof.

In some embodiments, the metal nitride capping layer 1004 is significantly thinner than the high-k dielectric layer 1003 and the metal gate electrode layer 1005 . For example, in an embodiment of the metal gate structure 1000 wherein the high-k dielectric layer 1003 is a HfO ₂ layer having a thickness of about 20 nm to about 40 nm and the metal gate electrode layer 1005 is about 20 nm to about 40 nm thick A TiN layer with a thickness of about 40 nm, the metal nitride capping layer 1004 may have a thickness 1004A of about 5 nm to about 15 nm.

In some embodiments, the thickness 1004A of the metal nitride capping layer 1004 is selected to facilitate the diffusion of oxygen atoms from the high-k dielectric layer 1003 and/or the interface layer 1009 . Specifically, in such an embodiment, thickness 1004A is selected such that O atoms diffuse from high-k dielectric layer 1003 and/or interface layer 1009 during the thermal annealing process that occurs after deposition of metal nitride capping layer 1004 . In such an embodiment, the thickness 1004A is selected to be less than the diffusion length of O atoms through the metal nitride capping layer 1004 during the thermal annealing process. In one example, one such thermal anneal process is a tip anneal process performed on the metal gate structure 1000 for a duration of 1-2 seconds and a peak temperature of about 700 to about 900°C.

Metal gate electrode layer 1005 is a metal layer formed on metal nitride capping layer 1004 and includes one or more deposited metal layers. In some embodiments, the metal gate electrode layer 1005 is configured as the gate electrode and/or work function metal of the metal gate structure 1000 . In such an embodiment, the one or more metal layers included in the metal gate layer 1005 are selected to have a common gate work function value that facilitates the metal gate structure 1000 and the inclusion of metal therein Operation of the semiconductor element of the gate structure 1000 . The metal gate electrode 1005 may be formed via any suitable deposition method, including but not limited to CVD, PECVD, MOCVD, ALD, evaporation, reactive sputtering, chemical solution deposition, and/or any combination thereof.

In some embodiments, the metal gate electrode layer 1005 is a p-metal gate material, such as TiN. Alternatively, in some embodiments, the metal gate electrode layer 1005 is an n-metal gate. Suitable N metals for use in the metal gate electrode layer 1005 include titanium aluminum carbide (Ti _x AlC). Formation of metal gate structures with reduced EOT

According to various embodiments, during fabrication of the metal gate structure 1000, prior to depositing the metal gate electrode layer 1005, a continuous plasma hydrogenation and nitridation process is performed on the metal nitride capping layer 1004. In such an embodiment, the EOT of the metal gate structure 1000 is reduced, while the leakage current of the metal gate structure 1000 is increased by a lower than desired amount. Furthermore, in such embodiments, the metal gate structure 1000 exhibits little or no flat-band voltage shift typically associated with reduced EOT.

For example, in one embodiment of the metal gate structure 1000, the interface oxide layer 1002 has a thickness of about 1-2 nm, the high-k dielectric layer 1003 has a thickness 1003A of about 2-3 nm, and the metal nitride capping Layer 1004 has a thickness 1004A of about 3-4 nm. In such an embodiment, one measurable effect of treating the metal nitride capping layer 1004 with the continuous plasma hydrogenation and nitridation process described herein is that the measurable EOT of the metal gate structure 1000 is reduced by about 1 Å (ie, , down from about 9 Å to about 8 Å). Another effect of such treatment of metal nitride capping layer 1004 is that (at a flat-band voltage of -1 V) leakage current increases by a factor of about 2.4 (ie, from about 0.268 A/cm ² to about .658 A/cm 2 ) ² ). In contrast, according to established scaling trends known in the art, when the EOT of the metal gate structure 1000 is instead reduced by conventional techniques (eg, by scaling down the thickness 1003A by about 1 Å) , the leakage current is expected to increase by a factor of about 10. Accordingly, it has been found that treating the metal nitride capping layer 1004 with the continuous plasma hydrogenation and nitridation process described herein has approximately approx. quarter to reduce the impact of the EOT of the metal gate structure 1000 .

Furthermore, in addition to the EOT reduction described above, it has been shown that the flat-band voltage offset measured in the metal gate structure 1000 remains substantially constant when the metal gate structure 1000 is formed using a continuous plasma hydrogenation and nitridation process. Stablize. Therefore, applying a continuous plasma hydrogenation and nitridation process to the metal nitride capping layer 1004 enables the fabrication of a metal gate structure 1000 with reduced EOT without flat band voltage shift and without impact on device design.

11 illustrates a flow diagram of process steps for reducing EOT in metal gate structures in accordance with various embodiments of the present disclosure. FIGS. 12A to 12J are schematic cross-sectional views of semiconductor devices corresponding to different stages of the process of FIG. 11 according to various embodiments of the present disclosure.

The method 1100 begins at step 1101 , as shown in FIG. 12A , wherein a high-k dielectric layer 1003 is deposited on the interface oxide layer 1002 . The high-k dielectric layer 1003 may be formed via any suitable deposition method described above in connection with FIG. 10 .

In step 1102 , as shown in FIG. 12B , a metal nitride capping layer 1004 is deposited on the high-k dielectric layer 1003 . Metal nitride capping layer 1004 may be formed via any suitable deposition method described above in connection with FIG. 10 . In some embodiments, depositing the metal nitride capping layer 1004 results in the formation of an interfacial layer 1009 disposed at the interface between the high-k dielectric layer 1003 and the metal nitride capping layer 1004 . In such embodiments, interface layer 1009 typically includes vacancies (which may be similar to vacancies 213 in Figure 2A) and/or O atoms introduced during the deposition process of step 1102 by contamination present in the processing environment.

In optional step 1103, the exposed surface 1201 shown in Figure 12B is exposed to air. For example, in some embodiments, the metal nitride capping layer 1004 is deposited in one processing system, such as the multi-chamber processing system 500 in FIG. 5, while the next processing step to be performed on the semiconductor substrate 1001 is performed in a different executed in the processing system. Therefore, in such an embodiment, after depositing the metal nitride layer 1004, the semiconductor substrate 1001 is exposed to air. In embodiments where the metal nitride capping layer 1004 is deposited in one chamber of a multi-chamber processing system and step 1104 is performed in one or two other processing chambers of the same multi-chamber processing system, no Optional step 1103.

In an embodiment where the metal nitride capping layer 1004 deposited in step 1102 is a sacrificial metal nitride layer that is subsequently removed, the method 1100 proceeds to step 1131 . In an embodiment where the metal nitride capping layer 1004 deposited in step 1102 remains in the metal gate structure 1000 , the method 1100 proceeds to step 1104 . In some embodiments, the sacrificial metal nitride layer can be removed by using a subsequent wet or dry etch process that is selective to the removal of the metal nitride capping layer 1004 .

In step 1104 , as shown in FIG. 12C , a continuous plasma hydrogenation and nitridation process is performed on the surface 1201 of the metal nitride capping layer 1004 . The plasma hydrogenation and nitridation process may be substantially similar to the plasma hydrogenation and nitridation process described above in connection with FIG. 4 . Additionally, the plasma hydrogenation process includes non-oxidizing plasma-excited hydrogen species and does not include any oxidizing plasma-excited hydrogen species.

In some embodiments, the RF power is at about 500 W at a chamber pressure between about 20 mTorr and about 100 mTorr, at a processing temperature (eg, substrate pedestal temperature) between about 400 °C and about 500 °C and about 1500 W, the flow rate of H is between about ₂₀ sccm and about 100 sccm, and the flow rate of Ar is between about 900 sccm and about 980 sccm, and the plasma hydrogenation process of step 1104 is performed for about 30 Duration between seconds and about 150 seconds. In some embodiments, the flow rate of H ₂ is between about 1% and about 15% of the total process gas introduced into the chamber. In some embodiments, at a chamber pressure between about 45 mTorr and about 55 mTorr, at a process temperature between about 425°C and about 475°C, wherein the RF power is between about 700 W and about 800 W , the flow rate of H ₂ is between about 45 sccm and about 55 sccm, and the flow rate of Ar is between about 965 sccm and about 955 sccm, and the plasma hydrogenation process of step 1104 is performed for between about 85 seconds and about 95 seconds duration in between.

In some embodiments, at a chamber pressure between about 10 mTorr and about 50 mTorr, at a process temperature between about 400°C and about 500°C, wherein the RF power is between about 500 W and about 1500 W , the flow rate of _NH3 is between about 1% and about 10% of the total process gas flow rate, the flow rate of _N2 is between about 45% and about 55% of the total process gas flow rate, and the flow rate of Ar Selected to be equal to the remainder of the process gas flow, the plasma nitridation process of step 1104 is performed for a duration between about 30 seconds and about 150 seconds. In some embodiments, at a chamber pressure between about 15 mTorr and about 25 mTorr, at a process temperature between about 425°C and about 475°C, wherein the RF power is between about 700 W and about 800 W , the flow rate of _NH3 is between about 2% and about 3% of the total process gas flow rate, the flow rate of _N2 is between about 45% and about 55% of the total process gas flow rate, and the flow rate of Ar Selected to be equal to the remainder of the process gas flow, the plasma nitridation process of step 1104 is performed for a duration between about 85 seconds and about 95 seconds.

In summary, in step 1104, substrate 1201 is exposed to plasma excited hydrogen species generated during a plasma hydrogenation process, and some or all oxides present on surface 1201 are reduced. Additionally, in some embodiments, such plasmonic excited hydrogen species may also reduce some or all of the oxygen (O) atoms present in the host material of the metal nitride capping layer 1004 . Additionally, in step 1104, the substrate 1201 is exposed to plasma excited nitrogen species generated during the plasma nitridation process, thereby saturating the surface 1201 with N atoms, and in some embodiments, filling the surface 1201 with N atoms. The vacancies present in the host material of the metal nitride capping layer 1004 . Thus, in some embodiments, as shown in Figure 12D, the interface layer 1009 is eliminated or significantly reduced.

In some embodiments, the plasma hydrogenation process of step 1104 is performed in the same process chamber as the plasma nitridation process of step 1104 , eg, process chamber 400 of FIG. 4 . Alternatively, the plasma hydrogenation process of step 1104 is performed in a first processing chamber of a multi-chamber processing system, and the plasma nitridation process of step 1104 is performed in a second processing chamber of the same multi-chamber processing system. In either case, note that the surface 1201 is not exposed to air between the plasma hydrogenation process and the plasma nitridation process of step 1104. Thus, in either embodiment, surface 1201 is not exposed to air after exposure to plasmonic excited hydrogen species and prior to exposure to plasmonic excited nitrogen species.

In some embodiments, an oxygen-free conditioning process is performed in the processing chamber prior to performing the plasma hydrogenation process in the processing chamber, eg, to reduce trace oxygen contamination in the processing chamber. In such an embodiment, the processing chamber is treated with an oxygen-free plasma without placing the substrate therein and prior to processing the substrate via the plasma hydrogenation process described above. Such plasma processing of the processing chamber prior to introduction of the substrate into the chamber is sometimes referred to as plasma every wafer (PEW) process or PEW processing.

In some embodiments, such a PEW process includes introducing one or more non-oxygen-containing gases (eg, N ₂ , NH ₃ , Ar, H ₂ , or any suitable combination thereof) into a processing chamber, and energizing one or more More gases to form an oxygen-free plasma. Alternatively, the PEW process may include introducing plasma radicals and/or ions containing N, H, or _NH3 , or any suitable combination thereof, into a processing chamber, wherein the plasma is in a remote plasma source outside the processing chamber form. In one embodiment, _NH3 gas or a combination of _NH3 and Ar gas is introduced into the processing chamber. In another embodiment, _H2 gas or a combination of _H2 and Ar gas is introduced into the processing chamber. In yet another embodiment, _N2 gas or a combination of _N2 and Ar gases is introduced into the processing chamber.

Typically, plasma processing of a processing chamber prior to introduction of the substrate involves introducing or forming a hydrogen and/or nitrogen containing plasma in the processing chamber. In some embodiments, radicals (eg, N*, NH*, and/or H*) generated by the plasma inside the processing chamber during the PEW process react with traces of O atoms within the processing chamber.

In some embodiments, one or more gases introduced into the processing chamber are excited by an RF power source, such as RF power source 414 of FIG. 4, during the PEW process. The RF power can be pulsed at 2% to 70% duty cycle and can vary from about 100 W to about 2500 W. The RF power may be a continuous wave varying from about 100 W to about 2500 W. In such an embodiment, at a chamber pressure of about 10 mTorr to about 200 mTorr, at a process temperature of between about 400°C and about 500°C, wherein the RF power is between about 250 W and about 750 W, The flow rate of H ₂ is between about 50 sccm and about 200 sccm, and the flow rate of O ₂ is between about 450 sccm and about 550 sccm, and the PEW process of step 1104 is performed for between about 20 seconds and about 100 seconds duration.

In optional step 1105, exposed surface 1201 is exposed to air. For example, in some embodiments, the continuous hydrogenation and nitridation processes described above are performed in one processing system, while the next processing steps to be performed on the semiconductor substrate 1001 are performed in a different processing system. Therefore, in such an embodiment, after depositing the metal nitride layer 1004, the semiconductor substrate 1001 is exposed to air. In embodiments where the continuous hydrogenation and nitridation process is performed in one chamber of a multi-chamber processing system and step 1106 is performed in another processing chamber of the same multi-chamber processing system, optional steps are not performed 1105.

In an embodiment in which a sacrificial silicon-containing layer is subsequently deposited and removed as part of forming the metal gate structure 1000 , the method 1100 proceeds from step 1105 to step 1121 . In an embodiment in which no sacrificial silicon layer is deposited when forming the metal gate structure 1000 , the method 1100 proceeds to step 1106 . The sacrificial silicon-containing layer can be formed by using a CVD or ALD process that uses one or more silicon-containing precursor gases to form the deposited layer.

In step 1106 , a thermal annealing process (eg, annealing after capping) is performed on the semiconductor substrate 1001 , the interface layer 1002 , the high-k dielectric layer 1003 , and the metal nitride capping layer 1004 . For example, in some embodiments, a tip annealing process is performed in step 1106 where a peak temperature of about 600 to 900°C is reached. Post-cap annealing is performed on the partially formed metal gate structure 1000 to smooth the interface, repair unsaturated bonds, and inject thermal energy into the metal nitride capping layer.

In step 1107 , as shown in FIG. 12E , a metal gate electrode layer 1005 is deposited on the processed metal nitride capping layer 1004 , thereby completing the formation of the metal gate structure 1000 . The metal gate electrode 1005 may be formed via any suitable deposition method described above in connection with FIG. 10 .

In step 1121, as shown in FIG. 12F, a sacrificial silicon layer 1202 is deposited over the metal nitride capping layer 1004. Step 1121 is performed after the surface 1201 of the metal nitride capping layer 1004 is treated by the continuous plasma hydrogenation and nitridation process of step 1104 and the optional air exposure of step 1105 .

The sacrificial silicon layer 1202 may comprise any suitable silicon-containing material, such as amorphous silicon, and may be deposited using any suitable deposition process known in the art, such as a CVD process. A sacrificial silicon layer 1202 is deposited over the metal nitride capping layer 1004 to reduce damage to the metal nitride capping layer 1004, the interface layer 1009 (if still present), and the high dielectric during subsequent thermal annealing processes (such as the so-called post-cap annealing process). Formation of oxide in dielectric constant dielectric layer 1003 . In some embodiments, the post-cover annealing process includes an atmospheric thermal annealing process. Subsequently, further oxidation of the very thin layers of the metal gate structure 1000 may occur, including the interface layer 1002 , the high-k dielectric layer 1003 , and the metal nitride capping layer 1004 , thereby increasing the EOT of the metal gate structure 1000 . However, there is a layer in which the sacrificial silicon layer 1202 can shield the metal gate structure 1000 from atmospheric O atoms during the pre-cover anneal process. Additionally, the sacrificial silicon layer 1202 can react with and thereby retain O atoms that diffuse out of the high-k dielectric layer 1003, the interface layer 1009 (if still present), and the metal nitrogen during the thermal annealing process Compound capping layer 1004. Thus, sacrificial silicon layer 1202 minimizes or eliminates the possibility of undesirably oxidizing portions of metal gate structure 1000 during subsequent thermal annealing processes.

In step 1122 , a thermal annealing process (eg, annealing after capping) is performed on the semiconductor substrate 1001 , the interface layer 1002 , the high-k dielectric layer 1003 , the metal nitride capping layer 1004 , and the sacrificial silicon layer 1202 . The thermal annealing process of step 1122 may be substantially similar to the thermal annealing process of step 1106 described above.

In step 1123, the sacrificial silicon layer 1202 is removed from the metal gate structure 1000. Any technically feasible removal process may be employed in step 1123, including a selective wet etch process, a plasma-based dry etch process, a chemical mechanical polishing process, or any combination thereof. The method 1100 then proceeds to step 1107 where the final layer of the metal gate structure 1000 is deposited.

In step 1131, as shown in Figure 12G, a sacrificial silicon layer 1203 is deposited over the metal nitride capping layer 1004. The sacrificial silicon layer 1203 may be substantially similar to the sacrificial silicon layer 1202 deposited in step 1131 . However, note that in step 1131, the metal nitride capping layer 1004 has not been treated with the continuous plasma hydrogenation and nitridation process. Subsequently, the metal nitride capping layer 1004 may still include the interface layer 1009 as shown.

In step 1132 , a thermal annealing process (eg, post-cover annealing) is performed on the semiconductor substrate 1001 , the interface layer 1002 , the high-k dielectric layer 1003 , the metal nitride cover layer 1004 , the interface layer 1009 , and the sacrificial silicon layer 1203 . The thermal annealing process of step 1132 may be substantially similar to the thermal annealing process of step 1106 described above.

In step 1133 , as shown in FIG. 12H , the sacrificial silicon layer 1203 , the metal nitride capping layer 1004 , and the interface layer 1009 are removed from the metal gate structure 1000 . Any technically feasible removal process or combination of processes may be employed in step 1123, including a selective wet etch process, a plasma-based dry etch process, a chemical mechanical polishing process, or any combination thereof. Method 1100 then proceeds to step 1134 .

In step 1134, as shown in FIG. 12I, a final metal nitride capping layer 1204 is deposited over the high-k dielectric layer 1003. The final metal nitride capping layer 1204 may be substantially similar to the metal nitride capping layer 1004 and may include an interfacial layer 1009 .

In optional step 1135, the exposed surface 1205 shown in Figure 12I is exposed to air. For example, in some embodiments, the final metal nitride capping layer 1204 is deposited in one processing system and the next processing step to be performed on the semiconductor substrate 1001 (ie, step 1136 ) is performed in a different processing system. Thus, in such an embodiment, the semiconductor substrate 1001 is exposed to air after the final metal nitride layer 1204 is deposited. In embodiments where the final metal nitride capping layer 1204 is performed in one chamber of a multi-chamber processing system and step 1136 is performed in one or two other processing chambers of the same multi-chamber processing system, no Optional step 1135 is performed.

In step 1136, as shown in Figure 12J, a continuous plasma hydrogenation and nitridation process is performed on the surface 1205 of the final metal nitride capping layer 1204. The continuous plasma hydrogenation and nitridation process performed in step 1136 may be substantially similar to the process employed in step 1104 . Subsequently, the interfacial layer 1009 may be eliminated or reduced during step 1136, thereby removing O atoms present in the final metal nitride capping layer 1204, interfacial layer 1009, and in some embodiments high-k dielectric layer 1003. Therefore, without scaling down the thickness 1003A of the high-k dielectric layer 1003, the EOT of the metal gate structure 1000 is reduced.

After performing the continuous plasma hydrogenation and nitridation process in step 1136, the method 1100 proceeds to step 1107 where the final layer of the metal gate structure 1000 is deposited. In an embodiment, where steps 1136 and 1107 are performed in different processing systems, the semiconductor substrate 1001 must be exposed to air. However, because the plasma nitridation process of step 1136 can completely or nearly completely nitride the exposed surface 1205 of the final metal nitride capping layer 1204, little or no oxidation thereof typically occurs during this air exposure. One-step nitridation - hydrogenation treatment

The method 1300 begins at step 1301 , as shown in FIG. 14A , wherein a high-k dielectric layer 1003 is deposited on the interface oxide layer 1002 . The interface oxide layer 1002 may be deposited by any suitable method, such as chemical oxidation of the underlying semiconductor substrate 1001, thermal oxidation of the underlying substrate, atomic layer deposition (ALD), chemical vapor deposition (CVD), or similar. The high-k dielectric layer 1003 may be formed via any suitable deposition method described above in connection with FIG. 10 . The high-k dielectric layer 1003 may comprise any high-k material that is oxidizable. According to one embodiment, the high-k dielectric layer 1003 includes silicon dioxide (SiO ₂ ) or hafnium oxide (HfO ₂ ).

In step 1302, a capping layer 1404 is deposited on the high-k dielectric layer 1003 as shown in FIG. 14B. The capping layer 1404 may be formed via any suitable deposition method described above in connection with FIG. 10 . The capping layer 1404 may include metal nitride. According to one embodiment, the capping layer may include a metal nitride, such as titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TAN), or titanium silicon nitride (TiSiN). In some embodiments, depositing capping layer 1404 results in the formation of interfacial layer 1409 disposed at the interface between high-k dielectric layer 1003 and capping layer 1404 . In such embodiments, interface layer 1409 typically includes defects such as vacancies (which may be similar to vacancies 213 in Figure 2A) and/or O introduced during the deposition process of step 1302 by contamination present in the processing environment atom. Defects can allow undesired charge transfer due to electron hopping between defects. The charge transfer can cause current leakage or dielectric breakdown, thereby reducing the electrical reliability of the metal gate structure 1000 .

In optional step 1303, the exposed surface 1401 shown in Figure 14B is exposed to air. For example, in some embodiments, capping layer 1404 is deposited in one processing system, such as multi-chamber processing system 500 in Figure 5, while the next processing step to be performed on semiconductor substrate 1001 is performed in a different processing system . Thus, in such an embodiment, the semiconductor substrate 1001 is exposed to air after the capping layer 1404 is deposited. In embodiments where capping layer 1404 is deposited in one chamber of a multi-chamber processing system and step 1304 is performed in one or two other processing chambers of the same multi-chamber processing system, optional steps are not performed 1303.

In an embodiment wherein the capping layer 1404 deposited in step 1302 is a sacrificial layer that is subsequently removed, the method 1400 proceeds to step 1331 . In an embodiment where the capping layer 1404 deposited in step 1302 remains in the metal gate structure 1000 , the method 1300 proceeds to step 1304 . In some embodiments, the sacrificial layer can be removed by using a subsequent wet or dry etch process that is selective to the removal of the capping layer 1404 .

In step 1304 , as shown in FIG. 14C , a single-step plasma hydrogenation and nitridation process is performed on the surface 1401 of the capping layer 1404 . The single-step plasma hydrogenation and nitridation process involves exposing the workpiece, such as the metal gate structure 1000, to a processing plasma, wherein the processing plasma includes a nitrogen-containing gas and a hydrogen-containing gas. In some embodiments, the hydrogen-containing gas comprises substantially both nitrogen-containing and hydrogen-containing gases, such as ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or hydrogen azide (HN ₃ ). In one example, the hydrogen-containing gas includes ammonia (NH ₃ ), and the nitrogen-containing gas includes (N ₂ ). According to one embodiment, the treatment plasma may include a single gas containing hydrogen and nitrogen, such as hydrazine (N ₂ H ₄ ) or ammonia (NH ₃ ). According to one embodiment, the processing plasma may include an additional neutral carrier gas, such as argon (Ar), or helium (He). In one example, the process gas contained in the process plasma consists essentially of ammonia ( _NH3 ), nitrogen ( _N2 ), and a neutral carrier gas such as argon (Ar) or helium (He). Additionally, a bias voltage may be applied to the substrate by bias power supply 426 during the single-step plasma hydrogenation and nitridation process of step 1304 . Similar to RF power supply 414, bias power supply 426 is generally capable of generating RF signals having tunable frequencies ranging from about 2 MHz to about 160 MHz and powers between about 0 kW and about 10 kW. The bias power improves the conformality of the grown film by rearranging the deposited atoms.

In some embodiments, the RF power is at about 300 W at a chamber pressure between about 10 mTorr and about 100 mTorr, at a processing temperature (eg, substrate pedestal temperature) between about 350°C and about 500°C between about 2000 W, a flow rate of NH between about ₅ sccm and about 100 sccm, a flow rate of N between about 50 sccm and about 1000 sccm, and a helium (He) flow rate of about ₁ to about Between 1000 seem, the single-step plasma hydrogenation and nitridation process of step 1304 is performed for a duration between about 30 seconds and about 150 seconds, and applied with a frequency from about 2 MHz to about 160 MHz, and at about 0 Substrate bias for bias power between kW and about 10 kW.

In some embodiments, at a chamber pressure between about 15 mTorr and about 25 mTorr, at a process temperature between about 425°C and about 475°C, wherein the RF power is between about 900 W and about 1100 W , the flow rate of NH ₃ is between about 15 sccm and about 35 sccm, the flow rate of N ₂ is between about 450 sccm and about 550 sccm, and the flow rate of Ar is between about 450 sccm and about 500 sccm, and the flow rate of step 1304 is performed. The single-step plasma hydrogenation and nitridation process was performed for durations between about 85 seconds and about 95 seconds, and no substrate bias power was applied.

In summary, in step 1304, surface 1401 is exposed to plasma excited hydrogen and nitrogen species generated during the plasma process, and some or all of the oxides present on surface 1401 are converted to nitrides. Thus, as shown in Figure 14D, in some embodiments, the thickening of the interfacial layer 1409 is eliminated or substantially reduced. The interface layer 1409 remains, but no layer thickening occurs. The reduction or nitridation of the interface layer 1409 reduces the EOT and changes the work function of the metal gate structure 1000 .

In some embodiments, prior to performing the single-step plasma hydrogenation and nitridation process of step 1304, an oxygen-free conditioning process is performed in the processing chamber, eg, to reduce trace oxygen contamination in the processing chamber. In such an embodiment, the processing chamber is treated with an oxygen-free plasma without placing the substrate therein and prior to processing the substrate through the single-step plasma hydrogenation and nitridation process described above.

In optional step 1305, exposed surface 1401 is exposed to air. For example, in some embodiments, the single-step plasma hydrogenation and nitridation process of step 1304 above is performed in one processing system, while the next processing step to be performed on the semiconductor substrate 1001 is performed in a different processing system. Therefore, in such an embodiment, after deposition of layer 1404, semiconductor substrate 1001 is exposed to air. In an embodiment, the single-step plasma hydrogenation and nitridation process of step 1304 is performed in one chamber of a multi-chamber processing system, and step 1306 is performed in another processing chamber of the same multi-chamber processing system , optional step 1305 is not performed.

In an embodiment in which a sacrificial silicon-containing layer is subsequently deposited and removed as part of forming the metal gate structure 1000 , the method 1300 proceeds from step 1305 to step 1321 . In an embodiment in which no sacrificial silicon layer is deposited when forming the metal gate structure 1000 , the method 1300 proceeds to step 1306 . The sacrificial silicon-containing layer can be formed by using a CVD or ALD process that uses one or more silicon-containing precursor gases to form the deposited layer.

In step 1306 , a thermal annealing process (eg, annealing after capping) is performed on the semiconductor substrate 1001 , the interface layer 1002 , the high-k dielectric layer 1003 , and the capping layer 1404 . For example, in some embodiments, a tip annealing process is performed in step 1306, wherein a peak temperature of about 600°C to about 900°C is reached. Post-cap annealing is performed on the partially formed metal gate structure 1000 to smooth the interface, repair unsaturated bonds, and inject thermal energy into the cap layer 1404 .

In step 1307 , as shown in FIG. 14E , a metal gate electrode layer 1005 is deposited on the processed capping layer 1404 , thereby completing the formation of the metal gate structure 1000 . The metal gate electrode 1005 may be formed via any suitable deposition method described above in connection with FIG. 10 .

In step 1321, as shown in FIG. 14F, a sacrificial silicon layer 1202 is deposited over capping layer 1404. Step 1321 is performed after the surface 1401 of the capping layer 1404 has been treated by the single-step plasma hydrogenation and nitridation process of step 1304 and the optional air exposure of step 1305 .

In step 1322 , a thermal annealing process (eg, annealing after capping) is performed on the semiconductor substrate 1001 , the interface layer 1002 , the high-k dielectric layer 1003 , the capping layer 1404 , and the sacrificial silicon layer 1202 . The thermal annealing process of step 1322 may be substantially similar to the thermal annealing process of step 1306 described above.

In step 1323, the sacrificial silicon layer 1202 is removed from the metal gate structure 1000. Any technically feasible removal process may be employed in step 1323, including a selective wet etch process, a plasma-based dry etch process, a chemical mechanical polishing process, or any combination thereof. The method 1300 then proceeds to step 1307 where the final layer of the metal gate structure 1000 is deposited.

In step 1331, as shown in FIG. 14G, a sacrificial silicon layer 1203 is deposited over capping layer 1404. The sacrificial silicon layer 1203 may be substantially similar to the sacrificial silicon layer 1202 deposited in step 1331 . Note, however, that in step 1331, cap layer 1404 has not been treated with a single-step plasma hydrogenation and nitridation process. Subsequently, the capping layer 1404 may still include the interface layer 1409 as shown.

In step 1332 , a thermal annealing process (eg, annealing after capping) is performed on the semiconductor substrate 1001 , the interface layer 1002 , the high-k dielectric layer 1003 , the capping layer 1404 , the interface layer 1409 , and the sacrificial silicon layer 1203 . The thermal anneal process of step 1332 may be substantially similar to the thermal anneal process of step 1306 described above.

In step 1333 , as shown in FIG. 14H , the sacrificial silicon layer 1203 , the capping layer 1404 , and the interface layer 1409 are removed from the metal gate structure 1000 . Any technically feasible removal process or combination of processes may be employed in step 1333, including a selective wet etch process, a plasma-based dry etch process, a chemical mechanical polishing process, or any combination thereof. Method 1300 then proceeds to step 1334.

In step 1334, a final capping layer 1404f is deposited over the high-k dielectric layer 1003 as shown in FIG. 14I. The final capping layer 1404f may be composed of the same material of the capping layer 1404, and the final capping layer may also include the interface layer 1409.

In optional step 1335, the exposed surface 1405 shown in Figure 14I is exposed to air. For example, in some embodiments, the final capping layer 1404f is deposited in one processing system, while the next processing step to be performed on the semiconductor substrate 1001 (ie, step 1336) is performed in a different processing system. Thus, in such an embodiment, the semiconductor substrate 1001 is exposed to air after deposition of the final capping layer 1404f. In embodiments where the final capping layer 1404f is deposited in one chamber of a multi-chamber processing system and step 1336 is performed in one or two other processing chambers of the same multi-chamber processing system, optional Step 1335.

In step 1336, as shown in Figure 14J, a single-step plasma hydrogenation and nitridation process is performed on the surface 1405 of the final capping layer 1404. The single-step plasma hydrogenation and nitridation process performed in step 1336 may be substantially similar to the process employed in step 1304. Subsequently, interfacial layer 1409 thickening may be eliminated or reduced during step 1336, thereby removing O atoms present in final capping layer 1404f, interfacial layer 1009, and in some embodiments high-k dielectric layer 1003. Therefore, without scaling down the thickness 1003A of the high-k dielectric layer 1003, the EOT of the metal gate structure 1000 is reduced.

After performing the single-step plasma hydrogenation and nitridation process in step 1336, the method 1300 proceeds to step 1307, where the final layer of the metal gate structure 1000 is deposited. In an embodiment where steps 1336 and 1307 are performed in different processing systems, the semiconductor substrate 1001 must be exposed to air. However, because the plasma nitridation process of step 1336 can completely or nearly completely nitride the exposed surface 1405 of the final capping layer 1404f, little or no oxidation thereof typically occurs during this air exposure.

In the embodiments disclosed herein, a continuous hydrogenation and nitridation process, or a single step hydrogenation and nitridation process, is employed to enable the formation of metal gate structures with reduced EOT compared to similar structures formed by conventional methods. The plasma hydrogenation process and subsequent plasma nitridation process are performed in the metal nitride layer in the film stack, thereby removing, in some embodiments, O atoms disposed within the film stack layer, and in some embodiments reducing Oxygen-containing interfacial layers disposed within the film stack are minimized or prevented from thickening, and in some embodiments, N atoms are added to the film stack layers. Consequently, the EOT of the metal gate structure is reduced with little or no concomitant flat-band voltage shift. Additionally, the metal gate structures operate with increased leakage currents that are as low as one-fourth the increase in leakage current associated with similar metal gate structures formed via conventional techniques.

Although the foregoing relates to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from its essential scope, which is determined by the scope of the following claims.

100: Conductive structure 101: Source or drain structure 102: first metal layer 103: Metal nitride layer 104: Overlay 105: Silicide 106: Conductive layer 109: Contact Well 110: Semiconductor substrate 120: Insulation material 200: part 201: Surface 211: Host O atom 212: Surface O atom 213: vacancy 310: XPS Spectrum 320: XPS Spectrum 400: Plasma Processing Chamber 404: Substrate support base 406: Chamber Wall 408: Chamber cover 410: Induction Coil Elements 412: The first impedance matching network 414: RF Power 416: Electrical Ground 417: Electrical Ground 418: Shield electrode 419: Electrical ground 420: switch 422: Detector 424: Second Impedance Matching Network 426: Bias power supply 428: Substrate 430: Gas Panel 432: Entry port 434: Gas mixture 436: Plasma 438: Throttle valve 440: Vacuum Pump 442: Gas Source 444: Gas Pipeline 446: Controller 448: central processing unit (central processing unit; CPU) 450: memory 452: Support circuit 500: Multi-chamber processing system 506: Passing Chamber 508: Buffer chamber 510: Single Wafer Load Gate 512: Single Wafer Load Gate 513: Heating element 514: Processing Chamber 516: Processing Chamber 518: Processing Chamber 520: Processing Chamber 522: Processing Chamber 523: Preheat chamber 524: Processing Chamber 525: Preheat chamber 526: Robot 528: Robot 530: Computer Systems 600: Method 601: Steps 603: Step 604: Step 605: Steps 701: Surface 703: Plasma-Excited Nitrogen Species 800: Method 801: Steps 802: Steps 803: Steps 804: Steps 805: Steps 900: Method 901: Steps 902: Steps 903: Steps 905: Steps 1000: Metal gate structure 1001: Semiconductor substrate 1002: Interface Layer 1003: High-K dielectric layer 1003A: Thickness 1004A: Thickness 1004: Metal Nitride Overlay 1005: Metal gate electrode layer 1009: Interface Layer 1100: Method 1101: Steps 1102: Steps 1103: Steps 1104: Steps 1105: Steps 1106: Steps 1107: Steps 1121: Steps 1122: Steps 1123: Steps 1131: Steps 1132: Steps 1133: Steps 1134: Steps 1135: Steps 1136: Steps 1201: Surface exposed 1202: Sacrificial Silicon Layer 1203: Sacrificial Silicon Layer 1205: Surface exposed 1300: Method 1301: Steps 1302: Steps 1303: Steps 1304: Steps 1305: Steps 1306: Steps 1307: Steps 1321: Steps 1322: Steps 1323: Steps 1331: Steps 1332: Steps 1333: Steps 1334: Steps 1335: Steps 1336: Steps 1401: Surface 1404: Overlay 1404f: Final overlay 1409: Interface Layer

In order to enable a detailed understanding of the manner in which the above-described features of the disclosure are used, a more specific description of the disclosure, briefly summarized above, can be made with reference to embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the appended drawings illustrate only common embodiments of the present disclosure and are therefore not to be considered limiting of its scope, for the present disclosure may admit to other equally effective embodiments.

FIG. 1 shows a cross-sectional view of a contact structure formed on a substrate as part of a semiconductor element according to an embodiment of the present disclosure.

FIGS. 2A-2E are schematic diagrams of metal nitride layers within the contact structure of FIG. 1 at various stages of fabricating the contact structure, according to an embodiment of the present disclosure.

FIG. 3 is an X-ray Photoelectron Spectroscopy (XPS) spectrum 310 for a TiN film deposited and thermally annealed before processing and for the same after processing, according to an embodiment of the present disclosure. XPS spectrum 320 of a deposited and thermally annealed TiN film.

4 is a cross-sectional side view of a processing chamber configured to implement one or more aspects of the present disclosure.

5 is a top plan view of a multi-chamber processing system configured to implement one or more aspects of the present disclosure.

Figure 6 illustrates a flow diagram of process steps for reducing bulk and interfacial oxygen in contact structures in accordance with some embodiments of the present disclosure.

FIGS. 7A-7E are schematic cross-sectional views of a semiconductor device corresponding to different stages of the process of FIG. 6 according to various embodiments of the present disclosure.

8 illustrates a flow diagram of process steps for reducing bulk and interfacial oxygen in contact structures in accordance with some embodiments of the present disclosure.

Figure 9 illustrates a flow diagram of process steps for reducing bulk and interfacial oxygen in contact structures in accordance with some embodiments of the present disclosure.

FIG. 10 shows a cross-sectional view of a metal gate structure formed in accordance with an embodiment of the present disclosure.

11 illustrates a flow diagram of process steps for reducing effective oxide thickness (EOT) in metal gate structures in accordance with various embodiments of the present disclosure.

FIGS. 12A to 12J are schematic cross-sectional views of semiconductor devices corresponding to different stages of the process of FIG. 11 according to various embodiments of the present disclosure.

13 illustrates a flow diagram of processing steps for processing a metal gate structure with a single-step hydrogenation and nitridation process in accordance with various embodiments of the present disclosure.

FIGS. 14A to 14J are schematic cross-sectional views of semiconductor devices corresponding to different stages of the process of FIG. 13 according to various embodiments of the present disclosure.

To facilitate understanding, the same reference numerals have been used, where possible, to identify the same elements that are common to the figures. It is contemplated that elements and features of one embodiment may be advantageously incorporated in other embodiments without further recitation.

Domestic storage information (please note in the order of storage institution, date and number) none

Foreign deposit information (please mark in the order of deposit country, institution, date and number) none

1000: Metal gate structure

1001: Semiconductor substrate

1002: Interface Layer

1003: High-K dielectric layer

1401: Surface

1404: Overlay

1409: Interface Layer

Claims (17)

A method of forming a structure in a semiconductor device, the method comprising: depositing a metal nitride layer on a high-k dielectric layer formed on a semiconductor substrate to form a portion of the structure, wherein the semiconductor substrate is disposed over a substrate support surface of a pedestal disposed in a first processing chamber of a cluster tool; continuing an exposed surface of the deposited metal nitride layer formed on the semiconductor substrate exposure to a non-oxidizing plasma-excited hydrogen species, followed by exposure to a plasma-excited nitrogen species, while applying a bias voltage to the semiconductor substrate disposed on a substrate support surface of a pedestal, The pedestal is disposed in a second processing chamber of the cluster tool; a silicon-containing layer is deposited on the exposed surface; a thermal annealing process is performed on the silicon-containing layer; and the silicon-containing layer is removed. The method of claim 1, further comprising: after successively exposing the exposed surface to the non-oxidizing plasma-excited hydrogen species and the plasma-excited nitrogen species, in the exposed surface of the metal nitride layer A metal layer is deposited on the surface. The method of claim 2, wherein the structure includes a p-metal gate structure and the metal layer includes a work function metal of the p-metal gate structure. The method of claim 1, further comprising: forming a silicon dioxide-containing interface layer before depositing the high-k dielectric layer, and then forming the high-k dielectric layer on the silicon dioxide-containing interface layer constant dielectric layer. The method of claim 1, wherein the exposed surface is not exposed to air after exposing the exposed surface to the non-oxidizing plasma-excited hydrogen species and prior to exposing the exposed surface to the plasma-excited nitrogen species. The method of claim 1, before depositing the metal nitride layer on the high-k dielectric layer, further comprising: depositing a sacrificial metal nitride layer on the high-k dielectric layer; depositing a silicon-containing layer on the sacrificial metal nitride layer; performing a thermal annealing process on the sacrificial metal nitride layer and the silicon-containing layer; and removing the sacrificial metal nitride layer and the silicon-containing layer. The method of claim 1, further comprising exposing a surface of a processing chamber to an oxygen-free plasma prior to exposing the exposed surface to the non-oxidizing plasma excited hydrogen species. The method of claim 7, wherein the oxygen-free plasma is formed in the processing chamber when the semiconductor substrate is not disposed in the processing chamber. The method of claim 1, further comprising continuously exposing the exposed surface to the non-oxidizing plasma-excited hydrogen species followed by exposure to the plasma-excited nitrogen species in air. A method of forming a structure in a semiconductor device, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate, wherein the semiconductor substrate is disposed over a base; depositing a metal nitride layer on top of the layer; exposing an exposed surface of the metal nitride layer to a non-oxidizing plasma-excited hydrogen species, followed by exposure to a plasma-excited nitrogen species, while biasing a applying to the base; exposing the exposed surface to air after successively exposing the exposed surface to the non-oxidizing plasma-excited hydrogen species, followed by exposure to the plasma-excited nitrogen species; and exposing the exposed surface to air After the exposed surface is exposed to air, the high-k dielectric layer and the metal nitride layer are annealed. The method of claim 10, after performing annealing of the high-k dielectric layer and the metal nitride layer, depositing a metal layer on the exposed surface of the metal nitride layer. The method of claim 10, wherein the non-oxidizing plasma excited hydrogen species is produced from a process gas, the process gas comprising hydrogen gas ( _H2 ). The method of claim 10, wherein the metal nitride layer has a thickness that is less than a diffusion length of oxygen in the metal nitride layer when the metal nitride layer is annealed. A method of forming a structure in a semiconductor device, the method comprising: depositing a high-k dielectric layer on a semiconductor substrate, wherein the semiconductor substrate is disposed on a base of a processing chamber; depositing a metal nitride layer on the dielectric constant dielectric layer to form part of the structure while applying a bias to the base of the processing chamber; and continuing by an exposed surface of the metal nitride layer Exposure to a non-oxidizing plasma-excited hydrogen species followed by exposure to a plasma-excited nitrogen species reduces a first effective oxide thickness of the metal nitride layer to a second effective oxide thickness, wherein The non-oxidizing plasma excited hydrogen species is made from a process gas comprising hydrogen ( _H2 ) and the plasma excited nitrogen species is made from a process gas comprising nitrogen ( _N2) ) and ammonia (NH ₃ ). The method of claim 14, wherein the exposed surface is not exposed to air after exposing the exposed surface to the non-oxidizing plasma-excited hydrogen species and prior to exposing the exposed surface to the plasma-excited nitrogen species. The method of claim 12, further comprising: performing an oxygen-free plasma processing process on a processing chamber prior to exposing the exposed surface to the non-oxidizing plasma-excited hydrogen species, the processing chamber In the chamber, the exposed surface is exposed to the non-oxidizing plasma excited hydrogen species. The method of claim 16, wherein the oxygen-free plasma processing process is performed on the processing chamber when the semiconductor substrate is not disposed in the processing chamber.

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