TWI774808B - Fet operational temperature determination by resistance thermometry - Google Patents

Abstract

Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Description

FET operating temperature measurement using resistance thermometry

The present technology relates to field effect transistors with internal temperature sensing components.

Among III-V semiconductor materials, gallium nitride (GaN) has received considerable attention in recent years due to its ideal electronic as well as electro-optical properties. Gallium nitride (GaN) has a wide and direct energy gap of about 3.4 eV, is more resistant to avalanche effects, and has a higher intrinsic field strength than more common semiconductor materials such as silicon. As a result, GaN retains its electrical properties at higher temperatures than other semiconductors such as silicon or gallium arsenide. Compared to silicon, GaN also has a higher current-carrying saturation velocity. In addition, GaN has a wurtzite crystal structure, is a hard material, has high thermal conductivity, and has a higher melting point than other conventional semiconductors such as silicon, germanium, and gallium arsenide.

Due to its desirable properties, GaN can be used in high-speed, high-voltage and high-power applications, as well as optoelectronic applications. For example, gallium nitride materials can be used in active circuit components in semiconductor amplifiers such as Doherty amplifiers for radio frequency (RF) communications, radar and microwave applications. In high power applications, GaN transistors can be driven close to their performance limits and can heat up to temperatures well in excess of 120ºC. Excessive temperatures can lead to premature degradation and/or failure of GaN transistor devices, as is the case in other semiconductor transistors.

Structures and methods for sensing the operating temperature of a transistor are described herein. Thermal structures can be formed in the transistor and used to assess the operating temperature of the transistor by sensing changes in resistance of the thermal structure, eg, using metal resistance thermometry (MRT). In some embodiments, the source field plate and/or gate structure of a field effect transistor (FET) can be used as a thermally sensitive structure and is modified so that in the region of the source field plate and/or gate structure, applying Probe current or current. A voltage may be generated over the entire area due to the applied current. The voltage can be monitored to sense temperature changes in the FET region adjacent to the thermally sensitive structure.

Some embodiments relate to a field effect transistor with temperature sensing, comprising a gate, a source contact, a drain contact, a source field plate coupled to the source contact, connected to the source field plate and with a first a first pair of contact pads spaced apart for applying a probe current through the source field plate and a second pair of contact pads connected to the source field plate and spaced a second distance for inducing a probe current to flow through voltage on the area of the source field plate.

In some aspects, the source field plate covers at least a portion of the gate. In some cases, the source field plate exhibits a change in resistance when the temperature of the source field plate changes by not less than 0.001 ohms/ºC. According to some embodiments, the source field plate is AC coupled to the source contact.

In some embodiments, the first pair of contact pads includes a first thin film resistor and a second thin film resistor. The resistance of the first thin film resistor and the second thin film resistor may be between 300 ohms and 5000 ohms. In some embodiments, the second pair of contact pads includes a third thin film resistor and a fourth thin film resistor. The resistance of the third thin film resistor and the fourth thin film resistor may be between 300 ohms and 5000 ohms.

According to some aspects, the temperature-sensing field effect transistor may further include a probe current source connected to the first pair of contact pads. The probing current source can be configured to provide alternating current. In some cases, the alternating current has a frequency between 50 kHz and 5 megahertz.

According to some embodiments, the FET with temperature sensing may further include voltage sensing circuitry connected to the second pair of contact pads. A voltage sensing circuit can provide an output signal to a feedback circuit that controls the power level of the field effect transistor.

In some aspects, the temperature-sensitive field effect transistor is incorporated into a power amplifier configured to amplify the signal to a power level of no less than 0.25 watts. In some cases, the amplified power level may be a value between 0.25 watts and 150 watts.

In some cases, the temperature-sensitive field effect transistor further includes an active region controlled by a gate, wherein the active region includes GaN, GaAs (gallium arsenide), or InP (indium phosphide). According to some embodiments, the active region includes silicon (Si). In some embodiments, the field effect transistor may be an LDMOS FET, MOSFET, MISFET, or MODFET. In some cases, the field effect transistor may be a HEMT, HFET, or pHEMT.

Some embodiments relate to methods of operating transistors with temperature sensing. A method of operating a field effect transistor may include the actions of applying a signal to a gate of the field effect transistor; amplifying the signal with the field effect transistor; applying a probe current to a region of a source field plate of the field effect transistor, wherein The source field plate is coupled to the source contact of the field effect transistor; and senses a voltage generated by the probe current.

A method may further include the act of evaluating the peak temperature of the field effect transistor from the sensed voltage. The act of evaluating may include using calibration results associated with the field effect transistor.

In some aspects, a method may further include the acts of comparing the sensed voltage to a reference value; and controlling the power level of the field effect transistor based on the comparison.

In some embodiments, the act of applying the probe current includes applying the probe current along a region of the source field plate that covers at least a portion of the gate.

In some cases, the act of applying the probe current includes applying an alternating current in the region. According to some aspects, the act of applying the alternating current may include applying the alternating current at a first frequency that is not less than 10 times different from the frequency of the signal amplified by the field effect transistor.

According to some embodiments, the act of applying the probe current may include intermittently applying the probe current in the region such that the probe current is driven at time intervals that are not driven by the probe current in the region of the source field plate other time intervals.

Some embodiments relate to a temperature-sensitive field effect transistor (FET) including a gate, a floating gate plate adjacent to the gate and having an extended length, a source contact, a drain contact, and a connection to the floating gate a first pair of contact pads and a first pair of contact pads separated by a first distance for applying a detection current through the floating gate plate. The FET may also further include a second pair of contact pads connected to the floating gate plate and separated by a second distance for sensing a voltage on the area of the floating gate plate through which the detection current flows.

In some aspects, the floating gate plate covers at least a portion of the gate. The floating gate plate can exhibit a change in resistance when the temperature of the floating gate plate changes by not less than 0.001 ohm/ºC.

In some cases, the first pair of contact pads includes a first thin film resistor and a second thin film resistor. The resistance of the first thin film resistor and the second thin film resistor may not be lower than 300 ohms. In some embodiments, the second pair of contact pads includes a third thin film resistor and a fourth thin film resistor. The resistance of the third thin film resistor and the fourth thin film resistor may not be lower than 300 ohms.

Some embodiments of the FET may further include a probe current source connected to the first pair of contact pads. The probing current source can be configured to provide alternating current. In some cases, the frequency of the alternating current may be between 50 kHz and 5 megahertz.

According to some aspects, the FET may further include voltage sensing circuitry connected to the second pair of contact pads. The voltage sensing circuit can provide an output signal to a feedback circuit that controls the power level of the field effect transistor.

In some applications, the field effect transistor may be incorporated into a power amplifier configured to amplify a signal to a power level of no less than 0.25 watts. The FET of this embodiment may further include an active region controlled by a gate, wherein the active region includes GaN, GaAs, or InP. The FET of this embodiment may further include an active region controlled by a gate, wherein the active region includes Si. In some implementations, the FET of this embodiment may be an LDMOS FET, a MOSFET, a MISFET, or a MODFET. In some cases, the FETs of this embodiment may be HEMTs, HFETs, or pHEMTs.

Some embodiments relate to methods of operating field effect transistors that use floating gate plates to sense transistor temperature. A method may include the actions of applying a signal to a gate of a field effect transistor; amplifying the signal with the field effect transistor; applying a probe current along an area of a floating gate plate of the field effect transistor, wherein the floating gate plate covers at least a portion of the gate; and sensing a voltage generated by the detection current.

In some embodiments, a method may further include the act of evaluating the peak temperature of the field effect transistor from the sensed voltage. The act of evaluating may include using calibration results associated with the field effect transistor. A method may also include the act of comparing the sensed voltage with a reference value and controlling the power level of the field effect transistor based on the result of the comparison.

In some aspects, the act of applying the probe current can include applying the probe current along a region of the floating gate plate that covers at least a portion of the gate. In some cases, the act of applying the probe current may include applying an alternating current to the region. The action of applying the alternating current may include applying the alternating current at a first frequency, and the first frequency is not less than 10 times different from the carrier frequency of the signal amplified by the field effect transistor. In some embodiments, the act of applying the probe current may include intermittently applying the probe current to the region such that the probe current is driven at time intervals that are not driven by the probe current in the region of the floating gate plate other time intervals.

Some embodiments relate to a temperature-sensitive field effect transistor including a gate metal having an extended length, the gate metal having a first end and an opposing second end, a source contact, a drain contact, a A first contact pad connected to the gate metal at the first end for applying an AC probe current to the gate metal, a capacitor and a resistor connected in series between the reference potential and the end region of the gate metal remote from the first end A device, and a pair of contact pads connected to separate regions of the gate metal to induce a voltage drop along the gate metal in response to the AC probe current.

In some embodiments, the gate metal may exhibit a change in resistance when the temperature of the gate metal changes by no less than 0.001 ohms/°C.

Some embodiments may further include a probe current source connected to the first contact pad. The frequency of the AC probe current may be between 50 kHz and 5 megahertz.

In some cases, the FET may include voltage sensing circuitry connected to a pair of contact pads. A voltage sensing circuit can provide an output signal to a feedback circuit that controls the power level of the field effect transistor.

According to some aspects, the field effect transistor of this embodiment may be incorporated into a power amplifier configured to amplify a signal to a power level of no less than 0.25 watts. The FET of this embodiment may further include an active region controlled by a gate metal, wherein the active region includes GaN, GaAs, or InP. In some cases, the FET of this embodiment may further include an active region controlled by a gate metal, wherein the active region includes Si. According to some embodiments, the field effect transistors may be LDMOS FETs, MOSFETs, MISFETs, or MODFETs. In some cases, the field effect transistor may be a HEMT, HFET, or pHEMT.

Some embodiments relate to a method of operating a field effect transistor that uses a gate metal to sense temperature. A method may include the acts of applying a signal to a gate metal of a field effect transistor; amplifying the signal with the field effect transistor; applying an alternating detection current to a first end region of the gate metal of the field effect transistor, wherein The second end region of the gate metal is remote from the first end region and is terminated by a capacitor and a resistor connected in series between the reference potential and the second end region; and induced by an alternating current probe current along the gate metal Voltage drop due to length.

According to some aspects, a method may further include an act of evaluating a peak temperature of a field effect transistor from the sensed voltage. A method may also include the act of comparing the sensed voltage with a reference value and controlling the power level of the field effect transistor based on the result of the comparison.

In some cases, the act of applying the AC detection current may include applying the AC detection current at a first frequency that is not less than 10 times different from the carrier frequency of the signal. According to some embodiments, the act of applying the AC probe current may include intermittently applying the AC probe current to the first end region such that the AC probe current is driven at time intervals that are not interrupted along the length of the gate metal. The AC probe current is driven apart by other time intervals.

Some embodiments relate to a temperature-sensitive field effect transistor including a gate metal having an extended length, the gate metal having a first end and a second end, a source, a drain, and proximate the first end a first contact pad connected to the first end region of the gate metal and configured to apply an alternating detection current to the gate metal, wherein no other contact pads are connected to the gate metal for conducting the detection current , and wherein substantially all of the probe current is coupled to the field effect transistor source after application.

In some embodiments, the FET may further include a pair of contact pads connected to separate regions of the gate metal for inducing a voltage drop along the gate metal in response to the AC probe current. In some cases, the voltage sensing circuitry may be connected to a pair of contact pads. According to some aspects, the voltage sensing circuit can provide an output signal to a feedback circuit that controls the power level of the field effect transistor.

In some cases, the gate metal can exhibit a change in resistance when the temperature of the gate metal changes by not less than 0.001 ohms/ºC.

According to some aspects, the frequency of the AC probe current may be between 50 kilohertz and 5 megahertz. In some cases, the FET of this embodiment may be incorporated into a power amplifier configured to amplify a signal to a power level of no less than 0.25 watts. The FET of this embodiment may further include an active region controlled by a gate, wherein the active region includes GaN, GaAs, or InP. The FET of this embodiment may further include an active region controlled by a gate metal, wherein the active region includes Si. In some cases, the field effect transistors may be LDMOS FETs, MOSFETs, MISFETs, or MODFETs. In some aspects, the field effect transistor can be a HEMT, HFET, or pHEMT.

Some embodiments relate to a method of operating a field effect transistor that uses a gate metal to sense temperature. A method may include the acts of applying a signal to a gate metal of a field effect transistor; amplifying the signal with the field effect transistor; A probe current is coupled to the source of the field effect transistor; and a voltage drop is induced along the length of the gate metal by the AC probe current.

In some embodiments, a method may further include the act of evaluating the peak temperature of the field effect transistor from the sensed voltage. A method may also include the act of comparing the sensed voltage with a reference value and controlling the power level of the field effect transistor based on the result of the comparison.

In some cases, the act of applying the AC detection current may include applying the AC detection current at a first frequency that is not less than 10 times different from the carrier frequency of the signal. According to some embodiments, the act of applying the AC probe current may include intermittently applying the AC probe current to the region such that the AC probe current is driven at time intervals that are free from the AC probe current in the region of the gate metal. The other time intervals that are driven are spaced apart.

The foregoing apparatus and method embodiments may be implemented using any suitable combination of the aspects, features, and acts described in further detail above or below. These and other aspects, embodiments, and features of the teachings herein can be more fully understood from the description in conjunction with the accompanying drawings.

Those skilled in the art will understand that the drawings described herein are for illustration purposes only. It should be understood that, in some instances, various aspects of the embodiments may be exaggerated or shown enlarged in order to facilitate the understanding of the embodiments. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles taught in the present case. In the drawings, like reference numerals generally refer to the same features, similar functions, and/or structurally similar elements throughout the various figures. Where the drawings relate to microfabricated circuits, only a single element and/or circuit may be shown to simplify the drawing. In fact, a large number of components or circuits can be fabricated in parallel on a large area of a substrate or an entire substrate. Furthermore, the depicted elements or circuits may be integrated into larger circuits.

When referring to the drawings in the following detailed description, the spatial references "top," "bottom," "upper," "lower," "vertical," "horizontal," "above," "below," etc. may be used. Such references are used for teaching purposes and are not intended as absolute references to elements of the implementation. Elements of an implementation may be spatially oriented in any suitable manner, which may be different from that shown in the figures. The drawings are not intended to limit the scope of the present teachings in any way.

High electron mobility transistors (HEMTs) are semiconductor transistors that utilize two-dimensional electron gas (2DEG) for carrier transport. 2DEG is formed at a heterojunction between two different semiconductor materials with different energy gaps. The heterojunction results in the formation of spatially thin potential wells that collect the high-density electrons that form the 2DEG. In general, 2DEGs are formed in undoped semiconductors. Due to the lack of dopants (acting as impurities), free electrons can pass through the undoped semiconductor with greatly reduced scattering. Consequently, HEMTs can operate at very high frequencies, eg, deep into the megahertz frequency range, and are suitable for radar, microwave, and RF communications applications. HEMTs formed using gallium nitride or gallium arsenide materials can also be used for high power applications. During high power operation, the transistor may heat up to high temperatures (eg, over 120ºC), and it may be necessary to know the maximum temperature reached by the transistor and/or monitor the temperature of the transistor when put into use in a particular application.

According to some embodiments, although aspects of the invention are not limited to HEMT transistors, an exemplary HEMT structure to which temperature-sensing aspects can be applied is shown in FIG . 1A . HEMT 100 may be formed as a lateral element and include source S, drain D, and gate G including gate metal 140 . The gate metal 140 may have a length L _g and control the current flow between the drain D and the source S. According to some embodiments, the gate length L _g may be between about 0.1 microns and about 3.0 microns. The gate, source, and drain can be formed on the same side of the substrate 105 (eg, on the treated surface of the substrate). The advantage of the lateral HEMT structure is that no through-substrate vias are required for connection to the source or drain of the element, which makes the entire backside of the element available for heat dissipation. Single-sided electrical connections also make integrating HEMTs into integrated circuits (ICs) an easier task.

In some embodiments, electrical isolation regions 115 may be formed around the source and drain to improve element isolation and reduce leakage current. The isolation region 115 may be formed by ion implantation, which may damage the crystal structure, thereby increasing its resistance to leakage current.

According to some embodiments, HEMT 100 may include a multilayer structure including substrate 105 , buffer layer 112 , conductive layer 114 in which 2DEG 150 is formed, barrier layer 116 , and at least one electrically insulating dielectric layer 120 . Some embodiments may or may not include semiconductor capping layer 118 , which may be formed of the same material as conductive layer 114 . The HEMT may also include a source contact 160 connected to the source deposition 130 and a drain contact 162 connected to the drain deposition 132 .

In some embodiments, HEMT 100 may also further include at least one gate-connected field plate 145 that is electrically connected to gate metal 140 and extends beyond the edge of gate metal 140 . In some cases, gate-connected field plate 145 and gate metal 140 may be formed from the same metal deposited in the same deposition step (eg, T-gate structure). According to some embodiments, the gate metal 140 may be located closer to the source deposition 130 than the drain deposition 132, although in some cases the gate may be located between the source and drain deposition, or in other embodiments located closer to the drain. In some embodiments, an insulating passivation layer (not shown) may be formed over the gate-connected field plate 145 and the source and drain contacts 160 , 162 .

One or more HEMTs 100 may be arranged on a die for operation together, as shown in the plan view of FIG. 1B or FIG . 1C . Other configurations are possible, and multiple transistors can be connected in the circuit that operate on separate signals. In some implementations, the source, gate, and drain of the transistor may have extended lengths in one direction (eg, the width direction _Wg ) and extend parallel to each other, as depicted in FIG . 1B . In some embodiments, the HEMT may be included between the gate or gate connection field plate 145 and the gate contact pad 185, the source contact 160 or the source field plate (not shown in Figures 1A -1C ) Conductive leads 170 (eg, interconnects patterned during metallization levels) extend between source contact pad 180 and between drain contact 162 and drain contact pad 182 . For example, as shown in Figure 1C , when a transistor is repeated multiple times on a substrate in an array, the drain contact 162 may be shared between two adjacent transistors, and the source contact 160 Can be shared between two adjacent transistors. In other configurations, there may be only one of source contact 160 or drain contact 162 between two adjacent extended gates (sometimes referred to as gate fingers) in the array, and the source and drain contacts may alternate along the array such that source contact 160 and drain contact 162 in each array are common to two adjacent gates in the array.

Although the details of HEMTs are described in connection with the various embodiments described herein, the invention is not limited to HEMT elements. Embodiments may be used on other field effect transistors such as, but not limited to, junction FET (JFET), metal oxide semiconductor FET (MOSFET), metal-insulator-semiconductor FET (MISFET), metal-semiconductor FET (MESFET), Modulation doped FET (MODFET), heterostructure FET (HFET), and pseudo-shaped HEMT (pHEMT), etc. Furthermore, the present invention is not limited to gallium nitride materials. Transistors of the type described above may have an active region of semiconductor controlled by a gate, which may use any suitable semiconductor material or for example, but not limited to, silicon (Si), germanium (Ge), silicon carbide (SIC), gallium arsenide (GaAs), indium phosphide (InP), cadmium telluride (CdTe) and other materials.

As used herein, the term "gallium nitride material" is used to refer to gallium nitride (GaN) and any alloy thereof, such as aluminum gallium nitride ( _{AlxGa (1-x) N} ), indium gallium nitride (Iny) Ga _(1-y) N), Aluminum Indium Gallium Nitride ( _AlxInyGa (1- _{xy )} N), Gallium Arsenide Phosphide Nitride ( _{GaAsxPyN (1} - _xy )N), Aluminum Indium Gallium Arsenic phosphorus nitride (Al _x In _y Ga _(1-xy) As _a P _b N _(1-ab) ) and the like. Generally, when present, arsenic and/or phosphorus are in low concentrations (ie, less than 5 weight percent). In certain preferred embodiments, the gallium nitride material has a high concentration of gallium and contains little or no aluminum and/or indium. In high gallium concentration embodiments, the sum of (x + y) may be less than 0.4 in some embodiments, less than 0.2 in some embodiments, less than 0.1 in some embodiments, or even less in other embodiments . In some cases, it is preferred that at least one layer of gallium nitride material has a composition of GaN (ie, x=y=a=b=0). For example, the active layer in which most of the current conduction occurs may have a composition of GaN. The gallium nitride material in the multilayer stack may be n-type or p-type doped, or may be undoped. Suitable gallium nitride materials are described in US Patent No. 6,649,287, which is incorporated herein by reference in its entirety.

The drawings of the HEMT in Figures 1A , 1B and 1C are not drawn to scale. According to some embodiments, the contact pads may be substantially larger than shown in the figures, and may be substantially larger than the gate, source, and drain contacts. In some implementations, the extended gate metal 140 can be significantly narrower than the source and/or drain contacts. Although Figures 1A , 1B and 1C depict one or several HEMT elements, many elements may be formed on a die or wafer in various embodiments . For example, linear arrays of HEMTs can be fabricated on a semiconductor die to form power transistors. Due to their small size, it is possible to form hundreds or thousands of HEMTs on a die and thousands or millions of HEMTs on a wafer. The HEMTs described above or other types of transistors can be connected in different types of integrated circuits on the die, such as, but not limited to, amplifiers, current sources, signal switches, pulse generator circuits, power converters, special application integrated circuits ( ASICs) etc.

In applications such as radar, microwave, and RF communications, signal amplification or switching of high power levels often occurs. For example, amplifiers can amplify signals to power levels of tens or hundreds of watts for long-distance transmission. High power levels can result in heating within the amplifier transistor, which, if overheated, can lead to undesirable changes in device performance, premature aging, and/or device failure. The inventors have recognized and understood that heating is non-uniform within a field effect transistor and that a hot spot 155 typically occurs near the drain side of the gate ( FIG . 1A ). In some embodiments, the temperature in this region may exceed 160°C during FET operation. This elevated temperature accelerates FET aging and reduces mean time to failure (MTTF). It is believed that accelerated aging is due, at least in part, to an increased rate of compound formation at the material interface of the device. In some cases, prolonged periods of excessively high temperature may cause sudden component failure (for example, by reducing the component's resistance to high voltage failure).

To better understand heating in FETs, the inventors have conceived and implemented structures and methods for monitoring temperature within FETs using metal resistance thermometry (MRT). In some embodiments, thermally sensitive structures near gate metal 140 and/or the gate metal itself can be used to monitor FET temperature. In some embodiments, thermally sensitive structures may be coupled to gate metal 140 . In other embodiments, thermally sensitive structures may be connected or coupled to gate metal 160 . In some cases, the sensed temperature value may be used in a feedback model (paradigm) to control the operation of the FET in order to reduce the operating temperature of the FET.

Referring now to the front view of FIG . 2A , a HEMT is depicted in which a floating gate plate 147 has been formed adjacent to the gate metal 140 and the gate connection field plate 145. According to some embodiments, floating gate plates can be used as heat-sensitive structures in transistors. The HEMT may otherwise resemble the structure described in Figure 1A . Floating gate plate 147 may be isolated from gate metal 140 and gate-connected field plate 145 by insulating layer 122 (eg, an oxide layer or other dielectric layer). The floating gate plate 147 may extend along and cover a portion of the gate metal 140, or may cover the entire gate metal. In some cases, the floating gate plate 147 may be offset from the gate metal 140 toward the drain and may not cover the gate metal 140 nor the gate-connected field plate 145 . Alternatively, the floating gate plate 147 may cover a small portion of the gate metal 140 and/or a portion of the gate-connected field plate 145 . Biasing the floating gate plate 147 can reduce capacitive coupling between the gate metal and/or the field plates connected to the gate, and reduce adverse effects on transistor speed.

When the terms "on," "adjacent," or "over" are used to describe the position of a layer or structure, the layer being described may or may not have one or more layers of material between the layer described and the layer described above. On, adjacent to, or above the lower layer. When a layer is described as being "directly" or "immediately" on, adjacent to, or over another layer, there are no intervening layers present. When a layer is described as being "on" or "over" another layer or substrate, it can cover the entire layer or substrate, or a portion of both the layer and the substrate. The terms "on" and "above" are used to facilitate interpretation relative to the drawings and are not intended as absolute directional references. Elements can be fabricated and/or implemented in other orientations than shown in the figures (eg, rotated more than 90 degrees about a horizontal axis).

Plan views of various embodiments of the floating gate plate 147 are shown in Figures 2B and 2C . Other configurations of floating gate plate 147 are possible, and the invention is not limited to the layout pattern shown. When the FETs are formed in an array, such as shown in Figure 1C , a floating gate plate 147 can be formed on each transistor so that the temperature of each transistor can be independently monitored. Alternatively, the floating gate plate 147 may be formed on one (eg, one at or near the center of the array) or several transistors distributed along the array to sample one or more representative temperatures in the array.

According to some embodiments, the floating gate plate 147 (or floating gate) can be configured for use with a four-point probe, for example, so that four-terminal Kelvin resistance measurements can be made. In some cases, there may be two pairs of conductive contact pads 210a , 210b , 212a , 212b that provide electrical connection to the floating gate plate 147 . According to some embodiments, the contacts in a pair of contact pads may be spaced apart (eg, in distal or opposite end regions of the thermally sensitive structure). In some embodiments, pairs of contact pads may not be located at the ends of the floating gate plate, and may be located at different points along the floating gate plate 147 . In the preferred case, at least two contact pieces (212a, 212b ) are spaced apart on the floating gate plate 147 by a distance D that is sufficient to measure along the floating gate plate 147 when the current is forced along the floating gate plate 147 change in voltage drop.

Contact pads 210a, 210b, 212a, 212b may be electrically isolated from interconnect 161, which provides electrical connections to gate metal 140, source contact 160, and drain contact 162. According to some embodiments, the contact pads 210a, 210b, 212a, 212b may be formed of the same material as the floating gate plate 147 and patterned at the same time. In other embodiments, the contact pads may be formed of a different material than the floating gate plate 147 and deposited in electrical contact with the floating gate plate during separate processing steps. In some cases, the contact pads may be formed as conductive interconnects.

In some embodiments, the gate plate 147 may not float, but rather be driven at one or more desired voltage values. Instead, gate metal 140 and gate-connected field plate 145 (if any) may be floating. In such an embodiment, the four-point probe may be connected to the floating gate metal 140 and/or the floating gate connected field plate 145, one or both of which may be used as thermally sensitive structures in the transistor.

In operation and as shown in Figure 2B , a probe current IP may be applied through the first pair of contact pads 210a, _210b on the thermally sensitive structure. The applied current can be DC current or AC current. The probe current _IP can be applied in the area of the floating gate plate 147 adjacent to the gate metal 140 (not visible in Figure 2B ) , or in the gate-connected field plate 145, if present below. While the probe current IP is applied, the second pair of contact pads (212a, _212b ) can be used to monitor the voltage _Vs across at least a portion of the area where the current flows. From the measured voltage V _S and the known value of the applied current IP, the resistance value R _{S of} the detection area of the thermally sensitive structure can be confirmed. According to some embodiments, the amount of probe current applied may be between 200 microamps and 10 milliamps.

Many metals or materials for gate metal, gate field plate (connected or coupled), source contact, source field plate (connected or coupled) and drain contact have temperature sensitive R _S (T) The resistance. According to some embodiments, these metals or materials can be used for heat-sensitive structures in transistors. The temperature-dependent resistivity will be reflected in the measurement voltage V _S (T). Thus, monitoring the voltage V _S (T) of the microscale thermal structures within the FET can provide an indication of the FET's operating temperature, which is in the region near the gate and near the highest temperature region of the element.

Several materials may be used for the floating gate plate 147 or other heat sensitive structures described herein. A single metal or material layer may be used in some cases, or a multi-layer metal stack may be used in other cases. In some embodiments, non-metallic materials such as polysilicon may be used. Exemplary metal stacks that can be used include, but are not limited to, nickel/gold, nickel/gold/titanium, titanium/platinum/gold, titanium/gold, titanium/platinum/gold/titanium, nickel/palladium/gold/titanium, nickel/ platinum/gold/titanium, nickel/titanium/aluminum/tungsten, nickel/molybdenum/aluminum/tungsten, nickel/tantalum/aluminum/tantalum, nickel/tantalum/aluminum/tungsten, nickel/nickel monoxide/aluminum/tungsten, nickel/ Nickel monoxide/tantalum/aluminum/tantalum, nickel/nickel monoxide/tantalum/aluminum/tungsten, molybdenum/aluminum/tungsten, nickel/tungsten nitride/aluminum/tungsten, nickel/nickel monoxide/molybdenum/aluminum/tungsten, Nickel/Nickel Oxide/Tungsten Nitride/Aluminum/Tungsten, Tungsten Nitride/Aluminum/Tungsten, Platinum/Au/Titanium, Titanium/Platinum/Au, Aluminum/Copper, Nickel/Chromium, or Titanium Nitride/Copper. A single metal layer can be formed from any metal in such a multilayer stack.

In practice, the gate metal 140 can be driven at RF frequencies (eg, frequencies in excess of 500 MHz and up to 7 GHz) for use in communications applications. Higher frequencies may be used in other embodiments. In high frequency applications, it may be desirable to reduce unwanted coupling of the RF signal to circuitry connected to floating gate plate 147 or thermally sensitive structures (circuitry not shown in Figure 2B or Figure 2C ). According to some embodiments, coupling of the RF signal to the thermally sensitive structure and/or its circuitry may be reduced by adding a high impedance element 220 between the floating gate plate/thermally sensitive structure and the connecting circuitry. According to some embodiments, an inductor or a resistor or a combination thereof may be used as the high impedance element, although a capacitor may be used instead or in addition in embodiments where the applied probe current _IP is an AC current.

In some embodiments, the high impedance elements 220 (the four shown in Figure 2B ) comprise resistors, for example, thin film resistors. Thin film resistors may be formed from TaN, for example, polysilicon, or any other suitable material. The high resistive impedance element 220 may have a resistance value between 300 ohms and 2000 ohms. According to some embodiments, the resistance value may be between 500 ohms and 1500 ohms. In some cases, the thin film resistor or high impedance element 220 may be formed on the same die as the transistor to which temperature sensing is applied. In some cases, high impedance elements may be formed on separate dies (eg, packaged with transistors) or on a circuit board (eg, on which transistors are mounted) and electrically connected to floating Contact pads of gate plate 147, for example. In some cases, the high impedance element 220 may comprise discrete resistors, which may be mounted outside the packaged transistors containing the thermally sensitive structures. The package may include pins for connecting the resistors of the high impedance element 220 . Thin film resistive elements formed on the same die as the transistors may allow for smaller components than having external discrete resistors. Alternatively, external resistors can allow customers more design flexibility.

According to some embodiments, the contact pads 211a, 211b, 213a, 213b may be formed of thin film resistors, as shown in Figure 2C . Thin film resistors may be deposited and patterned before or after floating gate plate 147 . The resulting contact pads 211a, 211b, 213a, 213b can form a resistive contact to the floating gate plate 147 at one end and connect or provide a connection point to additional temperature sensing circuitry at the opposite end.

According to some embodiments, one example of temperature sensing circuitry 300 includes floating gate 147 formed on a transistor (not shown), as depicted in FIG . 3 . For example, temperature sensing circuitry 300 may include current source 310 and differential amplifier 320 . The temperature sensing circuitry may also include the high impedance element 220 described above and shown in FIG . 3 as resistors R1-R4. In some embodiments, the current source 310 may comprise an integrated current source formed of one or more transistors, for example. The current source 310 may be formed on the same die as the transistor and floating gate plate 147, or in some cases, may be formed on a separate die. For the embodiment depicted in FIG . 3 , current source 310 may be configured to provide DC current, and in other embodiments, may be configured to provide AC current.

The differential amplifier 320 may comprise an integrated circuit with multiple transistors (eg, two transistors in a parallel circuit branch with either their emitters or sources connected to a common current source). The differential amplifier can be configured to sense the potential difference between the two regions of the floating gate plate 147, as shown in FIG. According to some embodiments, the differential amplifier 320 may include operational amplifier circuitry that provides limited differential gain from the voltage induced between the two regions of the floating gate plate 147 . Differential amplifier 320 may be formed on the same die as transistor and floating gate plate 147, or may be formed on a separate die.

The output VM from differential amplifier 320 can be used to monitor changes in the _voltage drop across the area of floating gate plate 147 during transistor operation. As mentioned above, the monitored voltage Vs( _T ) varies with temperature and can provide an indication of the peak operating temperature of the transistor. In some implementations, the output voltage _VM may be processed to estimate and/or track the operating temperature of the FET. For example, _VM can be converted to temperature values as described herein, and the temperature values can be output as digital data and/or displayed visually on test equipment. In some cases, the temperature of the FET can be monitored during component testing to assess how well the FET operates when in use and/or to estimate the MTTF of the FET when in use. In some embodiments, the FET temperature can be monitored during a quality control process at the time of manufacture.

In other embodiments, the output voltage _VM may be provided to the comparator 330 to determine whether the FET is operating within predetermined temperature limits. For example, the output voltage VM can be compared with a predetermined reference voltage _{Vref to} generate the control signal _CS . A control signal can be fed back to control the operation of the transistor. For example, the control signal can be used to change the bias of the transistor, the voltage supply value and/or to change the variable attenuator on the input RF signal, thereby changing the operating power of the transistor to reduce the temperature or allow the temperature to rise. In other embodiments, other methods may be used to process _VM and generate control signal _CS .

Components other than floating gate plate 147 can be used as thermally sensitive structures in the FET, and other temperature sensing circuits can be used in other embodiments. Further embodiments are depicted in Figures 4 to 6B . In some embodiments, the gate metal or material 140 of the FET can be used to sense the FET temperature, as depicted in FIG . 4 . The inventors have recognized and understood that applying a DC current to the gate can adversely affect the biasing of the transistor, as doing so will introduce a bias gradient along the gate. Therefore, in addition to the gate bias _Vgs , the AC probe current _IP , _AC from the AC current source 410 can also be applied to the gate 140 of the transistor. According to some embodiments, the AC current source 410 may include an integrated oscillator and a current amplifier. The AC current source 410 may be integrated on the same die as the transistor implementing the temperature sensing, or on a separate die.

An RC shunt including capacitor C1 and resistor R2 may be connected to gate 140 to provide a path for AC detection current. The RC shunt may be connected to the gate at a region remote from the current source 410 where it is connected to the gate. To avoid interfering with the RF signal, the frequency at which the AC current is detected can be significantly lower than the frequency of the RF signal. For example, a characteristic frequency of an RF signal may be the carrier frequency used to transmit data in RF communications, or may be the carrier frequency of radar pulses used in radar applications.

In some embodiments, the frequency at which the AC current is detected may differ from the frequency of the RF signal by a factor of no less than 25. In some cases, the frequency at which the AC current is detected may differ from the frequency of the RF signal by a factor of not less than 10. Various probing AC frequencies can be used. For example, in some embodiments, the frequency of the detector current _IP may be about 1 megahertz. In some cases, the probing AC frequency may be a value between 50 kilohertz and 5 megahertz. Other embodiments may use probing AC frequencies with values no less than 10 Hz. Other embodiments may use probing AC frequencies with values as high as 10 or hundreds of megahertz. The RC shunt may include a low pass filter that provides a path to detect current but blocks high frequencies. In some embodiments, the values of C1 and R2 may be selected to provide a cutoff frequency of the RC _shunt that is approximately equal to or higher than the frequency of the probe current IP by 20%. AC voltage sensing circuitry 420 may be employed when AC detection current is used. In some embodiments, the AC voltage sensing circuitry may include an average peak voltage detector. The AC voltage sensing circuitry 420 may be integrated on the same die as the transistor implementing the temperature sensing, or on a separate die.

In some embodiments (eg, a test facility), one or both of the current sources 310, 410 and the voltage sensing circuits 320, 420 may be embodied as commercial instruments or stand-alone test equipment. In such cases, probes may be used to connect to contact pads or connected probe pads (not shown) on a die containing one or more transistors under test. Such embodiments can be used, for example, when testing or qualifying components at manufacture, and allow for smaller electrical transistor cores.

Figure 5 depicts another embodiment of a temperature sensing circuitry for a FET in which an AC probe current is applied to the gate metal 140 of the FET. In such an embodiment, an RC shunt may not be used, and there may be no contact pads at the distal end of the gate metal for detecting current flow. Instead, substantially all of the AC current _{IP , AC} may be coupled to the transistor, source contact 160 and/or source 130 ( as shown in this example). The probing current frequency can be selected to increase or maximize the flow of AC current probing the source, source contacts, and/or source field plate. The embodiment depicted in FIG . 5 includes the possibility of producing a smaller electrical transistor die or integral assembly than the embodiment shown in FIG . 4 .

Figure 6A depicts an embodiment in which the source field plate 660 may be used as a thermally sensitive structure for sensing temperature during operation of the FET. In these examples, although a HEMT is depicted, other types of FETs may be used. According to one example, a plan view of the element is shown in Figure 6B . According to some embodiments, source field plate 660 may be patterned to cover at least a portion of gate 140 and/or gate-connected field plate 145 . The source field plate 660 may be insulated from the gate and/or gate-connected field plates by the insulating layer 122 and connected to the source contact 160 by a conductive interconnect 665 . In some embodiments, conductive interconnect 665, source contact 160, and source field plate 660 may be formed simultaneously from the same layer of material (eg, during the same deposition process). In some embodiments, the conductive interconnects 665 may include thin film resistors as described above, which are patterned and deposited in a separate process step than the source field plate. For example, the inter-resistive connection 665 may provide a slight DC potential to the source field plate such that the AC probe current applied to the source field plate 660 is higher than the ground voltage.

In some cases, conductive interconnects 665 may be located near or at the ends of the source field plates, allowing the applied probe current to flow over most of the length of the source field plates 660 rather than being shunted near the middle of the source field plates. In some embodiments, the contact pads (eg, pad 210b in Figure 6B ) may be omitted, and the applied probe current may flow along most of the length of the source field plate 660 through the conductive interconnect 665 to the reference potential, the reference potential is connected to the source contact 160 of the transistor. In some cases, conductive interconnects 665 may include thin film resistors as described above, which reduce RF coupling to source contact 160 .

According to some embodiments, the source field plate 660 may be electrically floating. For example, there may be no direct current path between source field plate 660 and source contact 160 . In some cases, there may be one or more capacitive couplers 667 that capacitively couple the source field plate 660 to the source contact 160, as shown in Figure 6C . Capacitive coupler 667 may be formed from a conductive film that is separated from source contact 160 by an insulating layer (eg, an oxide layer or other dielectric). To improve the thermal sensing accuracy of the transistor's hot spot 155 (shown in Figure 6A ) by means of the floating gate source field plate, there may be a narrow conductive interconnect 665 connecting the capacitive coupler 667 to the source field plate 660.

In other embodiments, the source field plate 660 may extend all the way to and cover the source contact 160 to provide capacitive coupling with the source contact. In such an embodiment, the individual capacitive coupler 667 may not be present. Instead, source field plate 660 may be present as a single rectangular conductive film covering at least a portion of source contact 160 and at least a portion of gate 140 and/or gate-connected field plate 145 .

Using the source field plate 660 for thermal sensing of the FET instead of the gate 140 or gate-connected field plate 145 can have several benefits. The first benefit is that a portion of the source field plate 660 can be located in the vicinity of the hottest region 155 of the FET. In some implementations, the shape of the source field plate 660 may be limited to the area near the hot spot of the transistor, as depicted in Figure 6A . For example, the source field plate 660 may be limited to areas that do not overlap or partially overlap the gate metal 140 and do not extend more than a quarter of the distance from the gate-to-drain contact 162 . Another benefit is that the source field plate 660 can be electrically connected to the source with RF///DC isolation, with little or no perturbation to transistor performance. Otherwise, such perturbations may occur when currents and voltages for sensing temperature are applied to the gate metal 140 of the transistor or the field plate 145 of the gate connection.

Another benefit of using the source field plate 660 for temperature sensing for certain FET types is that problems associated with leakage of probe currents applied to the transistor gates can be avoided. In some FETs, the probe current applied to the gate metal of the transistor may leak into the AC current path (eg, to the source of the transistor). Such leakage can be temperature dependent and result in an inaccurate assessment of component temperature over a range of temperatures. Conversely, the source field plate 660 may have better isolation than the gate and may reduce _leakage of the probe current IP during temperature sensing.

Although the use of a source field plate may be preferable in some cases, some embodiments may use gate metal 140 and/or gate-connected field plate 145 for thermal induction. In other embodiments, separate temperature sensing circuits in the same transistor may use gate metal or gate and source field plates. Two temperature sensing circuits with two thermally sensitive structures may be employed to provide redundancy and/or measurement confirmation. In some embodiments, two temperature sensing circuits can be used to evaluate thermal gradients in the FET and to better estimate the peak temperature of the element based on the thermal gradients.

It is also beneficial to use the heat sensitive structures described above. For example, existing FET structures and materials (with only minor modifications) can be used to sense FET temperature. Additionally, the thermally sensitive structures can be microscale and located near the hot spot 155 of the FET, so that an improved local estimate of the peak temperature of the FET can be obtained. In some embodiments, the thermally sensitive structure may have a length in the gate length direction that is anywhere between 0.2 microns and 5 microns. The width of the thermally sensitive structure may be approximately equal to the width of the FET gate, and may be between 1 micron and 1 millimeter. The thickness of the thermally sensitive structures may be between 50 nanometers and 2 micrometers. In other embodiments, other dimensions may be used for thermally sensitive structures.

According to some embodiments, one or more FETs on a die or wafer may be used to calibrate the temperature sensitivity of thermally sensitive structures (gate metal, gate-connected field plates, source field plates) in the FETs. For example, when the source, gate, and drain contacts of a FET are left to float, a die or wafer can be placed on a hot plate and heated over a range of temperatures. The wafer or die can be allowed to thermally equilibrate at each temperature before making resistance measurements. The resistance measurement may include applying a probe current _IP and inducing a voltage drop V _S (T) over the area of the thermally sensitive structure in which the probe current flows. The result of such a calibration might look like Figure 7 .

The data in Figure 7 was obtained with an exemplary HEMT device using a metal source field plate as the thermally sensitive structure. The graph shows the resistance value (calculated from applied current and measured voltage drop) plotted as a function of substrate temperature. In this exemplary device, the resistance of the thermally sensitive structure varies by approximately 0.006 ohms/°C with respect to changes in temperature of the structure. Other embodiments with different materials may have different thermal sensitivities. In some cases, the thermal sensitivity may be between 0.001 ohms/ºC and 0.05 ohms/ºC. In other cases, the thermal sensitivity of the thermally sensitive structure may have a lower or higher value than this range.

The graph of Figure 7 can be used to evaluate the temperature of the same FET element (or similar FET element containing the same thermal structure) that is probed during operation of the element. As an example, a calibration equation (eg, the equation used to fit a line to the data in the points in Figure 7 ) or a look-up table can be determined from the measurement data and used to convert subsequently measured resistance values to temperature.

Although resistance values are plotted in Figure 7 , other embodiments may use other values. In some cases, voltage may not be converted to resistance. Instead, the measured voltage can be plotted as a function of substrate temperature, and the voltage value can be used directly to estimate the temperature of the same FET element probed during element operation. In other cases, the sheet resistance (ohms/square) of a thermally sensitive structure can be determined and plotted as a function of temperature so that the results can be used to evaluate thermally sensitive structures of different shapes and/or sizes despite having the same sheet resistance temperature in the FET.

Use examples of calibration values, such as those obtained for the example in Figure 7 . Further description will be given in conjunction with Figures 8 and 9 . To generate the graph shown in Figure 8 , the HEMTs were operated at different power levels (0 to about 8 watts/mm), while the substrate supporting the HEMTs was sequentially set at five different temperatures. The resistance values plotted for each measurement shown in Figure 8 are confirmed by the voltage drop _VS ( _T ) measured across the area of the source field plate and the applied probe current IP.

After finding the resistance value (depicted in Figure 8 ) under different operating conditions, the measured resistance of Figure 8 can be converted to a temperature value using the calibration value of Figure 7 (or the resulting calibration equation or checklist) . The corresponding temperature values are plotted in Figure 9 as an example of data conversion using calibration data.

The slope of each line in Figure 9 represents the thermal resistance of the thermally sensitive structure (source field plate) at different substrate operating temperatures. Plot the thermal resistance of exemplary components as a function of temperature in Figure 10 .

In packaged power transistors, a heat sink (eg, a thermally conductive plate) may be included to improve thermal conduction of heat away from the transistor. In some cases, there may be more than one heat sink. In some cases, the heat sink may be included in the power transistor package. In some embodiments, there may be additional or alternative heat spreaders outside the power transistor package to which the transistor package is assembled. Some embodiments may include a temperature sensor (eg, a thermistor) on the heat sink so that the temperature of the heat sink can be monitored during operation of the power transistor. Thus, embodiments similar to the data shown in Figures 8 and 9 can be used to estimate the operating temperature of the power transistor using the measured resistance value and the measured temperature of the heat sink in thermal contact with the power transistor.

It should be understood that the values plotted in Figures 7 to 10 are for exemplary elements only and for explanatory purposes only. Different values and calibration curves may be obtained for elements different from the sample element. The invention is not limited to the values and calibration data shown in these figures.

Methods of operating a FET in accordance with embodiments of the present invention provide techniques for sensing and evaluating the operating temperature of a FET. In some cases, the value of the sensed temperature can be used for feedback control of the FET. According to some embodiments, a method of operating a field effect transistor may include the acts of applying a signal to the gate of the field effect transistor, amplifying the signal with a FET, and in a sensitive structure region of the FET (eg, source field plate) A probe current is applied. The source field plate can be coupled to the source contact of the FET. A method may also include sensing a voltage resulting from the applied probe current. In some cases, the probe current may be applied to the gate, floating gate, gate field plate, or floating gate plate of the FET. In other cases, the probe current may be applied to at least two components of the FET's gate, floating gate, gate field plate or floating gate plate, and source field plate.

A method of operating a FET may include evaluating the temperature of the field effect transistor from the induced voltage, the temperature representing a local peak temperature near the gate of the transistor. Evaluation of temperature may include calibration results of thermally sensitive structures using field effect transistors. In some embodiments, the induced voltage may not be converted to temperature. Instead, the induced voltage can be used as an indicator of the temperature of the FET. For example, in some embodiments, a method of operating a FET may include the act of comparing the induced voltage to a reference value. In some cases, the power level of the FET may be controlled based on the comparison.

In some aspects of temperature sensing, a method may include applying a probe current along a region of a heat sensitive structure (eg, a source field plate or a floating gate plate) that covers at least a portion of the gate of the FET. In some cases, the act of applying the probe current includes applying an alternating current in the region. For some embodiments, applying the alternating current may include applying the alternating current at a first frequency that is not less than 25 times different from the carrier or characteristic frequency amplified by the field effect transistor.

In some embodiments, applying the probe current may include intermittently applying the current in the region such that the current is driven at time intervals that are separated by other time intervals in the region of the thermally sensitive structure where the probe current is not applied separated. Applying the probe current intermittently reduces power consumption and interference with FET operation. According to some embodiments, the detection current may be applied only during and/or immediately after the input signal rises above a predetermined power or voltage level. For example, a comparator may be connected to sense the input level applied to the gate 140 of the FET and activate the current sources 310, 410 in response to the input level exceeding or falling below a reference value. In this manner, temperature sensing may be performed only during and/or immediately after the transistor is processing a large input signal (eg, during and/or after a peak power interval).

Methods of operating FETs including temperature sensing may also include the act of amplifying a signal (eg, for communication systems, medical imaging equipment, or microwave applications) or switching voltage and/or current (eg, for power conversion applications, power generation, buffering circuit, or overvoltage/overcurrent protection). In power applications, FETs with thermal sensing can be used in power amplifiers, such as Doherty amplifiers, which amplify the signal to a power level of no less than 0.25 watts. In some embodiments, thermal induction can be used in power amplifiers that amplify signals to power levels in the range of no less than 0.5 watts and up to 150 watts. It should be understood that FETs with temperature sensing can be used in a variety of different FET applications, and that temperature sensing techniques using conventional gate and/or source structures, as described herein, have little or no effect on the normal operation of the FET.

Field effect transistors can be implemented in different configurations. Exemplary configurations include combinations of configurations (1) to (18) described below.

(1) A field effect transistor with temperature sensing, comprising: a gate electrode; a source electrode contact; a drain electrode contact; a source field plate coupled to the source contact; a first pair of contact pads for applying a probe current through the source field plate; and a second pair of contact pads connected to the source field plate and separated by a second distance for sensing the source field through which the probe current flows voltage on the area of the board.

(2) The field effect transistor of configuration (1), wherein the source field plate covers at least a portion of the gate.

(3) The field effect transistor according to configuration (1) or (2), wherein the source field plate exhibits a change in resistance when the temperature change of the source field plate is not less than 0.001 ohm/ºC.

(4) The field effect transistor of any one of configurations (1) to (3), wherein the source field plate is AC coupled to the source contact.

(5) The field effect transistor according to any one of configurations (1) to (4), wherein the first pair of contact pieces includes a first thin film resistor and a second thin film resistor.

(6) The field effect transistor according to configuration (5), wherein the resistances of the first thin film resistor and the second thin film resistor are not less than 300 ohms.

(7) The field effect transistor of any one of configurations (5) or (6), wherein the second pair of contact pieces includes a third thin film resistor and a fourth thin film resistor.

(8) The field effect transistor according to any one of configurations (5) to (7), wherein the resistances of the third thin film resistor and the fourth thin film resistor are not less than 300 ohms.

(9) The field effect transistor of any one of configurations (1) to (8), further comprising a detection current source connected to the first pair of contact pads.

(10) The field effect transistor of configuration (9), wherein the detection current source is configured to provide an alternating current.

(11) The field effect transistor of configuration (9) or (10), wherein the alternating current has a frequency between 50 kHz and 5 megahertz.

(12) The field effect transistor of any one of configurations (1) to (11), further comprising voltage sensing circuitry connected to the second pair of contact pads.

(13) The field effect transistor of configuration (12), wherein the voltage sensing circuit can provide an output signal to a feedback circuit that controls the power level of the field effect transistor.

(14) The field effect transistor according to any one of configurations (1) to (13), wherein the field effect transistor is incorporated into a power amplifier configured to amplify a signal not lower than 0.25 watt power level.

(15) The field effect transistor of any one of configurations (1) to (14), further comprising an active region controlled by a gate, wherein the active region includes GaN, GaAs, or InP.

(16) The field effect transistor of any one of configurations (1) to (14), further comprising an active region controlled by a gate, wherein the active region includes Si.

(17) The field effect transistor according to any one of configurations (1) to (16), wherein the field effect transistor is an LDMOS FET, MOSFET, MISFET, or MODFET.

(18) The field effect transistor of any one of configurations (1) to (16), wherein the field effect transistor is a HEMT, HFET, or pHEMT.

Methods for operating field effect transistors may include various acts and aspects. Exemplary methods include combinations of method features (19) to (26) as described below. Such methods may be used, at least in part, to operate field effect transistors of the configurations listed above.

(19) A method of operating a field effect transistor, the method comprising: applying a signal to a gate of the field effect transistor; amplifying the signal signal with the field effect transistor; applying a detection current to a source of the field effect transistor a region of the pole field plate, wherein the source field plate is coupled to the source contact of the field effect transistor; and inducing a voltage generated by the probe current.

(20) The method of (19), further comprising evaluating a peak temperature of the field effect transistor from the induced voltage.

(21) The method according to (20), wherein evaluating includes using calibration results associated with field effect transistors.

(22) The method of any one of (19) to (21), further comprising: comparing the sensed voltage with a reference value; and controlling the power level of the field effect transistor based on the comparison.

(23) The method of any one of (19) to (22), wherein applying the probe current includes applying the probe current along a region of the source field plate that covers at least a portion of the gate.

(24) The method of any one of (19) to (23), wherein applying the probe current includes applying an alternating current in the region.

(25) The method according to (24), wherein applying the alternating current includes applying the alternating current at a first frequency that is not less than 10 times different from the carrier frequency amplified by the field effect transistor.

(26) The method according to any one of (19) to (25), wherein applying the probe current includes intermittently applying the probe current in the region such that the probe current is driven at time intervals, the time intervals being driven by the source Regions of the field plate where no probe current is driven are separated by other time intervals.

Field effect transistors can be implemented in different additional configurations. Exemplary configurations include combinations of configurations (27) through (43) as described below.

(27) A field effect transistor with temperature sensing, comprising: a gate; a floating gate plate adjacent to the gate and having an extended length; a source contact; a drain contact; connected to the floating gate plate and a first pair of contact pads separated by a first distance for applying a detection current through the floating gate plate; and a second pair of contact pads connected to the floating gate plate and separated by a second distance for inductive detection The voltage on the area of the floating gate plate through which current flows.

(28) The field effect transistor of configuration (27), wherein the floating gate plate covers at least a portion of the gate.

(29) The field effect transistor according to configuration (27) or (28), wherein the floating gate plate exhibits a change in resistance when the temperature of the floating gate plate changes by not less than 0.001 ohm/ºC.

(30) The field effect transistor of any one of configurations (27) to (29), wherein the first pair of contact pieces includes a first thin film resistor and a second thin film resistor.

(31) The field effect transistor according to configuration (30), wherein the resistances of the first thin film resistor and the second thin film resistor are not less than 300 ohms.

(32) The field effect transistor of any one of configurations (30) or (31), wherein the second pair of contact pieces includes a third thin film resistor and a fourth thin film resistor.

(33) The field effect transistor according to the configuration (32), wherein the resistances of the third thin film resistor and the fourth thin film resistor are not less than 300 ohms.

(34) The field effect transistor of any one of configurations (27) to (33), further comprising a probe current connected to the first pair of contact pads.

(35) The field effect transistor of configuration (34), wherein the detection current source is configured to provide an alternating current.

(36) The field effect transistor of configuration (34) or (35), wherein the alternating current has a frequency between 50 kHz and 5 megahertz.

(37) The field effect transistor of any one of configurations (27) to (36), further comprising voltage sensing circuitry connected to the second pair of contact pads.

(38) The field effect transistor of configuration (37), wherein the voltage sensing circuit provides an output signal to a feedback circuit that controls the power level of the field effect transistor.

(39) The field effect transistor of any one of configurations (27) to (38), wherein the field effect transistor is incorporated into a power amplifier configured to amplify a signal to no less than 0.25 watt power level.

(40) The field effect transistor of any one of configurations (27) to (39), further comprising an active region controlled by a gate, wherein the active region comprises GaN, GaAs, or InP.

(41) The field effect transistor of any one of configurations (27) to (39), further comprising an active region controlled by a gate, wherein the active region includes Si.

(42) The field effect transistor of any one of configurations (27) to (41), wherein the field effect transistor is an LDMOS FET, MOSFET, MISFET, or MODFET.

(43) The field effect transistor of any one of configurations (27) to (41), wherein the field effect transistor is a HEMT, HFET, or pHEMT.

Methods for operating field effect transistors of any of configurations (27)-(43) may include various acts and aspects. Exemplary methods include combinations of method features (44) to (51) as described below. These methods can be used, at least in part, to operate field effect transistors of the configurations (27) to (43) listed above.

(44) A method of operating a field effect transistor, the method comprising: applying a signal to a gate of the field effect transistor; amplifying the signal signal with the field effect transistor; along a floating gate plate of the field effect transistor A probe current is applied to the region, wherein the floating gate plate covers at least a portion of the gate; and a voltage generated by the probe current is induced.

(45) The method of (44), further comprising evaluating a peak temperature of the field effect transistor from the sensed voltage.

(46) The method of (45), wherein evaluating includes using calibration results associated with field effect transistors.

(47) The method of any one of (44) to (46), further comprising: comparing the sensed voltage with a reference value; and controlling the power level of the field effect transistor based on the comparison.

(48) The method of any one of (44) to (47), wherein applying the probe current includes applying the probe current along a region of the floating field plate that covers at least a portion of the gate

(49) The method of any one of (44) to (48), wherein applying the probe current includes applying an alternating current to the region.

(50) The method according to (49), wherein applying the alternating current includes applying the alternating current at a first frequency that is not less than 10 times different from the carrier frequency of the signal amplified by the field effect transistor.

(51) The method according to any one of (44) to (50), wherein applying the detection current comprises applying the detection current to the region intermittently such that the detection current is driven at time intervals, the time intervals being driven by the floating gate Areas of the plate where no probe current is driven are separated by other time intervals.

Field effect transistors can be implemented in different additional configurations. Exemplary configurations include combinations of configurations (52) through (62) as described below.

(52) A field effect transistor with temperature sensing, comprising: a gate metal having an extended length, having a first end and an opposite second end; a source contact; a drain contact; a first contact piece, connected to the gate metal near the first end for applying an alternating detection current to the gate metal; a capacitor and a resistor connected in series between the reference potential and the end region of the gate metal remote from the first end; a A pair of contact pads is connected to a separate area of the gate metal for inducing a voltage drop along the gate metal in response to an AC probe current.

(53) The field effect transistor of configuration (52), wherein the gate metal exhibits a change in resistance when the temperature of the gate metal changes by not less than 0.001 ohm/ºC.

(54) The field effect transistor of any one of configurations (52) or (53), further comprising a probe current source connected to the first contact pad.

(55) The field effect transistor of any one of configurations (52) to (54), wherein the alternating current probe current has a frequency between 50 kilohertz and 5 megahertz.

(56) The field effect transistor of any one of configurations (52) to (55), further comprising voltage sensing circuitry connected to the pair of contact pads.

(57) The field effect transistor of configuration (56), wherein the voltage sensing circuit can provide an output signal to a feedback circuit that controls the power level of the field effect transistor.

(58) The field effect transistor of any one of configurations (52) to (57), wherein the field effect transistor is incorporated into a power amplifier configured to amplify a signal to no less than 0.25 watt power level.

(59) The field effect transistor of any one of configurations (52) to (58), further comprising an active region controlled by a gate, wherein the active region comprises GaN, GaAs, or InP.

(60) The field effect transistor of any one of configurations (52) to (58), further comprising an active region controlled by a gate, wherein the active region includes Si.

(61) The field effect transistor of any one of configurations (52) to (60), wherein the field effect transistor is an LDMOS FET, MOSFET, MISFET, or MODFET.

(62) The field effect transistor of any one of configurations (52) to (60), wherein the field effect transistor is a HEMT, HFET, or pHEMT.

Methods for operating field effect transistors of any of configurations (52)-(62) may include various acts and aspects. Exemplary methods include combinations of method features (63) to (67) as described below. These methods may be used, at least in part, to operate field effect transistors of the configurations (52)-(62) listed above.

(63) A method of operating a field effect transistor, the method comprising: applying a signal to a gate metal of the field effect transistor; amplifying the signal with the field effect transistor; applying an alternating current detection current to the gate electrode of the field effect transistor a first end region of metal, wherein a second end region of gate metal is remote from the first end region and terminated by a capacitor and a resistor connected in series between the reference potential and the second end region; and sensing by The AC probe current produces a voltage drop along the length of the gate metal.

(64) The method of (63), further comprising evaluating a peak temperature of the field effect transistor from the sensed voltage.

(65) The method according to (63) or (64), further comprising: comparing the sensed voltage with a reference value; and controlling the power level of the field effect transistor based on the comparison.

(66) The method according to any one of (63) to (65), wherein applying the AC detection current includes applying the AC detection current at a first frequency that differs from the carrier frequency of the signal by not less than 10 times.

(67) The method of any one of (63) to (67), wherein applying the alternating detection current comprises intermittently applying the alternating detection current to the first end region such that the alternating detection current is driven at time intervals, The time intervals are separated by other time intervals along the length of the gate metal where no AC probe current is driven.

Field effect transistors can be implemented in different additional configurations. Exemplary configurations include combinations of configurations (68) through (78) as described below.

(68) A field effect transistor with temperature sensing, comprising: a gate metal having an extended length, the gate metal having a first end and a second end; a source electrode; a drain electrode; and a first contact piece, at a first end region connected to the gate metal near the first end and configured to apply an alternating probing current to the gate metal, wherein no other contact pads are connected to the gate metal for conducting the probing current, and wherein substantially all of the The probe current is coupled to the FET source after application.

(69) The field effect transistor of configuration (68), further comprising a pair of contact pads connected to separate regions of the gate metal for inducing a voltage drop across the gate metal in response to the alternating probing current.

(70) The field effect transistor of configuration (69), further comprising a voltage sensing circuit connected to the pair of contact pads.

(71) The field effect transistor of configuration (70), wherein the voltage sensing circuitry provides an output signal to a feedback circuit that controls the power level of the field effect transistor.

(72) The field effect transistor of any one of configurations (68) to (71), wherein the gate metal exhibits a change in resistance when the temperature of the gate metal changes by not less than 0.001 ohm/ºC.

(73) The field effect transistor of any one of configurations (68) to (72), wherein the alternating current probe current has a frequency between 50 kilohertz and 5 megahertz.

(74) The field effect transistor of any one of configurations (68) to (73), wherein the field effect transistor is incorporated into a power amplifier configured to amplify a signal to no less than 0.25 watt power level.

(75) The field effect transistor of any one of configurations (68) to (74), further comprising an active region controlled by a gate metal, wherein the active region comprises GaN, GaAs, or InP.

(76) The field effect transistor of any one of configurations (68) to (74), further comprising an active region controlled by a gate metal, wherein the active region includes Si.

(77) The field effect transistor of any one of configurations (68) to (76), wherein the field effect transistor is an LDMOS FET, MOSFET, MISFET, or MODFET.

(78) The field effect transistor of any one of configurations (68) to (76), wherein the field effect transistor is a HEMT, HFET, or pHEMT.

The method for operating the field effect transistor of any of configurations (68)-(78) may include various acts and aspects. Exemplary methods include combinations of method features (79) to (83) as described below. These methods may be used, at least in part, to operate field effect transistors of the configurations (68)-(78) listed above.

(79) A square field effect method for operating a transistor, the method comprising: applying a signal to a gate metal of a field effect transistor; amplifying the signal with the field effect transistor; applying an alternating current detection current to the gate of the field effect transistor a region of the gate metal where substantially all of the AC probe current is coupled to the source of the field effect crystal; and induces a voltage drop along the length of the gate metal produced by the AC probe current.

(80) The method of (79), further comprising evaluating a peak temperature of the field effect transistor from the sensed voltage.

(81) The method of (79) or (80), further comprising: comparing the sensed voltage with a reference value; and controlling the power level of the field effect transistor based on the comparison.

(82) The method according to any one of (79) to (81), wherein applying the AC detection current includes applying the AC detection current at a first frequency that differs from the carrier frequency of the signal by not less than 10 times.

(83) The method of any one of (79) to (82), wherein applying the AC detection current includes intermittently applying the AC detection current to the zone such that the AC detection current is driven at time intervals, the time intervals Other time intervals in which no AC probe current is driven are separated by the region of the gate metal.

in conclusion

In some embodiments, the terms "approximately" and "about" are used to mean within ±20% of the target value, in some embodiments within ±10% of the target value, and in some embodiments ±5% of the target value %, and in some embodiments ±2% of the target value. The terms "approximately" and "approximately" may include target values.

The techniques described herein can be embodied in a method in which at least some of the acts have been described. Actions performed as part of a method may be ordered in any suitable manner. Thus, embodiments may be constructed in a different order to perform actions than described, even though illustrative embodiments are described as sequential actions, possibly including performing some actions concurrently. Furthermore, in some embodiments, methods may contain more actions than those described, and in other embodiments, there may be fewer actions than those described.

Having thus described at least one illustrative embodiment of this invention, various changes, modifications, and improvements will readily occur to those skilled in the art. Such changes, modifications, and improvements are intended to be encompassed by the spirit and scope of the present invention. Furthermore, the supplementary descriptions are exemplary only and not intended to be limiting. The present invention is limited only by those defined by the following claims and their equivalents.

S‧‧‧Source D‧‧‧Drain G‧‧‧Gate L _g ‧‧‧Length W _g ‧‧‧Width direction _{D‧‧‧Distance} IP ‧‧‧Detecting current V _S ‧‧‧Voltage R _S ‧‧‧Resistance value R1, R2, R3, R4‧‧‧Resistor VM ‧‧‧Output voltage V _{ref ‧‧‧Default} reference voltage C _S ‧‧‧Control signal V _gs ‧‧‧Gate bias C1‧‧‧Capacitor IP _{‧‧‧Detector} current V _S (T)‧‧‧Voltage drop 10‧‧‧HEMT105‧‧‧Substrate 112‧‧‧Buffer layer 114‧‧‧Conducting layer 115‧‧‧Electrical Isolation Regions/Isolation Regions 116‧‧‧Barrier Layer 118‧‧‧Semiconductor Cap Layer 120‧‧‧Electrically Insulating Dielectric Layer 122‧‧‧Insulating Layer 130‧‧‧Source Deposition 130‧‧‧Source Electrode 132‧‧‧ Drain Deposition 140‧‧‧Gate Metal/Floating Gate Metal 145‧‧‧Field Plate 147‧‧‧Floating Gate Plate 150‧‧‧2DEG155‧‧‧Hottest Area/Hot Spot 160‧‧‧Source Contact /Gate Metal 161‧‧‧Interconnect 162‧‧‧Drain Contact 170‧‧‧Conductive Lead 180‧‧‧Source Contact Plate 182‧‧‧Drain Contact Plate 185‧‧‧Gate Contact Dot pads 210a, 210b, 212a, 212b‧‧‧Conductive contact pads 211a, 211b, 213a, 213b‧‧‧contact pads 220‧‧‧High resistive impedance element 300‧‧‧Temperature sensing circuit system 310‧‧‧Current source 320‧‧‧Differential Amplifiers330‧‧‧Comparators 410‧‧‧AC Current Sources, Current Sources420‧‧‧AC Voltage Sensing Circuitry 660‧‧‧Source Field Plates 665‧‧‧Conductive Interconnects 667‧‧‧ Capacitive Coupler

FIG . 1A is a front view illustrating the structure of a high electron mobility transistor (HEMT) according to some embodiments;

Figure 1B is a plan view illustrating the gate, source and drain structure of a HEMT according to some embodiments;

1C is a plan view illustrating a linear array of HEMT gates, sources, and drains, according to some embodiments;

FIG . 2A is a front view of a HEMT including a floating gate plate according to some embodiments;

Figure 2B is a plan view illustrating the structure of the gate, source and drain of a HEMT including a floating gate plate, according to some embodiments;

Figure 2C is a plan view illustrating the structure of the gate, source, and drain of a HEMT including a floating gate plate, according to some embodiments;

FIG . 3 is a diagram illustrating temperature sensing circuitry that may be used with floating gate plates according to some embodiments;

FIG . 4 is a diagram illustrating temperature sensing circuitry that may use gates of transistors according to some embodiments;

FIG . 5 is a diagram illustrating temperature sensing circuitry that may use gates of transistors according to some embodiments;

FIG . 6A is a front view illustrating a HEMT with a source field plate usable for thermal induction, according to some embodiments;

Figure 6B illustrates a plan view illustrating the structure of a gate, source, and drain of a HEMT including a source field plate;

Figure 6C illustrates a plan view illustrating the structure of a gate, source, and drain of a HEMT including a floating source field plate;

FIG . 7 is a graph plotting measured source field plate resistance as a function of substrate temperature in accordance with some embodiments;

FIG . 8 is a graph plotting the measured source field plate resistance as a function of amplifier operating power for various substrate temperatures, according to some embodiments;

FIG . 9 is a plot of the inferred temperature of the source field plate as a function of amplifier operating power at various substrate temperatures, according to some embodiments, based on the results of FIG . 8 ; and

FIG . 10 is a plot of the source field plate thermal resistance as a function of substrate temperature calculated according to some embodiments, based on the results of FIG . 9 .

The features and advantages of the illustrated embodiments will become more apparent from the detailed description given below in conjunction with the accompanying drawings.

Domestic storage information (please note in the order of storage institution, date and number) None

Foreign deposit information (please note in the order of deposit country, institution, date and number) None

105‧‧‧Substrate

112‧‧‧Buffer layer

114‧‧‧Conductive layer

120‧‧‧Electrically insulating dielectric layer

122‧‧‧Insulating layer

140‧‧‧Gate Metal/Floating Gate Metal

155‧‧‧Hottest area/hot spot

160‧‧‧Source Contact/Gate Metal

162‧‧‧Drain Contact

660‧‧‧Source Field Plate

D‧‧‧distance

G‧‧‧Gate

L _g ‧‧‧Length

S‧‧‧source

Claims (83)

A field effect transistor with temperature sensing, comprising: a gate; a source contact; a drain contact; a source field plate coupled to the source contact; a first pair of contact pieces, connected to to the source field plate and separated by a first distance for applying a probe current through the source field plate; and a second pair of contacts connected to the source field plate by a second distance spaced for sensing a voltage across the region of the source field plate through which the detection current flows. The field effect transistor of claim 1, wherein the source field plate covers at least a portion of the gate. The field effect transistor of claim 1, wherein the source field plate exhibits a change in resistance when the temperature change of the source field plate is not less than 0.001 ohm/ºC. The field effect transistor of claim 1, wherein the source field plate is AC coupled to the source contact. The field effect transistor according to any one of claims 1 to 4, wherein the first pair of contact pieces includes a first thin film resistor and a second thin film resistor. The field effect transistor of claim 5, wherein a resistance of the first thin film resistor and the second thin film resistor is not less than 300 ohms. The field effect transistor of claim 5, wherein the second pair of contact pieces includes a third thin film resistor and a fourth thin film resistor. The field effect transistor of claim 7, wherein a resistance of the third thin film resistor and the fourth thin film resistor is not less than 300 ohms. The field effect transistor of any one of claims 1 to 4, further comprising a probe current source connected to the first pair of contact pads. The field effect transistor of claim 9, wherein the detection current source is configured to provide alternating current. The field effect transistor of claim 9, wherein the alternating current has a frequency between 50 kHz and 5 megahertz. The field effect transistor of any one of claims 1 to 4, further comprising voltage sensing circuitry connected to the second pair of contact pads. The field effect transistor of claim 12, wherein the voltage sensing circuit provides an output signal to a feedback circuit that controls a power level of the field effect transistor. The field effect transistor of any one of claims 1 to 4, wherein the field effect transistor is incorporated into a power amplifier configured to amplify the signal to a power level of not less than 0.25 watts . The field effect transistor of any one of claims 1 to 4, further comprising an active region controlled by the gate, wherein the active region comprises GaN, GaAs or InP. The field effect transistor of any one of claims 1 to 4, further comprising an active region controlled by the gate, wherein the active region includes Si. The field effect transistor of any one of claims 1 to 4, wherein the field effect transistor is an LDMOS FET, a MOSFET, a MISFET, or a MODFET. The field effect transistor according to any one of claims 1 to 4, wherein the field effect transistor is HEMT, HFET, pHEMT. A method of operating a field effect transistor, the method comprising the steps of: applying a signal to a gate of the field effect transistor; amplifying the signal with the field effect transistor; applying a detection current to a gate of the field effect transistor a region of a source field plate, wherein the source field plate is coupled to a source contact of the field effect transistor; and induces a voltage generated by the probe current. The method of claim 19, further comprising the step of estimating a peak temperature of the field effect transistor from the sensed voltage. The method of claim 20, wherein the evaluating step includes the step of using calibration results associated with the field effect transistor. The method of claim 19, further comprising the steps of: comparing the sensed voltage with a reference value; and controlling a power level of the field effect transistor based on the comparison result. The method of claim 19, wherein the step of applying the probe current includes applying the probe current along a region of the source field plate that covers at least a portion of the gate. The method of any one of claims 19 to 23, wherein the step of applying the probe current includes applying an alternating current to the region. The method of claim 24, wherein the step of applying the alternating current comprises: applying the alternating current at a first frequency, the first frequency being not less than 10 times different from a carrier frequency amplified by the field effect transistor. The method of any one of claims 19 to 23, wherein the step of applying the probe current comprises applying the probe current in the region intermittently such that the probe current is driven at time intervals, the time intervals Other time intervals in which no probe current is driven are separated by this region of the source field plate. A field effect transistor with temperature sensing, comprising: a gate electrode; a floating gate electrode plate adjacent to the gate electrode and having an extended length; a source contact; a drain contact; a first pair contact pads connected to the floating gate plate and separated by a first distance for applying a detection current through the floating gate plate; and a second pair of contact pads connected to the floating gate plate and separated by a A second distance apart for sensing a voltage on an area of the floating gate plate through which the detection current flows. The field effect transistor of claim 27, wherein the floating gate plate covers at least a portion of the gate. The field effect transistor of claim 27, wherein the floating gate plate exhibits a change in resistance when a temperature change of the floating gate plate is not less than 0.001 ohm/°C. The field effect transistor of any one of claims 27 to 29, wherein the first pair of contact pieces includes a first thin film resistor and a second thin film resistor. The field effect transistor of claim 30, wherein a resistance of the first thin film resistor and the second thin film resistor is not less than 300 ohms. The field effect transistor of claim 30, wherein the second pair of contact pieces includes a third thin film resistor and a fourth thin film resistor. The field effect transistor of claim 32, wherein a resistance of the third thin film resistor and the fourth thin film resistor is not less than 300 ohms. The field effect transistor of any one of claims 27 to 29, further comprising a probe current source connected to the first pair of contact pads. The field effect transistor of claim 34, wherein the detection current source is configured to provide an alternating current. The field effect transistor of claim 34, wherein the alternating current has a frequency between 50 kilohertz and 5 megahertz. The field effect transistor of any one of claims 27 to 29, further comprising voltage sensing circuitry connected to the second pair of contact pads. The field effect transistor of claim 37, wherein the voltage sensing circuit provides an output signal to a feedback circuit that controls a power level of the field effect transistor. The field effect transistor of any one of claims 27 to 29, wherein the field effect transistor is incorporated into a power amplifier configured to amplify the signal to a power level of not less than 0.25 watts . The field effect transistor of any one of claims 27 to 29, further comprising an active region controlled by the gate, wherein the active region comprises GaN, GaAs or InP. The field effect transistor of any one of claims 27 to 29, further comprising an active region controlled by the gate, wherein the active region includes Si. The field effect transistor of any one of claims 27 to 29, wherein the field effect transistor is an LDMOS FET, MOSFET, MISFET, or MODFET. The field effect transistor of any one of claims 27 to 29, wherein the field effect transistor is HEMT, HFET, pHEMT. A method of operating a field effect transistor, the method comprising the steps of: applying a signal to a gate of the field effect transistor; amplifying the signal with the field effect transistor; along a float of the field effect transistor A probe current is applied to a region of the gate plate, wherein the floating gate plate covers at least a portion of the gate electrode; and a voltage generated by the probe current is induced. The method of claim 44, further comprising the step of estimating a peak temperature of the field effect transistor from the sensed voltage. The method of claim 45, wherein the step of evaluating includes using calibration results associated with the field effect transistor. The method of claim 44, further comprising the steps of: comparing the sensed voltage with a reference value; and controlling a power level of the field effect transistor based on the comparison result. The method of claim 44, wherein the step of applying the probe current comprises: applying the probe current along a region of the floating gate plate, the region covering at least a portion of the gate. The method of any one of claims 44 to 48, wherein the step of applying the probe current includes applying an alternating current to the region. The method of claim 49, wherein the step of applying the alternating current comprises: applying the alternating current at a first frequency that is not less than a carrier frequency of the signal amplified by the field effect transistor than 10 times. The method of any one of claims 44 to 48, wherein the step of applying the probe current includes intermittently applying the probe current to the region such that the probe current is driven at time intervals, the time intervals being The region of the floating gate plate is separated from other time intervals in which no detection current is driven. A field effect transistor with temperature sensing, comprising: a gate metal having an extended length, the gate metal having a first end and an opposite second end; a source contact; a drain contact ; a first contact piece connected to the gate metal near the first end for applying an alternating current detection current to the gate metal, a capacitor and resistor at a reference potential and away from the first end One end region of the gate metal is connected in series; and a pair of contact pieces are connected to the separated region of the gate metal for inducing a voltage drop along the gate metal in response to the AC detection current. The field effect transistor of claim 52, wherein the gate metal exhibits a change in resistance when a temperature change of the gate metal is not less than 0.001 ohm/°C. The field effect transistor of claim 52, further comprising a probe current source connected to the first contact pad. The field effect transistor of claim 54, wherein the AC detection current has a frequency between 50 kHz and 5 megahertz. The field effect transistor of claim 52, further comprising voltage sensing circuitry connected to the pair of contact pads. The field effect transistor of claim 56, wherein the voltage sensing circuit provides an output signal to a feedback circuit that controls a power level of the field effect transistor. The field effect transistor of any one of claims 52 to 57, wherein the field effect transistor is incorporated into a power amplifier configured to amplify the signal to a power level of not less than 0.25 watts . The field effect transistor of any one of claims 52 to 57, further comprising an active region controlled by the gate metal, wherein the active region comprises GaN, GaAs, or InP. The field effect transistor of any one of claims 52 to 57, further comprising an active region controlled by the gate metal, wherein the active region comprises Si. The field effect transistor of any one of claims 52 to 57, wherein the field effect transistor is an LDMOS FET, MOSFET, MISFET, or MODFET. The field effect transistor of any one of claims 52 to 57, wherein the field effect transistor is HEMT, HFET, pHEMT. A method of operating a field effect transistor, the method comprising the steps of: applying a signal to a gate metal of the field effect transistor; amplifying the signal with the field effect transistor; applying an alternating current detection current to the field effect transistor a first end region of the gate metal of the field effect transistor, wherein a second end region of the gate metal is remote from the first end region and connected to the second end region by a reference potential A capacitor and resistor connected in series therebetween terminate; and induce a voltage drop along a length of the gate metal by the AC probe current. The method of claim 63, further comprising the step of evaluating a peak temperature of the field effect transistor from the sensed voltage. The method of claim 63, further comprising the steps of: comparing the sensed voltage with a reference value; and controlling a power level of the field effect transistor based on the comparison result. The method of claim 63, wherein the step of applying the AC detection current comprises: applying the AC detection current at a first frequency, the first frequency being not less than 10 times different from a carrier frequency of the signal. The method of any one of claims 63 to 66, wherein the step of applying the AC probe current includes intermittently applying the AC probe current to the first end region such that the AC probe current is applied at time intervals driven, the time intervals are separated by other time intervals along the length of the gate metal where no AC probe current is driven. A field effect transistor with temperature sensing, comprising: a gate metal having an extended length, the gate metal having a first end and a second end; a source electrode; a drain electrode; and a first contact pad connected to the gate metal at the first end region near the first end and configured to apply an alternating probing current to the gate metal, wherein no other contact pads are connected to the probing current for conducting the probing current The gate metal, and wherein substantially all of the probe current is coupled to the field effect transistor source after application. The field effect transistor of claim 68, further comprising a pair of contact pads connected to the separated regions of the gate metal for inducing a voltage drop along the gate metal in response to the AC probe current. The field effect transistor of claim 69, further comprising voltage sensing circuitry connected to the pair of contact pads. The field effect transistor of claim 70, wherein the voltage sensing circuitry provides an output signal to a feedback circuit that controls a power level of the field effect transistor. The field effect transistor of any one of claims 68 to 71, wherein the gate metal exhibits a change in resistance when a temperature change of the gate metal is not less than 0.001 ohm/°C. The field effect transistor of any one of claims 68 to 71, wherein the AC probe current has a frequency between 50 kHz and 5 megahertz. The field effect transistor of any one of claims 68 to 71, wherein the field effect transistor is incorporated into a power amplifier configured to amplify the signal to a power level of not less than 0.25 watts . The field effect transistor of any one of claims 68 to 71, further comprising an active region controlled by the gate metal, wherein the active region comprises GaN, GaAs, or InP. The field effect transistor of any one of claims 68 to 71, further comprising an active region controlled by the gate metal, wherein the active region comprises Si. The field effect transistor of any one of claims 68 to 71, wherein the field effect transistor is an LDMOS FET, MOSFET, MISFET, or MODFET. The field effect transistor of any one of claims 68 to 71, wherein the field effect transistor is HEMT, HFET, pHEMT. A method of operating a field effect transistor, the method comprising the steps of: applying a signal to a gate metal of the field effect transistor; amplifying the signal with the field effect transistor; applying an alternating current probe current to the field a region of the gate metal of the FET in which substantially all of the AC probe current is coupled to the source of the FET; and inducing a generated by the AC probe current along a length of the gate metal voltage drop. The method of claim 79, further comprising the step of estimating a peak temperature of the field effect transistor from the sensed voltage. The method of claim 79, further comprising the steps of: comparing the sensed voltage with a reference value; and controlling a power level of the field effect transistor based on the comparison result. The method of any one of claims 79 to 81, wherein the step of applying the AC probe current comprises: applying the AC probe current at a first frequency that is not different from a carrier frequency of the signal less than 10 times. The method of any one of claims 79 to 81, wherein the step of applying the AC detection current comprises: intermittently applying the AC detection current to the region such that the AC detection current is driven at time intervals, etc. Time intervals are separated by other time intervals in which no AC probe current is driven in this region of the gate metal.

Images