TWI768725B - Separate display system - Google Patents

Abstract

A separate display system includes a processing device, a display device, and a transmission cable. The processing device includes a processing unit, a first conversion unit, and a second conversion unit. The display device includes a third conversion unit, a fourth conversion unit, and a display unit. The processing unit generates a first image signal and a first timing control signal. The first conversion unit converts the first image signal into a second image signal. The second conversion unit converts the first timing control signal into a second timing control signal. The third conversion unit receives and converts the second image signal into a third image signal. The fourth conversion unit receives and converts the second timing control signal into a third timing control signal. The display unit displays the third image signal according to the third timing control signal. The transmission cable connects the first conversion unit and the second conversion unit to the third conversion unit and the fourth conversion unit.

Description

Separate display system

This case is about a separate display system, especially a display system in which the host and the display screen are separated.

In a traditional display system, such as a TV, the host and the display screen are arranged in the same body. This configuration causes the volume of the display system to be too large. When the user installs or places the display system, the display system takes up too much space, which is inconvenient, and affects the aesthetics of the environment where the display system is placed.

With the advancement of science and technology, people's demand for multimedia audio and video effects and quality has also increased. For example, a vivid display screen and a good feeling experience are emphasized. The industry has improved the picture quality and resolution of the AV specification technology. High image quality and high resolution make the amount of transmitted signals huge, and the transmission efficiency of signals must be improved. The specifications of the hardware have increased accordingly. Therefore, manufacturers design multiple transmission channels in the transmission line, and the volume of the transmission line increases with the number of transmission channels.

As mentioned above, in order to improve the transmission efficiency of the signal and be able to load a huge amount of transmitted signals, how to reduce the excessive cost caused by the thick transmission line, and avoid the signal energy weakening caused by the long transmission line when transmitting the signal, the above These are all issues that urgently need to be addressed and resolved.

In view of the above, in some embodiments, a separate display system includes a processing device, a display device, and a transmission line. The processing device includes a processing unit, a first converting unit and a second converting unit. The display device includes a third conversion unit, a fourth conversion unit and a display unit. The processing unit generates a first image signal and a first timing signal, the first timing signal has a first timing rate and a first timing channel number, and the first timing rate is lower than the first image rate of the first image signal. The first converting unit converts the first video signal into a second video signal with a second video rate. The second conversion unit converts the first time control signal into a second time control signal, the second time control signal has a second time control rate and a second time control channel number, the first time control rate is lower than the second time control rate, The number of the first timed channels is higher than the number of the second timed channels. The third converting unit receives and converts the second image signal into a third image signal. The fourth converting unit receives and converts the second timing signal into a third timing signal, the third timing signal has a third timing rate and a third timing channel number, and the third timing rate is lower than that of the third video signal. The third image rate. The display unit displays the third image signal according to the third timing signal. The transmission line connects the first conversion unit and the second conversion unit to the third conversion unit and the fourth conversion unit, and the number of channels of the transmission line is equal to the sum of the number of image channels of the second video signal and the number of the second timing channel.

Referring to FIG. 1 , the separate display system includes a processing device 100 , a display device 200 and a transmission line 300 . The split display system can be adapted to a multimedia player. Taking a TV as an example, the display device 200 is a display screen of the TV, and the processing device 100 is a host of the TV. The processing device 100 can generate an image signal and a timing controller (TCON) signal, and send it to the display device 200 , wherein the image signal is a high-speed signal, and the timing signal is a low-speed signal. The display device 200 controls the liquid crystal in the display device 200 to perform regular polarity switching according to the timing signal, and the regular switching of the polarity of the liquid crystal can prevent the display device 200 from generating burn-in in specific pixels. The display device 200 displays the image signal according to the liquid crystal whose polarity is switched. The image signal may include differential signals, and the differential signals include positive differential signals and negative differential signals. But not limited to this, the image signal may not be a differential signal (such as a single transmission signal). The time control signal is not a differential signal, and the time control signal is a control signal of a single transmission signal.

The processing device 100 and the display device 200 are not jointly designed in a casing, and the processing device 100 and the display device 200 are two separate devices. The processing device 100 and the display device 200 are connected to each other by a transmission line 300 . The transmission line 300 has two connectors, one of which is connected to the connector on the processing device 100 , and the other connector of the transmission line 300 is connected to the connector on the display device 200 . The transmission line 300 includes a plurality of pairs of transmission channels for transmitting image signals, one transmission channel in each pair of signal transmission channels is used for transmitting the positive differential signal of the image signal, and the other transmission channel is used for transmitting the image signal the negative differential signal. The transmission line 300 also includes a plurality of single transmission channels for transmitting timing signals. Thereby, the processing device 100 sends the image signal and the control signal to the display device 200 via the transmission line 300, and the display device 200 converts the polarity of the liquid crystal according to the time control signal, and displays the image signal according to the liquid crystal whose polarity is converted. The length of the transmission line 300 can be arbitrarily designed according to the user, and the processing device 100 and the display device 200 can be placed at a distance more than a predetermined distance according to the user's usage habits and environmental space constraints. In some embodiments, the distance between the processing device 100 and the display device 200 and the length of the transmission line 300 may be more than 50 centimeters, and may even be as long as several meters.

Referring to FIG. 2 , the processing apparatus 100 includes a processing unit 110 , a first converting unit 130 and a second converting unit 131 . The first converting unit 130 and the second converting unit 131 are coupled between the processing unit 110 and the transmission line 300 . There are multiple pairs of transmission channels between the first conversion unit 130 and the processing unit 110 (hereinafter referred to as the first image channel 410 , as shown in the figure, a diagonal line is drawn on the first image channel 410 to represent multiple pairs of transmission channels). The communication port 510 is coupled to the processing unit 110 , and the communication port 510 receives and transmits the external video data D1 to the processing unit 110 . The processing unit 110 generates a first image signal S10 according to the video data D1 , the processing unit 110 sends the first image signal S10 according to the first image rate, and the first image signal S10 is sent to the first converting unit 130 through the first image channel 410 . Each pair of transmission channels in the first image signal S10 is respectively transmitted by each pair of transmission channels of the first image channel 410 . The first image signal S10 and the first image channel 410 have substantially the same number of first image channels.

The processing unit 110 includes a timing controller 111, the timing controller 111 is coupled to the second converting unit 131, and the timing controller 111 generates a first timing signal S11. There are multiple transmission channels (hereinafter referred to as the first timing channel 411 ) between the second conversion unit 131 and the timing controller 111 . The timing controller 111 sends the first timing signal S11 according to the first timing rate, and the first timing signal S11 is transmitted to the second converting unit 131 through the first timing channel 411 . Each single transmission channel of the first timing signal S11 is respectively transmitted by each single transmission channel of the first timing channel 411 . The first timing signal S11 and the first timing channel 411 have the same number of first timing channels.

The first converting unit 130 receives and converts the first image signal S10 having the first image rate into the second image signal S20. The second image signal S20 has a second image rate greater than the first image rate. The second converting unit 131 receives and converts the first timing signal S11 into the second timing signal S21. The second clock rate of the second clock signal S21 is greater than the first clock rate of the first clock signal S11. The first converting unit 130 and the second converting unit 131 respectively send the second image signal S20 and the second timing signal S21 to the transmission line 300 .

The transmission line 300 includes a plurality of pairs and a plurality of transmission channels, respectively used for transmitting a plurality of pairs of second video signals S20 (hereinafter referred to as second video channels) and a plurality of second timing signals S21 (hereinafter referred to as second timing channels) . The width and thickness of the transmission line 300 are related to the number of second video channels (hereinafter referred to as the number of second video channels) and the number of second timing channels (hereinafter referred to as the number of second timing channels). The sum of the number of transmission channels of the transmission line 300 is substantially equal to the sum of the number of the second image channels and the number of the second timing channels. Each pair of transmission channels in the second image signal S20 is respectively transmitted to the display device 200 by each pair of transmission channels of the second image channel, and each transmission channel in the second timing signal S21 is respectively transmitted by each pair of the second timing channels The transmission channel is transmitted to the display device 200 . The second image signal S20 and the second timing signal S21 respectively have a second number of image channels and a second number of timing channels. Since the second image rate and the second timing rate are larger than the first image rate and the first timing rate, respectively, the number of the second image channel and the number of the second timing channel are smaller than the number of the first image channel and the first timing channel, respectively . Assuming that the transmission line 300 uses the first number of video channels and the first number of timing channels, the line width will be greater than the line width when the second number of video channels and the second number of timing channels are used, so the transmission line 300 uses the second number of video channels and The second time-controlled channel number can reduce the manufacturing cost, and the user is more convenient to use.

In some embodiments, after the display device 200 receives the second image signal S20 and the second timing signal S21, the display device 200 reduces the second image signal S20 and the second timing signal S21 to the transmission rate before the increase, and then The image is displayed and the polarity of the liquid crystal is switched, but not limited thereto, the display device 200 can also reduce the second image signal S20 to a different transmission rate than before the increase, and then display the image. In detail, the display device 200 includes a third conversion unit 210 , a fourth conversion unit 211 and a display unit 230 . The third converting unit 210 and the fourth converting unit 211 are coupled between the transmission line 300 and the display unit 230 . There are multiple pairs of transmission channels (hereinafter referred to as third image channels 430 ) between the third conversion unit 210 and the display unit 230 . There are multiple transmission channels (hereinafter referred to as the third timing channel 431 ) between the fourth conversion unit 211 and the display unit 230 . The third conversion unit 210 receives the second video signal S20 from the transmission line 300 , and the third conversion unit 210 converts the second video signal S20 into a third video signal S30 having a third video rate. Each pair of transmission channels in the third image signal S30 is respectively transmitted by each pair of transmission channels of the third image channel 430 . The third video signal S30 and the third video channel 430 have the same number of third video channels. The number of the third image channels is smaller than the number of the second image channels, and the number of the third image channels may be substantially the same as the number of the first image channels or different from the number of the first image channels. The third image rate is less than the second image rate, and the third image rate may be substantially the same as the first image rate or different from the first image rate. When the third image rate is substantially the same as the first image rate, the third image signal S30 is substantially the same as the first image signal S10.

After the fourth converting unit 211 receives the second timing signal S21 from the transmission line 300, the fourth converting unit 211 converts the second timing signal S21 into a third timing signal S31, and the third timing signal S31 has a third timing signal rate. Each transmission channel of the third timing signal S31 is respectively transmitted by each transmission channel of the third timing channel 431 . The number of channels of the third timing signal S31 and the third timing channel 431 are both the number of the third timing channel. Wherein, the number of the third timing control channels is smaller than the number of the second timing control channels, and the number of the third timing control channels may be substantially the same as the number of the first timing control channels or different from the number of the first timing control channels. The third timing rate is smaller than the second timing rate, and the third timing rate is substantially the same as the first timing rate or different from the first timing rate. When the third clock rate is substantially the same as the first clock rate, the third clock signal S31 is substantially the same as the first clock signal S11. The fourth converting unit 211 sends the third timing signal S31 to the display unit 230 via the third timing channel 431 at the third timing rate. The display unit 230 converts the polarity of the liquid crystal according to the third timing signal S31 and displays the third image signal S30.

Therefore, the number of channels of the transmission line 300 can be reduced, so as to avoid the inconvenience of the user and the cost of the transmission line 300 caused by the transmission line 300 being too thick. In addition, through the conversion units 210 and 211, the second image signal S20 and the second timing signal S21 with the increased transmission rate can be converted into the third image signal S30 and the third timing signal S31 respectively, and the third image rate is low. At the second image rate, the third timing rate is lower than the second timing rate, so the display unit 230 can switch the polarity of the liquid crystal according to the third timing signal S31 and display the third image signal S30.

In some embodiments, when the first image channel number is divided by the second image channel number as a ratio, the second image rate is divided by the first image rate as the ratio, and the third image channel number is divided by the second image channel The number is the ratio, and the second frame rate divided by the third frame rate is the ratio. When the ratio of the number of the first timing control channels divided by the number of the second timing control channels is a ratio, the second timing control rate divided by the first timing control rate is the ratio, and the third timing control channel number is divided by the second timing control rate. The number of channels is the ratio, and the second clocked rate divided by the third clocked rate is the ratio. That is to say, the number of channels is inversely proportional to the transmission rate, and the multiple of increasing the transmission rate can correspond to the multiple of decreasing the number of channels. When the second image rate and the second timing rate can be twice the first image rate and the first timing rate, the second image channel number and the second timing channel number can be the first image channel number and the first Half of the number of timing channels; when the second image transmission rate and the second timing transmission rate can be twice the third image transmission rate and the third timing transmission rate, the number of the second image channels and the second timing channel The number can be half the number of the third image channel and the number of the third timing channel. However, the above embodiments are not limited. In other embodiments, the ratio of the first image rate to the second image rate, the ratio of the number of second image channels to the number of third image channels, the second image rate to the third image The ratio between the rate and the ratio of the number of the first image channel and the number of the second image channel is not a fixed ratio relationship. In other embodiments, the ratio of the first clocking rate to the second clocking rate, the ratio of the number of the second clocking channel to the number of the third clocking channel, the ratio of the second clocking rate and the third clocking rate , and the ratio between the number of the first time-controlled channel and the number of the second time-controlled channel is not a fixed ratio relationship.

In some embodiments, the image signals S10, S20, and S30 are high-speed signals and the timing signals S11, S21, and S31 are low-speed signals, and the transmission rate of the timing signal S11 is lower than the transmission rate of the image signal S10 and the transmission rate of the timing signal S21. The rate is lower than the transmission rate of the image signal S20, and the transmission rate of the timing signal S31 is smaller than the transmission rate of the image signal S30. For example, the number of first video channels is 16 pairs, the number of second video channels is 8 pairs, the first video rate is 75MHz, the second video rate is 150MHz, and the aforementioned ratio is 2. The number of the first timing control channel is 16, the number of the second timing control channel is 8, the first timing control rate is 50MHz, the second timing control rate is 100MHz, and the aforementioned ratio is also 2.

In some embodiments, the first timing channel number is equal to the first image channel number, the second timing channel number is equal to the second image channel number, and the third timing channel number is equal to the third image channel number. In other embodiments, not limited to the above, the number of the first time-controlled channels may not be equal to the number of the first image channels, the number of the second time-controlled channels may not be equal to the number of the second image channels, and the number of the third time-controlled channels may also be different. It may not be equal to the number of third image channels.

In some embodiments, please refer to FIG. 3 , the processing device 100 further includes a first buffer 150 , a first flip-flop 170 , a second buffer 151 and a second flip-flop 171 . The first converting unit 130 and the second converting unit 131 are coupled to the processing unit 110 , the processing unit 110 and the first converting unit 130 have a first image channel 410 , and the processing unit 110 and the second converting unit 131 are control channel 411. The first buffer 150 is coupled between the first conversion unit 130 and the first flip-flop 170 , and there are multiple pairs of transmission channels (hereinafter referred to as the fourth image channel 440 ) between the first conversion unit 130 and the first buffer 150 . , there are multiple pairs of transmission channels (hereinafter referred to as the fifth image channel 450 ) between the first buffer 150 and the first flip-flop 170 . The second buffer 151 is coupled between the second conversion unit 131 and the second flip-flop 171 , and there are multiple pairs of transmission channels (hereinafter referred to as the fourth timing channel 441 ) between the second conversion unit 131 and the second buffer 151 ), there are multiple pairs of transmission channels (hereinafter referred to as the fifth timing channel 451 ) between the second buffer 151 and the second flip-flop 171 . The first flip-flop 170 and the second flip-flop 171 are coupled to the transmission line 300 . The fourth video channel 440 and the fifth video channel 450 have the same number of second video channels as the second video signal S20 , and the fourth time control channel 441 and the fifth time control channel 451 have the same number of second video channels as the second time control signal S21 . Number of two image channels.

The first converting unit 130 stores the converted second image signal S20 in the first buffer 150 via the fourth image channel 440 . The second converting unit 131 stores the converted second timing signal S21 in the second buffer 151 via the fourth timing channel 441 . The alignment unit 190 is coupled to the first flip-flop 170 and the second flip-flop 171 , and the alignment unit 190 sends the alignment signal A1 to the first flip-flop 170 and the second flip-flop 171 . When the first flip-flop 170 and the second flip-flop 171 receive the alignment signal A1, the first flip-flop 170 obtains the second image signal S20 from the first buffer 150 through the fifth image channel 450, and the second flip-flop 171 obtains the second image signal S20 through the fifth image channel 450. The five timing channels 451 obtain the second timing signal S21 from the second buffer 151 . In addition, the first flip-flop 170 and the second flip-flop 171 transmit the second image signal S20 and the second timing signal S21 synchronously (ie, substantially at the same time) according to the alignment signal A1. The second image signal S20 and the second timing signal S21 are synchronously transmitted to the display device 200 through the second image channel and the second timing channel in the transmission line 300 , respectively. Based on this, the display device 200 receives the second image signal S20 and the second timing signal S21 synchronously, and the second image signal S20 and the second timing signal S21 can correspond to each other correctly according to the synchronous reception. In order to avoid errors when the display device 200 processes the second image signal S20 and the second timing signal S21 due to the time difference in displaying the image and switching the polarity of the liquid crystal.

In other embodiments, please refer to FIG. 4, in the processing device 100a, the positions of the first buffer 150 and the first flip-flop 170 can be exchanged with the first conversion unit 130, the second buffer 151 and the second flip-flop The position of 171 can be exchanged with the first conversion unit 130 . In detail, the first buffer 150 and the second buffer 151 are coupled to the processing unit 110 , the fourth image channel 440 is arranged between the first buffer 150 and the processing unit 110 , and the second buffer 151 and the processing unit 110 are arranged between the first buffer 150 and the processing unit 110 . There is a fourth timing channel 441 . The first flip-flop 170 is coupled between the first buffer 150 and the first converting unit 130 , there is a fifth image channel 450 between the first flip-flop 170 and the first buffer 150 , and the first converting unit 130 and the first There is a first image channel 410 between the flip-flops 170 . The second flip-flop 171 is coupled between the second buffer 151 and the second conversion unit 131 , there is a fifth timing control channel 451 between the second flip-flop 171 and the second buffer 151 , the second conversion unit 131 and the first A first timing channel 411 is provided between the two flip-flops 171 . The first converting unit 130 and the second converting unit 131 are coupled to the transmission line 300 . The fourth image channel 440 and the fifth image channel 450 have the same number of first image channels as the first image signal S10, and the fourth timing channel 441 and the fifth timing channel 451 have the same number of first image channels as the first timing signal S11. The number of channels is controlled at one time.

The processing unit 110 sends the first image signal S10 to the first buffer 150 through the fourth image channel 440 and sends the first timing signal S11 to the second buffer 151 through the fourth clock channel 441 to store. The alignment unit 190 sends the alignment signal A1 to the first flip-flop 170 and the second flip-flop 171 . When the first flip-flop 170 and the second flip-flop 171 receive the alignment signal A1, the first flip-flop 170 obtains the first image signal S10 from the first buffer 150 through the fifth image channel 450, and the second flip-flop 171 obtains the first image signal S10 through the fifth image channel 450. The five timing channels 451 obtain the first timing signal S11 from the second buffer 151 . In addition, the first flip-flop 170 and the second flip-flop 171 transmit the first image signal S10 and the first timing signal S11 synchronously according to the alignment signal A1. The first video signal S10 and the first timing signal S11 are synchronously sent to the first conversion unit 130 via the first video channel 410 and to the second conversion unit 131 via the first timing channel 411 . The first converting unit 130 and the second converting unit 131 can synchronously convert the first image signal S10 and the first timing signal S11 into the second image signal S20 and the second timing signal S21, and convert the second image signal S20 and The second timing signal S21 is transmitted to the display device 200 through the second image channel and the second timing channel in the transmission line 300 . Based on this, errors in displaying the image and switching the polarity of the liquid crystal caused by the time difference when the display device 200 processes the second image signal S20 and the second timing signal S21 can be avoided.

In some embodiments, please refer to FIG. 5 , the display device 200 further includes a third buffer 250 , a third flip-flop 270 , a fourth buffer 251 and a fourth flip-flop 271 . The third conversion unit 210 and the fourth conversion unit 211 are coupled to the transmission line 300 . The third buffer 250 is coupled between the third conversion unit 210 and the third flip-flop 270 , and there are multiple pairs of transmission channels (hereinafter referred to as the sixth image channel 460 ) between the third conversion unit 210 and the third buffer 250 . , there are also multiple pairs of transmission channels (hereinafter referred to as the seventh image channel 470 ) between the third buffer 250 and the third flip-flop 270 . The fourth buffer 251 is coupled between the fourth conversion unit 211 and the fourth flip-flop 271 , and there are multiple pairs of transmission channels (hereinafter referred to as the sixth image channel 460 ) between the fourth conversion unit 211 and the fourth buffer 251 . , there are also multiple pairs of transmission channels (hereinafter referred to as the seventh image channel 470 ) between the fourth buffer 251 and the fourth flip-flop 271 . The third flip-flop 270 and the fourth flip-flop 271 are coupled to the display unit 230 . control channel 431. Among them, the channel numbers of the sixth video channel 460, the seventh video channel 470 and the third video signal S30 are all the number of the third video channel, the sixth time control channel 461, the seventh time control channel 471 and the third time control signal S31 The number of channels is the number of the third time-controlled channel.

The third converting unit 210 and the fourth converting unit 211 respectively convert the second image signal S20 and the second timing signal S21 from the transmission line 300 into the third image signal S30 and the third timing signal S31. The third conversion unit 210 stores the third video signal S30 in the third buffer 250 via the sixth video channel 460 , and stores the third timing signal S31 in the fourth buffer 251 via the sixth clock channel 461 . The alignment unit 290 is coupled to the third flip-flop 270 and the fourth flip-flop 271 , and the alignment unit 290 sends the alignment signal A2 to the third flip-flop 270 and the fourth flip-flop 271 . When the third flip-flop 270 and the fourth flip-flop 271 receive the alignment signal A2, the third flip-flop 270 obtains the third image signal S30 from the third buffer 250 through the seventh image channel 470, and the fourth flip-flop 271 passes through the The seven-time control channel 471 obtains the third time control signal S31 from the fourth buffer 251 . In addition, the third flip-flop 270 and the fourth flip-flop 271 synchronously send the third image signal S30 and the third timing signal S31 to the display unit 230 according to the alignment signal A2. Based on this, the display device 200 receives the third video channel 430 and the third timing channel 431 synchronously, and the third video signal S30 and the third timing channel 431 can correspond to each other correctly according to the synchronous reception. In order to prevent the display device 200 from being affected by the time difference when the display device 200 displays the third image signal S30 and switches the polarity of the liquid crystal according to the third timing control channel 431 , an error occurs.

In other embodiments, please refer to FIG. 6, in the display device 200a, the positions of the third buffer 250 and the third flip-flop 270 can be exchanged with the third conversion unit 210, the fourth buffer 251 and the fourth flip-flop The position of 271 can be exchanged with the fourth conversion unit 211 . In detail, the third buffer 250 and the fourth buffer 251 are coupled to the transmission line 300 . The third flip-flop 270 is coupled between the third buffer 250 and the third conversion unit 210 , there is a seventh image channel 470 between the third buffer 250 and the third flip-flop 270 , and the third flip-flop 270 and the third There is a sixth image channel 460 between the conversion units 210 . The fourth flip-flop 271 is coupled between the fourth buffer 251 and the fourth conversion unit 211 , a seventh timing channel 471 is provided between the fourth buffer 251 and the fourth flip-flop 271 , and the fourth flip-flop 271 is connected to the fourth flip-flop 271 . There is a sixth timing channel 461 between the four conversion units 211 . The third converting unit 210 and the fourth converting unit 211 are coupled to the display unit 230 , and there are a third image channel 430 and a third timing channel 431 between the converting units 210 , 211 and the display unit 230 , respectively. The seventh video channel 470 and the sixth video channel 460 have the same number of second video channels as the second video signal S20 , and the seventh clock channel 471 and the sixth clock channel 461 have the same number of second video channels as the second clock signal S21 . Two time-controlled channels.

The transmission line 300 transmits and stores the second image signal S20 and the second timing signal S21 to the third buffer 250 and the fourth buffer 251, respectively. The alignment unit 290 sends the alignment signal A2 to the third flip-flop 270 and the fourth flip-flop 271 . When the third flip-flop 270 and the fourth flip-flop 271 receive the alignment signal A2 , the third flip-flop 270 obtains the second image signal S20 from the third buffer 250 through the seventh image channel 470 , and the fourth flip-flop 271 obtains the second image signal S20 through the seventh image channel 470 . The seven-time control channel 471 obtains the second time control signal S21 from the fourth buffer 251 . In addition, the third flip-flop 270 and the fourth flip-flop 271 respectively transmit the second image signal S20 and the second timing signal S21 synchronously according to the alignment signal A2. The second image signal S20 and the second timing signal S21 are simultaneously sent to the third conversion unit 210 via the sixth image channel 460 and to the fourth conversion unit 211 via the sixth timing channel 461 . The third converting unit 210 and the fourth converting unit 211 can simultaneously convert the second image signal S20 and the second timing signal S21 into the third image signal S30 and the third timing signal S31, and convert the third image signal S30 and The third timing signal S31 is transmitted to the display unit 230 through the third image channel 430 and the third timing channel 431 respectively. Based on this, the display unit 230 can avoid errors caused by the time difference when the display unit 230 displays the third image signal S30 and switches the polarity of the liquid crystal according to the third timing channel 431 .

In some embodiments, please refer to FIG. 7 with reference to FIGS. 2 to 6 , the processing device 100b includes two first conversion units 130 , 132 , two second conversion units 131 , 133 , and two first buffers 150, 152, 2 second buffers 151, 153, 2 first flip-flops 170, 172, 2 second flip-flops 171, 173. The display device 200b includes two third conversion units 210, 212, two fourth conversion units 211, 213, two third buffers 250, 252, two fourth buffers 251, 253, and two third flip-flops 270, 272, 2 fourth flip-flops 271, 273. The above quantities are not limited in this case. The first image channel 412 is coupled between the processing unit 110 and the first converting unit 132 . The fourth image channel 442 is coupled between the first converting unit 132 and the first buffer 152 . The fifth image channel 452 is coupled between the first buffer 152 and the first flip-flop 172 . The first timing control channel 413 is coupled between the timing controller 111 in the processing unit 110 and the second converting unit 133 . The fourth timing channel 443 is coupled between the second conversion unit 133 and the second buffer 153 . The fifth timing channel 453 is coupled between the second buffer 153 and the second flip-flop 173 . The transmission line 300 is coupled between the flip-flops 171 and 173 and the conversion units 211 and 213 . The sixth image channel 462 is coupled between the third conversion unit 212 and the third buffer 252 . The seventh image channel 472 is coupled between the third buffer 252 and the third flip-flop 272 . The third image channel 432 is coupled between the third flip-flop 272 and the display unit 230 . The sixth timing channel 463 is coupled between the fourth converting unit 213 and the fourth buffer 253 . The seventh timing channel 473 is coupled between the fourth buffer 253 and the fourth flip-flop 273 . The third timing channel 433 is coupled between the fourth flip-flop 273 and the display unit 230 . The fourth image channel 442 and the fifth image channel 452 have the same number of second image channels as the second image signal S22, and the fourth timing channel 443 and the fifth timing channel 453 have the same number of the second timing signal S23. Two time-controlled channels. The sixth image channel 462 and the seventh image channel 472 have the same number of third image channels as the third image signal S32, and the sixth timing channel 463 and the seventh timing channel 473 have the same number of third image channels as the third timing signal S33. Three time-controlled channels. Operations between the conversion units 132, 133, 212, 213, buffers 152, 153, 252, 253, flip-flops 172, 173, 272, 273 and the processing unit 110, the alignment units 190, 290, the transmission line 300 and the display unit 230 Similar to the conversion units 130 , 131 , 210 , 211 , buffers 150 , 151 , 250 , 251 , flip-flops 170 , 171 , 270 , and 271 in the above-mentioned embodiments, an embodiment is given below, using the buffer 150 -153, 250-253 are coupled after the conversion units 130-133, 210-213 are briefly described.

As shown in FIG. 7 , the processing unit 110 simultaneously generates the first image signals S10 and S12 and the first timing signals S11 and S13, wherein the processing unit 110 sends the first image signal S12 to the first converting unit 132 and sends the first image signal S12 to the first converting unit 132. The time control signal S13 is sent to the second conversion unit 133 . The first video signal S12 and the first video channel 412 have the same number of first video channels and the same first video rate. The first timing signal S13 and the first timing channel 413 have the same number of first timing channels and the same first timing rate. The first converting unit 132 and the second converting unit 133 convert the first image signal S12 and the first timing signal S13 into the second image signal S22 and the second timing signal S23 respectively, and convert the second image signal S22 and the second timing signal S22 The control signal S23 is stored in the first buffer 152 and the second buffer 153 respectively. The second video signal S22 has substantially the same second video channel number and second video rate as the second video signal S20. The second clocking signal S23 has substantially the same second clocking channel number and second clocking rate as the second clocking signal S21. The alignment unit 190 sends the alignment signal A1 to the first flip-flop 172 and the second flip-flop 173 . When the first flip-flop 172 and the second flip-flop 173 receive the alignment signal A1, the first flip-flop 172 obtains the second image signal S22 from the first buffer 152, and the second flip-flop 173 obtains the second image signal S22 from the second buffer 153. Two time control signals S23. In addition, the first flip-flop 172 and the second flip-flop 173 synchronously send the second image signal S22 and the second timing signal S23 according to the alignment signal A1, and the second image signal S22 and the second timing signal S23 are sent to the transmission line 300 to the The third converting unit 212 and the fourth converting unit 213 .

The third converting unit 212 and the fourth converting unit 213 convert the second image signal S22 and the second timing signal S23 into the third image signal S32 and the third timing signal S33, respectively, and store the third image signal S32 and the third image signal S32, respectively. The three timing signals S33 are sent to the third buffer 252 and the fourth buffer 253 . The third video signal S32 has substantially the same third video channel number and third video rate as the third video signal S30. The third clocking signal S33 has substantially the same third clocking channel number and third clocking rate as the third clocking signal S31 . The alignment unit 290 sends the alignment signal A2 to the third flip-flop 272 and the fourth flip-flop 273 . When the third flip-flop 272 and the fourth flip-flop 273 receive the alignment signal A2, the third flip-flop 272 and the fourth flip-flop 273 obtain the third image signal S32 and the third image signal S32 from the third buffer 250 and the fourth buffer 253, respectively. Three-time control signal S33. Moreover, the third flip-flop 272 and the fourth flip-flop 273 synchronously send the third image signal S32 and the third timing signal S33 to the display unit 230 according to the alignment signal A2.

In some embodiments, each image transmission signal S10-S13, S20-S23, S30-S33 includes video (Video) data and audio (Audio) information. In some embodiments, the conversion units 130-133, 210-213 may be software, hardware, firmware or a combined logic circuit. The flip-flops 170-173, 270-273 may be logic circuits. The buffers 150-153, 250-253 may be hardware registers. The processing unit 110 may be an embedded controller (EC), an application specific integrated circuit (ASIC), or a system on a chip (SOC). The display unit may be a liquid crystal display (Liquid-Crystal Display; LCD), or a light-emitting diode (Light-emitting diode; LED).

To sum up, in some embodiments, the number of channels of the transmission line can be reduced according to the arrangement of the first conversion unit and the second conversion unit to increase the transmission rate of the video signal and the control signal. Avoid the inconvenience of the user and the cost of the transmission line caused by the transmission line being too thick. According to the arrangement of the third conversion unit and the fourth conversion unit to reduce the transmission rate of the video signal and the control signal, the display unit can smoothly display the video signal and convert the polarity of the liquid crystal. In addition, setting buffers and flip-flops can achieve the effect of transmission synchronization, so as to avoid time errors during transmission, which may lead to errors during execution of the display device. By arranging a plurality of the first conversion unit, the second conversion unit, the third conversion unit and the fourth conversion unit, the transmission efficiency of the image signal and the control signal can also be improved, and the amount of the image signal and the control signal that can be transmitted is increased. In order to provide higher-resolution image display and more efficient liquid crystal polarity conversion. In some embodiments, when a plurality of conversion units operate simultaneously, the image processing capability is increased, and the timing signal can be transmitted by only one group of the conversion units.

Although this case has been disclosed with the above examples, it is not intended to limit this case. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of this case. Therefore, the protection scope of this case is The scope of the patent application attached herewith shall prevail.

100: Processing device 100a: Processing device 100b: Processing device 110: Processing unit 111: Timing Controller 130: First conversion unit 131: Second conversion unit 132: First conversion unit 133: Second conversion unit 150: First buffer 151: Second buffer 152: First buffer 153: Second buffer 170: First Trigger 171: Second Trigger 172: First Trigger 173: Second Trigger 190: Align Unit 200: Display device 200a: Display Devices 200b: Display Devices 210: Third conversion unit 211: Fourth conversion unit 212: Third conversion unit 213: Fourth conversion unit 230: Display unit 250: Third buffer 251: Fourth Buffer 252: Third Buffer 253: Fourth Buffer 270: Third Trigger 271: Fourth Trigger 272: Third Trigger 273: Fourth Trigger 290: Align Unit 300: Transmission Line 410: The first image channel 411: The first time control channel 412: First image channel 413: The first time control channel 430: The third image channel 431: The third time control channel 432: The third image channel 433: The third time control channel 440: Fourth image channel 441: Fourth timing channel 442: Fourth image channel 443: Fourth timing channel 450: Fifth Image Channel 451: Fifth timing channel 452: Fifth Image Channel 453: Fifth timing channel 460: sixth image channel 461: sixth timing channel 462: sixth image channel 463: sixth timing channel 470: Seventh Image Channel 471: Seventh time control channel 472: Seventh Image Channel 473: Seventh time control channel 431: Third channel 510: communication port S10: The first video signal S11: The first timing signal S12: The first video signal S13: The first timing signal S20: The second video signal S21: Second time control signal S22: The second video signal S23: Second timing signal S30: The third video signal S31: The third timing signal S32: The third video signal S33: The third timing signal A1: Alignment signal A2: Alignment signal D1: Video data

[FIG. 1] is a schematic diagram of an embodiment of a separate display system applying the present invention. [FIG. 2] is a schematic block diagram of an embodiment of a separate display system according to the present application. [FIG. 3] is a block diagram of another embodiment of the processing device of the separate display system according to the present application. 4 is a block diagram of another embodiment of the processing device of the separate display system according to the present application. FIG. 5 is a block diagram of another embodiment of the display device of the separate display system according to the present application. FIG. 6 is a block diagram of another embodiment of the display device of the separate display system according to the present application. FIG. 7 is a block diagram of another embodiment of the separate display system according to the present invention.

100: Processing device

110: Processing unit

111: Timing Controller

130: First conversion unit

131: Second conversion unit

200: Display device

210: Third conversion unit

211: Fourth conversion unit

230: Display unit

300: Transmission Line

410: The first image channel

411: The first time control channel

430: The third image channel

431: The third time control channel

510: communication port

S10: The first video signal

S11: The first timing signal

S20: The second video signal

S21: Second time control signal

S30: The third video signal

S31: The third timing signal

D1: Video data

Claims (10)

A separate display system includes: a processing device, including: a processing unit for generating a first image signal and a first timing signal, the first timing signal has a first timing rate and a first timing a number of clocked channels, the first clocking rate is lower than a first image rate of the first image signal; a first converting unit is used for converting the first image signal into one having a second image rate a second image signal; and a second converting unit for converting the first timing signal into a second timing signal, the second timing signal having a second timing rate and a second timing channel number, the first timing control rate is lower than the second timing control rate, the first timing control channel number is higher than the second timing control channel number; a display device, comprising: a third conversion unit for receiving and converting the second image signal into a third image signal; a fourth converting unit for receiving and converting the second timing signal into a third timing signal, the third timing signal having a third timing signal speed and a third timing control channel number, the third timing control rate is lower than a third image rate of the third image signal; and a display unit for displaying the third image signal according to the third timing signal ;and A transmission line is used for connecting the first conversion unit and the second conversion unit to the third conversion unit and the fourth conversion unit, and the number of channels of the transmission line is equal to the number of image channels of the second image signal and the number of the second The sum of the number of time-controlled channels; wherein, the display device and the processing device are two separate devices. The separate display system according to claim 1, wherein the number of the first timing control channels divided by the number of the second timing control channels is a ratio, and the second timing control rate divided by the first timing control rate is the The ratio; the third timed channel number divided by the second timed channel number is the ratio, and the second timed rate divided by the third timed rate is the ratio. The separate display system of claim 2, wherein the processing device comprises a first buffer, a first flip-flop, a second buffer and a second flip-flop, and the first buffer receives and stores the second image signal from the first conversion unit, the second buffer receives and stores the second timing signal from the second conversion unit, the first flip-flop sends the second image signal according to an alignment signal To the transmission line, the second flip-flop sends the second timing signal to the transmission line according to the alignment signal. The separate display system of claim 2, wherein the processing device comprises a first buffer, a first flip-flop, a second buffer and a second flip-flop, and the first buffer receives and stores the first image signal from the processing unit, the second buffer receives and stores the first timing signal from the processing unit, the first flip-flop sends the first image signal to the first according to an alignment signal a conversion unit, the second flip-flop sends the first timing signal to the second conversion unit according to the alignment signal. The separate display system according to claim 3 or 4, wherein the display device comprises a third buffer, a third flip-flop, a fourth buffer and a fourth flip-flop, The third buffer receives and stores the third image signal from the third conversion unit, the fourth buffer receives and stores the third timing signal from the fourth conversion unit, and the third flip-flop is based on another An alignment signal sends the third image signal to the display unit, and the fourth flip-flop sends the third timing signal to the display unit according to the other alignment signal. A separate display system includes: a processing device, including: a processing unit for generating a plurality of first image signals and a plurality of first timing signals, each of the first timing signals having a first timing control rate and a number of first timing channels, each of the first timing rates is lower than each of the first image rates of the first image signals; a plurality of first conversion units, one-to-one corresponding to the first image signals, each of the first converting units is used for converting each of the first image signals into a second image signal having a second image rate; and a plurality of second converting units corresponding to the a first time control signal, each of the first conversion units is used for converting each of the first time control signals into a second time control signal, and each of the second time control signals has a second time control rate and a the number of second timing control channels, each of the first time control rate is lower than each of the second time control rate, the number of each of the first time control channels is higher than the number of each of the second time control channels; a display device , comprising: a plurality of third conversion units, one-to-one corresponding to some of the first conversion units, each of the third conversion units is used for receiving and converting each of the second image signals into a third image signal; A plurality of fourth conversion units correspond to the second conversion units one by one, each of the fourth conversion units is used for receiving and converting each of the second time control signals into a third time control signal, each of the first time control signals The three clocked signals have a third clocked rate and a third number of clocked channels, each of the third clocked rates is lower than a third image rate of each of the third video signals; and a display unit, using displaying the third image signals according to the third timing signals; and a transmission line for connecting the first conversion unit and the second conversion unit to the third conversion unit and the fourth conversion unit, the transmission line The number of one channel is equal to the sum of the number of image channels of the second image signals and the number of the second timing control channels; wherein, the display device and the processing device are two separate devices. The separate display system of claim 6, wherein each of the first timing channels is divided by each of the second timing channels as a ratio, and each of the second clock rates is divided by each The first clock rate is the ratio; the number of each third clock channel divided by the number of each second clock channel is the ratio, and each second clock rate is divided by each third clock The control rate is this ratio. The separate display system of claim 7, wherein the processing device comprises a plurality of first buffers, a plurality of first flip-flops, a plurality of second buffers and a plurality of second flip-flops, the first The buffers and the first flip-flops correspond to the first conversion units one-to-one, the second buffers and the second flip-flops correspond to the second conversion units one-to-one, and each of the first buffers Each of the second image signals comes from the corresponding first conversion unit, and each of the second buffers receives and stores the corresponding second image signal. The corresponding second timing signal, each second timing signal comes from the corresponding second conversion unit, each first flip-flop sends the corresponding second image signal to the transmission line according to an alignment signal, each A second flip-flop sends the corresponding second timing signal to the transmission line according to the alignment signal. The separate display system of claim 7, wherein the processing device comprises a plurality of first buffers and a plurality of first flip-flops, a plurality of second buffers and a plurality of second flip-flops, the first The buffers and the first flip-flops correspond to the first conversion units one-to-one, the second buffers and the second flip-flops correspond to the second conversion units one-to-one, and each of the first buffers Each of the first image signals comes from the processing unit, each of the second buffers respectively receives and stores the corresponding first timing signal, and each of the first The timing signal comes from the processing unit, each of the first flip-flops sends the corresponding first image signal to the corresponding first conversion unit according to an alignment signal, and each of the second flip-flops sends the corresponding The first timing signal is sent to the corresponding second conversion unit. The split display system of claim 8 or 9, wherein the display device comprises a plurality of third buffers, a plurality of third flip-flops, a plurality of fourth buffers and a plurality of fourth flip-flops, the The third buffers and the third flip-flops correspond to the third conversion units one-to-one, the fourth buffers and the fourth flip-flops correspond to the fourth conversion units one-to-one, each of the first The three buffers respectively receive and store the corresponding third image signal, each of the third image signals comes from the corresponding third conversion unit, and each of the fourth buffers respectively receives and stores the corresponding second timing signal , each of the second timing signals comes from the corresponding fourth conversion unit, and each of the third flip-flops sends the corresponding third image according to another alignment signal The signal is sent to the display unit, each of the fourth buffers stores the corresponding second timing signal, and each of the fourth flip-flops sends the corresponding third timing signal to the display unit according to the other alignment signal.

Images