TWI760477B - Schottky-cmos asynchronous logic cells - Google Patents

Abstract

Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

Description

Schottky Complementary Metal-Oxygen Semi-Asynchronous Logic Cell

This application relates to semiconductor devices and circuits, and more particularly to analog, digital, and mixed-signal integrated circuits (ICs) employing supercomplementary metal-oxide-semiconductor (SCMOS ^™ ) devices and thereby exhibit improved device performance due to improvements in power consumption, operating speed, circuit area, and device density.

Since the introduction of integrated circuits (ICs), engineers have been trying to increase the density of circuits on ICs, which reduces the cost of manufacturing such ICs. One approach is to place more components/functions on one wafer. A second approach is to build more chips on a larger wafer to reduce IC cost. For example, silicon wafer size has grown from an average of 3 inches in diameter in the 1960s to 12 inches today. Various attempts have been made in the past to improve IC functionality, performance and cost figures. Early IC implementations used bipolar junction transistors (BJTs) with vertically stacked layers of various diffusion regions and containing three switching terminals (base, emitter, and collector). ) and other resistive (R) and capacitive (C) circuit elements. However, IC implementations from the last decade have used V-I signal and PHY parameter scaling to fit more components on a single chip. CMOS technology emerged after and surpassed BJT technology, which is relatively bulky, provides poor transistor yields, and exhibits high DC power usage. Device complexity has grown to exceed billions of circuit elements with complementary MOS (CMOS) configurations. One of the cost reductions and increases in performance of CMOS technology has been achieved for more than 30 years by shrinking the physical size of CMOS transistors. These dimensions have been scaled down to a size where the critical device parameter is one of several molecular layer thicknesses. However, further shrinking of CMOS is violating the constraints imposed by the laws of physics. In addition to attempting to fabricate tens of billions of these CMOS circuit elements with "molecular" dimensions, these significantly smaller circuits operate at very low signal (voltage) levels, making their signal integrity susceptible to noise and causing Speed degradation and or power/heat outflow.

In various embodiments, Schottky CMOS (also referred to herein as "Super CMOS" and SCMOS ^™ ) technology is employed using Schottky barrier diodes (SBDs) such as low threshold Schottky barrier diodes (LtSBD ^™ )) to build circuit blocks, thereby addressing the above disadvantages and problems associated with an increased need for higher semiconductor efficiencies and upcoming physical limitations on CMOS transistor size. In certain embodiments, an integrated circuit implements a NAND gate system. The integrated circuit includes: a first input coupled to a cathode of a first p-type Schottky diode; and x additional inputs coupled to one of the x additional p-type Schottky diodes x respective cathodes. The integrated circuit additionally includes a first n-type transistor including a gate node coupled to an anode of the first Schottky diode and the x additional x individual anodes of the Schottky diode. The integrated circuit additionally includes a p-type transistor including a gate node coupled to the anode of the first Schottky diode and the x additional Schottky diodes x individual anodes of the polar body. The integrated circuit additionally includes: a second n-type transistor including a gate node coupled to the cathode of the first p-type Schottky diode; and x additional n-type transistors A crystal comprising x respective gate nodes coupled to the x respective cathodes of the x additional p-type Schottky diodes. An output is coupled to a non-gate node of the first n-type transistor and a non-gate node of the p-type transistor. In some embodiments, an integrated circuit implements a NOR gate system. The integrated circuit includes: a first input coupled to an anode of a first n-type Schottky diode; and x additional inputs coupled to one of the x additional n-type Schottky diodes x individual anodes. The integrated circuit additionally includes a first p-type transistor including a cathode coupled to the first n-type Schottky diode and the x additional n-type Schottky diodes A gate node of one of the cathodes of the body. The integrated circuit additionally includes an n-type transistor including the cathode coupled to the first n-type Schottky diode and the x additional n-type Schottky diodes A gate node of the cathode. The integrated circuit additionally includes: a second p-type transistor including a gate node coupled to the anode of the first n-type Schottky diode; and x additional p-type transistors including x respective gate nodes of the x respective anodes coupled to the x additional n-type Schottky diodes. An output is coupled to a non-gate node of the first p-type transistor and a non-gate node of the n-type transistor. In some embodiments, an integrated circuit implements an x-input logic gate. The integrated circuit includes: a plurality of Schottky diodes including x Schottky diodes; and a plurality of source follower transistors including x source follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected in series to a second source-follower transistor of the plurality of source-follower transistors. Various advantages of the disclosed techniques will become apparent in view of the following description.

Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of one of the subject matter presented herein. It will be apparent, however, to those skilled in the art that subject matter may be practiced or designed without these specific details. In other instances, well-known methods, procedures, components, circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments. Trademarks designated by the "TM" symbol in this document are the property of Schottky LSI Co., Ltd. The technical solution of the present invention will be explained in detail and completely below with reference to the accompanying drawings. It will be apparent that the embodiments to be described are examples and only some but not all of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention should fall within the scope of protection of the present invention. The Schottky CMOS technology described herein uses a Schottky barrier diode (also referred to herein as "SBD" and "Schottky diode") to implement logic. In contrast to previous CMOS implementations, the various embodiments of Schottky CMOS described herein use Schottky diodes in place of p-type metal oxide semiconductor (PMOS) field effect transistors and/or n-type metal oxide semiconductors (NMOS) field effect transistor. Specifically, as the number of logic inputs to logic gates increases, replacing PMOS and NMOS transistors with Schottky diodes can increase the efficiency of the implemented logic in various ways, including reducing area consumed by circuit layout, reducing propagation delays and reduce the power required for switching. The following description is presented to enable those skilled in the art to make and use the invention provided in the context of a patent application and its claims. Various modifications to the preferred embodiment and the general principles and features set forth herein will be readily apparent to those skilled in the art. Therefore, the present invention is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features set forth herein. As can be understood by those skilled in the art, in FIGS. 1-8 and 12A-12G, V _SS indicates the source supply voltage, V _DD indicates the drain supply voltage, and V _OUT indicates the output voltage. 1 is a circuit diagram of a 2-input Schottky CMOS NAND gate in accordance with one of certain embodiments. The 2-input Schottky CMOS NAND gate includes two p-type Schottky diodes 102 and 104 and a source follower tree 106 including two n-type transistors 108 and 110 . The transistors in source follower tree 106 are connected in series, as indicated by connection 112 . Input A0 is coupled to a cathode of p-type Schottky barrier diode (SBD) 102 and to a gate node of n-type transistor 108 . Input A1 is coupled to a cathode of p-type SBD 104 and a gate node of n-type transistor 110 . An anode of SBD 102 and an anode of SBD 104 are coupled to the gates of result transistors 114 and 116 . The resulting transistor 114 is an n-type transistor and the resulting transistor 116 is a p-type transistor. Output 118 is coupled to the non-gate nodes of result transistors 114 and 116 . Specifically, output 118 is coupled to the drain node of n-type transistor 114 and output 118 is coupled to the drain node of p-type transistor 116 . In some embodiments, the 2-input Schottky CMOS NAND gate includes feedback logic that receives the output signal as one input at the gate nodes of n-type transistor 120 and p-type transistor 122 . While a CMOS implementation of a 2-input NAND gate would use a p-type transistor and an n-type transistor coupled to each input of the NAND gate, in some embodiments, a 2-input NAND gate Schottky CMOS Implementations use a p-type SBD coupled to each input and an n-type transistor (a p-type SBD in a Schottky CMOS implementation replaces one p-type transistor in a CMOS implementation). As the number of inputs in the NAND gate increases, the efficiency achieved by replacing transistors with SBDs increases, eg, as illustrated by the CMOS and Schottky CMOS performance comparisons of Figures 9-11. 2 is a circuit diagram of an 8-input Schottky CMOS NAND gate according to some embodiments. The 8-input Schottky CMOS NAND gate includes 8 p-type Schottky diodes 202-216 and a source follower tree 218 including 8 n-type transistors 220-234. Transistors 220-234 in source follower tree 218 are connected in series (eg, the drain node of transistor 220 is coupled to the source node of transistor 224, and the drain node of transistor 224 is coupled to the source of transistor 228 pole nodes, etc.). Input A0 is coupled to a cathode of p-type SBD 202 and to a gate node of n-type transistor 220 . Input A1 is coupled to a cathode of p-type SBD 204 and a gate node of n-type transistor 222 . Input A2 is coupled to a cathode of p-type SBD 206 and to a gate node of n-type transistor 224 . Input A3 is coupled to a cathode of p-type SBD 208 and a gate node of n-type transistor 226 . Input A4 is coupled to a cathode of p-type SBD 210 and to a gate node of n-type transistor 228 . Input A5 is coupled to a cathode of p-type SBD 212 and a gate node of n-type transistor 230 . Input A6 is coupled to a cathode of p-type SBD 214 and to a gate node of n-type transistor 232 . Input A7 is coupled to a cathode of p-type SBD 216 and a gate node of n-type transistor 234 . The anodes of SBDs 202-216 are coupled to the gates of result transistors 236 and 238. The resulting transistor 236 is an n-type transistor and the resulting transistor 238 is a p-type transistor. Output 240 is coupled to the non-gate nodes of result transistors 236 and 238 . Specifically, output 240 is coupled to the drain node of n-type transistor 236 and output 240 is coupled to the drain node of p-type transistor 238 . In some embodiments, the 8-input Schottky CMOS NAND gate includes feedback logic that receives the output signal as one input at the gate nodes of n-type transistor 242 and p-type transistor 244 . It will be appreciated that the scaling illustrated with respect to Figures 1-2 can be extended to other numbers of NAND gate inputs. For each additional input, an additional SBD is coupled to the additional input, and an additional source follower transistor complementary to the SBD (eg, an n-type transistor complementary to a p-type SBD) is added to the source follower A tree (eg, as illustrated by source-follower tree 106 of FIG. 1 or source-follower tree 218 of FIG. 2 ). The additional input is coupled to the additional SBD (eg, to the cathode of a p-type SBD) and to the gate node of the additional source follower transistor. An additional SBD (eg, the anode of a p-type SBD) is coupled to the gate nodes of a set of resultant transistors (eg, as illustrated by resultant transistors 114-116 of FIG. 1 or resultant transistors 236-238 of FIG. 2) . For example, a 4-input Schottky CMOS NAND gate includes 4 inputs A0-A3, four p-type SBDs (eg, configured as illustrated by SBDs 202-208 of FIG. 2), and 4 n-type transistors A crystal (eg, the transistors illustrated at 220, 222, 224, and 226 of FIG. 2 connected in series). In some embodiments, a Schottky CMOS NAND gate includes between 2 and 16 inputs, such as 12 inputs. Figure 3 is a circuit diagram of an 8-input CMOS NAND gate. A CMOS 8-input NAND gate requires three NAND gates 302 , 304 and 306 , a NOR gate 308 and inverters 310 and 312 . The stacked configuration of NAND gates 302 - 306 fed into NOR gate 308 (as shown in FIG. 3 ) requires increased power and increased supply compared to the Schottky CMOS 8-input NAND gates described with respect to FIG. 2 current, and results in an increased layout area, increased switching time, and increased propagation delay (as described further below with respect to FIGS. 9-12). 4 is a circuit diagram of a 2-input Schottky CMOS NOR gate according to some embodiments. The 2-input Schottky CMOS NOR gate includes two n-type Schottky diodes 402 and 404 and a source follower tree 406 including two p-type transistors 408 and 410 . The transistors in the source follower tree 406 are connected in series. Input A0 is coupled to an anode of n-type Schottky barrier diode (SBD) 402 and to a gate node of p-type transistor 408 . Input A1 is coupled to an anode of n-type SBD 404 and a gate node of p-type transistor 410 . A cathode of SBD 402 and a cathode of SBD 404 are coupled to the gates of result transistors 414 and 416 . The resulting transistor 414 is an n-type transistor and the resulting transistor 416 is a p-type transistor. Output 418 is coupled to the non-gate nodes of result transistors 414 and 416 . Specifically, output 418 is coupled to the drain node of n-type transistor 414 and output 118 is coupled to the drain node of p-type transistor 416 . In some embodiments, the 2-input Schottky CMOS NOR gate includes feedback logic that receives the output signal as one input at the gate nodes of n-type transistor 420 and p-type transistor 422 . While a CMOS implementation of a 2-input NOR gate would use a p-type transistor and an n-type transistor coupled to each input of the NOR gate, in some embodiments, a 2-input NOR gate Schottky CMOS Implementations use an n-type SBD coupled to each input and a p-type transistor (in Schottky CMOS implementations an n-type SBD is used to replace one of the n-type transistors in previous CMOS implementations). As the number of inputs in the NOR gate increases, the efficiency achieved by replacing transistors with SBDs increases. 5 is a circuit diagram of an 8-input Schottky CMOS NOR gate according to some embodiments. The 8-input Schottky CMOS NOR gate includes 8 n-type Schottky diodes 502-516 and a source follower tree 518 including 8 p-type transistors 520-534. Transistors 520-534 in source follower tree 518 are connected in series (eg, the drain node of transistor 520 is coupled to the source node of transistor 524, and the drain node of transistor 524 is coupled to the source of transistor 528 pole nodes, etc.). Input A0 is coupled to an anode of n-type SBD 502 and to a gate node of p-type transistor 520 . Input A1 is coupled to an anode of n-type SBD 504 and a gate node of p-type transistor 522 . Input A2 is coupled to an anode of n-type SBD 506 and to a gate node of p-type transistor 524 . Input A3 is coupled to an anode of n-type SBD 508 and a gate node of p-type transistor 526 . Input A4 is coupled to an anode of n-type SBD 510 and to a gate node of p-type transistor 528 . Input A5 is coupled to an anode of n-type SBD 512 and a gate node of p-type transistor 530 . Input A6 is coupled to an anode of n-type SBD 514 and to a gate node of p-type transistor 532 . Input A7 is coupled to an anode of n-type SBD 516 and a gate node of p-type transistor 534 . SBDs 502-516 are cathode coupled to the gates of result transistors 536 and 538. The resulting transistor 536 is an n-type transistor and the resulting transistor 538 is a p-type transistor. Output 540 is coupled to the non-gate nodes of result transistors 536 and 538 . Specifically, output 540 is coupled to the drain node of n-type transistor 536 and output 540 is coupled to the drain node of p-type transistor 538 . In some embodiments, the 8-input Schottky CMOS NOR gate includes feedback logic that receives the output signal as one input at the gate nodes of n-type transistor 542 and p-type transistor 544 . It will be appreciated that the scaling illustrated with respect to Figures 4-5 can be extended to other numbers of NOR gate inputs. For each additional input, an additional SBD is coupled to the additional input, and an additional source follower transistor complementary to the SBD (eg, a p-type transistor complementary to an n-type SBD) is added to the source follower A tree (eg, as illustrated by source-follower tree 406 of FIG. 4 or source-follower tree 518 of FIG. 5 ). The additional input is coupled to the additional SBD (eg, to the cathode of an n-type SBD) and to the gate node of the additional source follower transistor. An additional SBD (eg, the anode of a p-type SBD) is coupled to the gate nodes of a set of resultant transistors (eg, as illustrated by resultant transistors 414-416 of FIG. 4 or resultant transistors 536-538 of FIG. 5 ) ). For example, a 4-input Schottky CMOS NOR gate includes 4 inputs A0-A3, 4 n-type SBDs (eg, configured as illustrated by SBDs 502-508 of Figure 5), and 4 p-type transistors (eg, as the transistors illustrated in 520, 522, 524, and 526 of FIG. 5 connected in series). In some embodiments, a Schottky CMOS NOR gate includes between 2 and 16 inputs, such as 12 inputs. Figure 6 is a circuit diagram of an 8-input CMOS NOR gate. A CMOS 8-input NOR gate requires four 2-input NOR gates 602, 604, 606 and 608; two 2-input NAND gates 610 and 612; a 2-input NOR gate 614; and inverters 616 and 618. Compared to the Schottky CMOS 8-input NOR gates described with respect to FIG. 5, the stacked configuration of NOR gates 602-608 fed to NAND gates 610 and 612 relayed to NOR gate 614 (as shown in FIG. 6) ) requires increased power and increased supply current, and results in an increased layout area, increased switching time, and increased propagation delay. 7 is a circuit diagram of a Schottky CMOS implementation of a 4-to-1 multiplexer circuit (MUX) in accordance with certain embodiments. A Schottky CMOS MUX couples input I1 to a p-type SBD 702 and a gate node of an n-type transistor 704 . Inputs I2, I3 and I4 are similarly each coupled to a p-type SBD and a gate node of an n-type transistor. The output of p-type SBD 702 and transistor 704 are coupled to n-type SBD 706 and a p-type transistor 708 . The outputs and transistors of the SBDs receiving inputs from I2, I3, and I4 are similarly coupled to an n-type SBD and a p-type transistor, respectively. The output of the n-type SBD is coupled to a gate node of a p-type result transistor 710 and a gate node of an n-type result transistor 712 . The output of the resulting transistor is received by output 714 (labeled "Y"). In FIGS. 7-8, I31, I31N, I32, and I32N denote nodes of respective circuits. S1 and S2 are source voltages, which are used for circuits that provide reference voltages to nodes I31, I31N, I32, and I32N. Figure 8 illustrates a CMOS implementation of a 4-to-1 multiplexer circuit. In certain embodiments, the Schottky CMOS logic described with respect to FIGS. 1, 2, 4, 5, and/or 7 is configured for asynchronous (eg, static) operation. For example, a size of one or more components is selected such that the operation of the circuit is asynchronous or substantially asynchronous. In certain embodiments, the size of one or more components of the Schottky CMOS logic is selected to reduce and/or minimize switching noise immunity. In certain embodiments, one or more SBDs of the Schottky CMOS logic described with respect to FIGS. 1, 2, 4, 5, and/or 7 have a threshold forward voltage that is positive The forward voltage is below the threshold forward voltage of a transistor with a gate coupled to a SBD (eg, where both the transistor and the SBD are coupled to an input of the gate). For example, referring to FIG. 1 , in some embodiments, SBD 102 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 108 and/or SBD 104 has a threshold that is lower than transistor 110 Forward Voltage One of the threshold forward voltages. Referring to FIG. 2, in some embodiments, SBD 202 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 220 and SBD 204 has a threshold forward voltage that is lower than that of transistor 222. limit forward voltage, and/or SBD 206 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 224, and/or the like. 4, in some embodiments, SBD 402 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 408 and/or SBD 404 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 410. a threshold forward voltage. 5, in some embodiments, SBD 502 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 520 and SBD 504 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 522. limit forward voltage, and/or SBD 506 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 524, and/or the like. Referring to FIG. 7 , in some embodiments, SBD 702 has a threshold forward voltage that is lower than the threshold forward voltage of transistor 704 . 9 is a comparison of the layout area of a NAND gate implemented using Schottky CMOS (eg, as shown in FIGS. 1-2 ) to the layout area of a NAND gate implemented using CMOS (eg, as shown in FIGS. 1-2 ), according to certain embodiments 3) one of the diagrams. As can be seen from Figure 9, the area of Schottky CMOS NAND gates increases at a lower rate than the area of CMOS NAND gates increases as the number of inputs increases. FIG. 9 indicates that a layout area required for a 4-input Schottky CMOS NAND gate is less than 2.0 μm ² , which is significantly less than the area required for a 4-input CMOS NAND gate. The reduction in area required for a Schottky CMOS NAND gate with three or more inputs compared to a CMOS NAND gate with the same number of inputs is due, for example, to the signal lines and/or circuits required to implement the logic One of the reductions in the number of nets and a source follower tree (eg, as shown at 106, 218, 406, and 518) compared to the layout of CMOS NAND gates (eg, as shown at Figures 3 and 6) relatively small size. 10 is a comparison of root mean square (RMS) power consumption of a NAND gate implemented using Schottky CMOS (eg, as shown in FIGS. 1-2 ) with a NAND gate implemented using CMOS (eg, as shown in FIGS. 1-2 ), according to certain embodiments For example, as shown in Figure 3) a graph of power consumption. As can be seen from Figure 10, the power required for Schottky CMOS NAND gates increases at a lower rate than the power required for CMOS NAND gates increases as the number of inputs increases. Figure 10 indicates that the RMS power requirement for a 4-input Schottky CMOS NAND gate is less than 50.0 microwatts, which is significantly less than the power required for a 4-input CMOS NAND gate. 11 is the propagation delay of a NAND gate implemented using Schottky CMOS (eg, as shown in FIGS. 1-2 ) and a NAND gate implemented using CMOS (eg, as shown in FIG. 3 ), according to certain embodiments ) is a graph of the propagation delay. Figure 11 indicates that a 4-input Schottky CMOS NAND gate has a propagation delay of less than 80 picoseconds, which is significantly less than the propagation delay of a 4-input CMOS NAND gate. As can be seen from Figure 11, the propagation delay of CMOS NAND gates exhibits a particularly pronounced increase as the number of inputs increases from 3 to 4 inputs and from 6 to 7 inputs. The significant increase in required area, power consumption, and propagation delay that occurs in CMOS implementations of NAND gates as the number of inputs increases can be understood with reference to FIGS. 12A-12G. 12A-12G illustrate CMOS implementations of NAND gates with various numbers of inputs. 12A illustrates 2-input NAND logic implemented using a single 2-input NAND gate 1202. 12B illustrates 3-input NAND logic implemented using a single 3-input NAND gate 1204. FIG. 12C illustrates 4-input NAND logic implemented using two NAND gates 1206 and 1208 and one NOR gate 1210 . When the number of NAND inputs is increased from 3 inputs (as shown in FIG. 12B ) to 4 inputs (as shown in FIG. 12C ), two NAND gates 1206 and 1208 are used (instead of the single NAND gate 1204 of FIG. 12B ) ) and adding a NOR gate 1210 increases the propagation delay through the circuit. This increase is reflected in the jump from a propagation delay of less than 80 picoseconds for a 3-input CMOS NAND to a propagation delay of more than 120 picoseconds for a 4-input CMOS NAND, as shown in FIG. 11 . 12D-12E illustrate 5-input CMOS NAND gates and 6-input CMOS NAND gates, respectively. Like the 4-input CMOS NAND shown in Figure 12C, the 5-input CMOS NAND gate and the 6-input CMOS NAND gate feed the outputs of the two NAND gates to a NOR gate. The CMOS NAND gates of FIG. 12D feed the outputs of NAND gates 1212 and 1214 to NOR gate 1216 . The CMOS NAND gate of FIG. 12E feeds the outputs of NAND gates 1218 and 1220 to NOR gate 1222. 12F illustrates a 7-input NAND logic implemented using three NAND gates 1224, 1226 and 1228 and one NOR gate 1230. When the number of NAND inputs is increased from 6 inputs (as shown in Figure 12E) to 7 inputs (as shown in Figure 12F), three NAND gates (1224, 1226 and 1228) are used instead of the two of Figure 12E Multiple NAND gates (1218, 1220) increase the propagation delay through the circuit. This increase is reflected in the jump from a propagation delay of less than 140 picoseconds for a 6-input CMOS NAND to a propagation delay of nearly 180 picoseconds for a 7-input CMOS NAND, as shown in FIG. 11 . FIG. 12G illustrates an 8-input CMOS NAND gate having a circuit structure similar to the 8-input CMOS NAND gate described with respect to FIG. 3 . The CMOS NAND gates of FIG. 12G feed the outputs of NAND gates 1232 , 1234 and 1236 to NOR gate 1238 . 12A to 12G, C2YN, C3YN, C4YN, C5YN, C6YN, C7YN and C8YN indicate the outputs of the respective circuits, and C2Y, C3Y, C4Y, C5Y, C6Y, C7Y and C8Y indicate the inversions of the respective circuits output. As explained above with respect to the CMOS NAND gates of Figures 12A-12G, increasing the number of inputs of the CMOS NAND gates requires adding several NAND gates and/or adding a NOR stage. In certain embodiments (eg, as described with respect to FIGS. 1-2 and 4-5), increasing the number of inputs of a Schottky CMOS NAND gate includes increasing the number of SBDs and increasing a source follower A number of corresponding transistors in the coupler tree. In certain embodiments, the Schottky CMOS approach described herein results in a lower increase in circuit consumption, layout area, and propagation delay as the number of logic inputs increases compared to the CMOS approach. While specific embodiments are described above, it will be understood that it is not intended to limit the invention to these specific embodiments. On the contrary, the present invention includes alternatives, modifications and equivalents falling within the spirit and scope of the appended claims. Numerous specific details are set forth in order to provide a thorough understanding of one of the subject matter presented herein. It will be apparent to those skilled in the art, however, that the present subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in the description of the present disclosure and the appended claims, the singular forms "a/an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items. It will be further understood that when used in this specification, the terms "includes", "including", "comprises" and/or "comprising" specify the presence of stated features, operations, elements and/or components, but does not preclude the presence or addition of one or more other features, operations, elements, components and/or groups thereof. As used herein, depending on the context, the phrase "if a stated prerequisite is true" can be interpreted to mean "when a stated prerequisite is true" or "when a stated prerequisite is true""immediatelyafter" or "in response to a determination that a stated precondition is true" or "according to one of the stated preconditions to be true" or "in response to detecting that a stated precondition is true". Similarly, depending on context, the phrase "if it is determined that [a stated prerequisite is true]" or "if [a stated prerequisite is true]" or "when [a stated prerequisite is true]" ] can be construed to mean "immediately after it is determined that the stated preconditions are correct" or "in response to determining that the stated preconditions are correct" or "according to one of the stated preconditions to be correct" or " Immediately after detecting that the stated prerequisite is true" or "in response to detecting that the stated prerequisite is true". For purposes of illustration, the foregoing description has been set forth with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Numerous modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable those skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. Example.

102‧‧‧p-type Schottky diode104‧‧‧p-type Schottky diode/p-type Schottky barrier diode/Schottky barrier diode106‧‧‧source follower coupling Device Tree 108‧‧‧N-Type Transistor/Transistor 110‧‧‧N-Type Transistor/Transistor 112‧‧‧Connection 114‧‧‧Result Transistor/n-Type Transistor 116‧‧‧Result Transistor/p Type Transistor 118‧‧‧Output120‧‧‧N-Type Transistor122‧‧‧p-Type Transistor202‧‧‧p-Type Schottky Diode/Schottky Barrier Diode204‧‧‧p-Type Schottky Diode/Schottky Barrier Diode206‧‧‧p-Type Schottky Diode/Schottky Barrier Diode208‧‧‧p-Type Schottky Diode/Schottky Barrier Diode 210‧‧‧p-Type Schottky Diode/Schottky Barrier Diode 212‧‧‧p-Type Schottky Diode/Schottky Barrier Diode 214‧‧‧p-Type Schottky Diodes/Schottky Barrier Diodes 216‧‧‧p-Type Schottky Diodes/Schottky Barrier Diodes 218‧‧‧Source Follower Trees 220‧‧‧N-Type Transistor/Transistor 222‧‧‧N-Type Transistor/Transistor 224‧‧‧N-Type Transistor/Transistor 226‧‧‧N-Type Transistor/Transistor 228‧‧‧N-Type Transistor/Transistor 230 ‧‧‧n-type transistor/transistor 232‧‧‧n-type transistor/transistor 234‧‧‧n-type transistor/transistor 236‧‧‧resultant transistor/n-type transistor 238‧‧‧resultant transistor Crystal/p-type transistor 240‧‧‧Output 242‧‧‧n-type transistor 244‧‧‧p-type transistor 302‧‧‧NAND gate 304‧‧‧NAND gate 306‧‧‧NAND gate 308‧‧‧NOR Gate 310‧‧‧Inverter 312‧‧‧Inverter 402‧‧‧N-Type Schottky Diode/n-Type Schottky Barrier Diode/Schottky Barrier Diode 404‧‧‧n Type Schottky Diode/n-Type Schottky Barrier Diode/Schottky Barrier Diode 406‧‧‧Source Follower Tree 408‧‧‧p-Type Transistor/Transistor 410‧‧‧ p-type transistor/transistor 414‧‧‧resultant transistor/n-type transistor 416‧‧‧resulting transistor/p-type transistor 418‧‧‧output 420‧‧‧n-type transistor 422‧‧‧p-type Transistor 502‧‧‧N-Type Schottky Diode/n-Type Schottky Barrier Diode/Schottky Barrier Diode 504‧‧‧N-Type Schottky Diode/n-Type Schottky Diode Barrier Diodes/Schottky Barrier Diodes506‧‧‧N-Type Schottky Diodes/N-Type Schottky Barrier Diodes/Schottky Barrier Diodes508‧‧‧n-Type Schottky Diodes Base Diode/n-Type Schottky Barrier Diode/Schottky Barrier Diode510‧‧‧n-Type Schottky Diode/n-Type Schottky Barrier Diode/Schottky Barrier Diode Pole Body 512‧‧‧N-Type Schottky Diode/n-Type Schottky Barrier Diode/Schottky Barrier Diode 514‧‧‧n-Type Schottky Diode/n-Type Schottky Diode Base Barrier Diode/Schottky Barrier Diode 516‧‧‧N-Type Schottky Diode/N-Type Schottky Barrier Diode/Schottky Barrier Diode 518‧‧‧Source Follower Coupler tree520‧‧‧p-type transistor/transistor522‧‧‧p-type transistor/transistor524‧‧‧p-type transistor/transistor526‧‧‧p-type transistor/transistor528‧‧ ‧p-type transistor/transistor 530‧‧‧p-type transistor/transistor 532‧‧‧p-type transistor/transistor 534‧‧‧p-type transistor/transistor 536‧‧‧resultant transistor/n Type Transistor 538‧‧‧Result Transistor/p Type Transistor 540‧‧‧Output 542‧‧‧N Type Transistor 544‧‧‧P Type Transistor 602‧‧‧2 Input NOR Gate 604‧‧‧2 Input NOR gate 606‧‧‧2 input NOR gate 608‧‧‧2 input NOR gate 610‧‧‧2 input NAND gate/NAND gate 612‧‧‧2 input NAND gate/NAND gate 614‧‧‧2 input NOR gate/NOR Gate 616‧‧‧Inverter 618‧‧‧Inverter 702‧‧‧P-Type Schottky Barrier Diode/Schottky Barrier Diode 704‧‧‧N-Type Transistor/Transistor 706‧‧ ‧N-Type Schottky Barrier Diode 708‧‧‧P-Type Transistor 710‧‧‧P-Type Resulting Transistor 712‧‧‧N-Type Resulting Transistor 714‧‧‧Output 1202‧‧‧2 Input NAND Gate 1204 ‧‧‧3 input NAND gate/NAND gate 1206‧‧‧NAND gate 1208‧‧‧NAND gate 1210‧‧‧NOR gate 1212‧‧‧NAND gate 1214‧‧‧NAND gate 1216‧‧‧NOR gate 1218‧‧‧ NAND gate 1220‧‧‧NAND gate 1222‧‧‧NOR gate 1224‧‧‧NAND gate 1226‧‧‧NAND gate 1228‧‧‧NAND gate 1230‧‧‧NOR gate 1232‧‧‧NAND gate 1234‧‧‧NAND gate 1236‧‧‧NAND gate 1238‧‧‧NOR gate A0‧‧‧input A1‧‧‧input A2‧‧‧input A3‧‧‧input A4‧‧‧input A5‧‧‧input A6‧‧‧input A7‧‧ ‧Input C2Y‧‧‧Inverted output C2YN‧‧‧Output C3Y‧‧‧Inverted output C3YN‧‧‧Output C4Y‧‧‧Inverted output C4YN‧‧‧Output C5Y‧‧‧Inverted output C5YN‧‧‧Output C6Y‧‧‧Inverting output C6YN‧‧‧Output C7Y‧‧‧Inverting output C7YN‧‧‧Output C8Y‧‧‧Inverting output C8YN‧‧‧Output I1‧‧‧Input I2‧‧‧Input I3‧‧‧ Input I4‧‧‧Input I31‧‧‧Node I31N‧‧‧Node I32‧‧‧Node I32N‧‧‧Node S1‧‧‧Source Voltage S2‧‧‧Source Voltage V _DD ‧‧‧Drain Supply Voltage V _OUT ‧‧ ‧Output voltage V _SS ‧‧‧Source supply voltage

The foregoing features and advantages of the present invention, as well as additional features and advantages thereof, will be clearly understood from the following detailed description of one of the preferred embodiments when taken in conjunction with the accompanying drawings. In order to illustrate the technical solutions according to the embodiments of the present invention more clearly, the accompanying drawings required for the embodiments are briefly introduced below. However, the drawings illustrate only the more relevant features of the invention and are therefore not to be regarded as limiting, as the description may admit other effective features. 1 is a circuit diagram of a 2-input Schottky CMOS NAND gate in accordance with one of certain embodiments. 2 is a circuit diagram of an 8-input Schottky CMOS NAND gate according to some embodiments. Figure 3 is a circuit diagram of an 8-input CMOS NAND gate. 4 is a circuit diagram of a 2-input Schottky CMOS NOR gate according to some embodiments. 5 is a circuit diagram of an 8-input Schottky CMOS NOR gate according to some embodiments. Figure 6 is a circuit diagram of an 8-input CMOS NOR gate. 7 is a circuit diagram of a Schottky CMOS implementation of a 4-to-1 multiplexer circuit in accordance with certain embodiments. Figure 8 illustrates a CMOS implementation of a 4-to-1 multiplexer circuit. 9 is a graph comparing the layout area of a NAND gate implemented using Schottky CMOS to the layout area of a NAND gate implemented using CMOS, according to certain embodiments. 10 is a graph comparing the root mean square (RMS) power consumption of a NAND gate implemented using Schottky CMOS to the power consumption of a NAND gate implemented using CMOS, according to certain embodiments. 11 is a graph comparing the propagation delay of NAND gates implemented using Schottky CMOS to the propagation delays of NAND gates implemented using CMOS, according to certain embodiments. 12A-12G illustrate CMOS implementations of NAND gates with various numbers of inputs. Throughout the several views of the drawings, the same reference numerals refer to corresponding parts.

102‧‧‧p-type Schottky diode

104‧‧‧p-type Schottky diode/p-type Schottky barrier diode/Schottky barrier diode

106‧‧‧Source Follower Tree

108‧‧‧n-type transistor/transistor

110‧‧‧n-type transistor/transistor

112‧‧‧Connection

114‧‧‧Result transistor/n-type transistor

116‧‧‧Result transistor/p-type transistor

118‧‧‧Output

120‧‧‧n-type transistor

122‧‧‧p-type transistor

A0‧‧‧input

A1‧‧‧Input

V _DD ‧‧‧Drain Supply Voltage

V _OUT ‧‧‧Output voltage

V _SS ‧‧‧Source Supply Voltage

Claims (19)

An integrated circuit implementing a NAND gate system, the integrated circuit comprising: a first input coupled to a cathode of a first p-type Schottky diode; x additional inputs coupled to x x respective cathodes of additional p-type Schottky diodes; a first n-type transistor including a gate node coupled to one of the first p-type Schottky diodes an anode and x respective anodes of the x additional p-type Schottky diodes; and a p-type transistor including a gate node coupled to the first p-type Schottky diode the anode of the pole body and the x respective anodes of the x additional p-type Schottky diodes; a second n-type transistor including a gate node coupled to the first p the cathode of a type Schottky diode; and x additional n-type transistors including x respective gate nodes coupled to the x additional p-type Schottky diodes the x respective cathodes of the pole body; wherein an output is coupled to a non-gate node of the first n-type transistor and a non-gate node of the p-type transistor. The integrated circuit of claim 1, wherein a threshold forward voltage of the first p-type Schottky diode is less than a threshold voltage of the second n-type transistor. The integrated circuit of claim 1, wherein: a threshold forward voltage of a respective p-type Schottky diode of one of the x additional p-type Schottky diodes is less than the x additional n-type diodes a threshold forward voltage of a respective n-type transistor in one of the transistors, and A respective one of the x additional inputs is coupled to the respective p-type Schottky diode and the respective n-type transistor. The integrated circuit of claim 1, wherein a threshold forward voltage of the first p-type Schottky diode is less than a threshold voltage of the first n-type transistor. The integrated circuit of claim 1, wherein a threshold forward voltage of the first p-type Schottky diode is less than a threshold voltage of the p-type transistor. 5. The integrated circuit of any one of claims 1 to 5, wherein the integrated circuit is configured for asynchronous operation. 5. The integrated circuit of any one of claims 1 to 5, wherein the x additional n-type transistors comprise a second n-type transistor connected in series with a third n-type transistor. The integrated circuit of any one of claims 1 to 5, wherein x is greater than or equal to 4. The integrated circuit of claim 8, wherein a propagation delay of the integrated circuit is less than 80 picoseconds. The integrated circuit of claim 8, wherein a required layout area of the integrated circuit is less than 2.0 μm ² . The integrated circuit of claim 8, wherein the root mean square (RMS) power required by the integrated circuit is less than 50 microwatts (microwatts). An integrated circuit implementing a NOR gate system, the integrated circuit comprising: a first input coupled to an anode of a first n-type Schottky diode; x additional inputs coupled to x x respective anodes of additional n-type Schottky diodes; a first p-type transistor including a gate node coupled to one of the first n-type Schottky diodes a cathode and a cathode of the x additional n-type Schottky diodes; and an n-type transistor including a gate node coupled to the first n-type Schottky diode the cathode and the cathodes of the x additional n-type Schottky diodes; a second p-type transistor including a gate node coupled to the first n-type Schottky diode the anode of the pole body; and x additional p-type transistors including x respective gate nodes coupled to the x of the x additional n-type Schottky diodes respective anodes; wherein an output is coupled to a non-gate node of the first p-type transistor and a non-gate node of the n-type transistor. The integrated circuit of claim 12, wherein a threshold forward voltage of the first n-type Schottky diode is less than a threshold voltage of the second p-type transistor. The integrated circuit of claim 12, wherein: a threshold forward voltage of a respective n-type Schottky diode of one of the x additional n-type Schottky diodes is less than the x additional p-type A threshold forward current of a respective p-type transistor in one of the transistors voltage, and a respective one of the x additional inputs is coupled to the respective n-type Schottky diode and the respective p-type transistor. The integrated circuit of any of claims 12 to 14, wherein the integrated circuit is configured for asynchronous operation. The integrated circuit of any one of claims 12 to 14, wherein the x additional p-type transistors comprise a second p-type transistor connected in series with a third p-type transistor. An integrated circuit implementing an x input logic gate, the integrated circuit comprising: a plurality of Schottky diodes including x Schottky diodes; and a plurality of source follower transistors (source - follower transistors) comprising x source-follower transistors, wherein: each respective source-follower transistor of the plurality of source-follower transistors includes a respective Schottky coupled to A respective gate node of the base diode; and a first source-follower transistor of the plurality of source-follower transistors is connected in series to one of the plurality of source-follower transistors a second source follower transistor. The integrated circuit of claim 17, wherein: a threshold forward voltage of each of the x Schottky diodes is less than that of the x source follower transistors a threshold forward voltage of a respective source follower transistor, and An input of the integrated circuit is coupled to the respective Schottky diode and the respective source follower transistor. The integrated circuit of any one of claims 17 to 18, wherein the integrated circuit is configured for asynchronous operation.

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