TWI755529B - Atomic layer deposition bonding for heterogeneous integration of photonics and electronics - Google Patents

Abstract

Method and systems are presented for heterogeneous integration of photonics and electronics with atomic layer deposition (ALD) bonding. One method includes operations for forming a compound semiconductor and for depositing (e.g. via atomic layer deposition) a continuous film of a protection material (e.g., Al₂O₃) on a first surface of the compound semiconductor. Further, the method includes an operation for forming a silicon on insulator (SOI) wafer, with the SOI wafer comprising one or more waveguides. The method further includes bonding the compound semiconductor at the first surface to the SOI wafer to form a bonded structure and processing the bonded structure. The protection material protects the compound semiconductor from acid etchants during further processing of the bonded structure.

Description

Atomic Layer Deposition Combination of Photonic and Electronic Heterogeneous Integration

The subject matter disclosed herein relates generally to methods and systems for semiconductor fabrication, and more particularly to semiconductor fabrication that includes bonding of heterogeneous materials.

Heterogeneous combining of two different types of materials is becoming more common in optics and electronics for the fabrication of integrated circuits (ICs). This combination takes advantage of the use of materials with specific and different properties combined into a single semiconductor for processing.

For example, silicon-on-insulator (SOI) wafers provide low-loss waveguide routing, while III-V compound semiconductors efficiently generate light for lasers and absorb light efficiently for modulators and detectors used in optical communications. The combination of these materials provides an ideal platform for creating photonic integrated circuits (PICs). Since the materials are different, the combination in the manufacture of these PICs can greatly impact yield and process constraints. For example, in some applications, the goal is to fabricate highly integrated conveyors that are fabricated entirely through wafer-scale processing.

For hybrid silicon photonics, the shear strength of the compound semiconductor-to-silicon substrate bond has a dramatic effect on device yield. Separation and delamination between materials are common challenges to overcome due to the different materials to be combined. Additionally, many acids are used in the fabrication of these devices to etch the compound semiconductor after bonding; however, these acids follow the silicon channel to wick under the compound semiconductor and etch the bonding interface.

102‧‧‧Compound semiconductor wafer

104‧‧‧SOI wafer

106‧‧‧Superlattice

108‧‧‧InP bonding layer

110‧‧‧InGaAs layer

112‧‧‧Quantum Well (QWs) Layer

114‧‧‧InP layer

116‧‧‧SiO ₂ bonding layer

118‧‧‧SiO ₂ layer

120‧‧‧Silicon substrate

122‧‧‧Waveguide

202‧‧‧Compound semiconductor substrate

204‧‧‧Bottom/damage of compound semiconductors

302‧‧‧Compound Semiconductors

304‧‧‧Atomic Layer Deposition (ALD)

306‧‧‧Protective Materials

502‧‧‧Compound Semiconductors

504‧‧‧Combination structure

602‧‧‧Etching

702‧‧‧Screen

704‧‧‧Screen

802‧‧‧ Components

804‧‧‧ Components

806‧‧‧Compound Semiconductors

808‧‧‧Part of compound semiconductor

810‧‧‧Compound Semiconductors

900‧‧‧Method

902-920‧‧‧Operation

1000‧‧‧Method

1002-1010‧‧‧Operation

Each of the drawings, as in the accompanying drawings, describe only exemplary embodiments of the present case, and should not be considered limiting of its scope.

The first figure illustrates the incorporation of heterogeneous materials according to some exemplary embodiments.

A second diagram illustrates damage to compound semiconductors during processing of bonded structures due to the use of acids, according to some example embodiments.

A third diagram illustrates the addition of protective material via atomic layer deposition (ALD) according to some embodiments.

A fourth diagram illustrates the creation of bonded structures by bonding compound semiconductors and SOI wafers, according to some example embodiments.

A fifth figure illustrates compound structures without superlattice, according to some exemplary embodiments.

The sixth figure illustrates how the Al ₂ O ₃ enhanced bonding structure provides better protection during processing according to some example embodiments.

Figure 7 illustrates some results of the improvements obtained by using a protective layer according to some example embodiments.

An eighth graph illustrates the yield enhancement gains obtained with Al ₂ O ₃ layers according to some embodiments.

The ninth figure is a flow chart of the heterointegration method of photons and electrons using ALD bonding.

Tenth Figure is a flow chart illustrating a method for fabricating a bonding structure according to some example embodiments.

Example methods and systems relate to heterogeneous integration of photons and electrons combined using atomic layer deposition (ALD). Examples only represent possible variants. Unless expressly stated otherwise, components and functions are optional and may be combined or subdivided, and operations may be varied or combined or subdivided in sequence. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to one skilled in the art that the subject matter herein may be practiced without these specific details.

Bonded structures have issues that must be addressed during manufacture, such as bond shear strength and acid damage in post-bonding processing. There are solutions to these problems by changing the bonding layer of the III-V semiconductor to InGaAsP, which is more resistant to many acidic etchants. However, this change also reduces shear strength and leads to delamination prior to the acid step. Other options include changes to the acid etch step, element map, or moving back from the III-V edge to the III-V element. However, these solutions do not increase the shear strength of the bond, they increase processing time and cost, and do not fully address the problem of acid wicking. Furthermore, these schemes do not allow reducing the backshift from the III-V edge to the component, thus limiting the reduction in die size.

Embodiments presented in this case provide solutions for bonding SOI wafers with compound semiconductors (eg, semiconductors formed on III-V materials). Embodiments provide bonding surfaces where a thin layer of protective material (eg, Al ₂ O ₃ ) is added to compound semiconductors (eg, III-V-based semiconductors) after growth and prior to the bonding operation. In some examples, the addition of thin layers is performed via ALD, but other deposition methods may also be utilized. Al ₂ O ₃ prevents III-V materials from being affected by acidic etchants after bonding, and also increases the shear strength of the bond (eg, compared to SiO ₂ ). Additionally, the protective material results in fewer defects, higher yields, and provides the ability to fabricate smaller optical circuits while using less material.

One general aspect includes a method comprising the operations of: forming a compound semiconductor; depositing a continuous film of protective material on a first surface of the compound semiconductor; and forming an SOI wafer, wherein the SOI wafer includes one or more waveguides . The method also includes bonding the compound semiconductor at the first surface to the SOI wafer to form a bonded structure, and processing the bonded structure. The protective material protects the compound semiconductor from acidic etchants during processing of the bonded structure.

One general aspect includes a bonded structure comprising: a compound semiconductor including a continuous film of protective material deposited on a first surface of the compound semiconductor; and an SOI wafer. The SOI wafer includes one or more waveguides, wherein a compound semiconductor is bonded to the SOI wafer at a first surface to form a semiconductor structure; the bonded structure can be processed to pattern circuits on the compound semiconductor. The protective material protects the compound semiconductor from acidic etchants during processing of the bonded structure.

A general aspect includes a method comprising the operations of: forming a III-V-based semiconductor; depositing a continuous film of _{Al2O3 on} a first surface of the III-V-based semiconductor; dividing the III-V-based semiconductor to producing an epitaxial die; and plasma cleaning the epitaxial die. The method also includes the operations of: forming an SOI wafer, wherein the SOI wafer includes one or more waveguides; placing the first surface of the epitaxial die on the SOI wafer; bonding the epitaxial die to the SOI wafer to form a bonded structure; remove the substrate of the epitaxial die by grinding and chemical operations; and process the bonded structure, wherein Al ₂ O ₃ protects the epitaxial die from acidic etchants during processing of the bonded structure.

The first figure illustrates the incorporation of heterogeneous materials according to some exemplary embodiments. The first figure shows a cross-section of the compound semiconductor 102 and SOI wafer 104 before bonding together. The SOI wafer 104 or silicon-on-insulator wafer is produced with a silicon substrate 120, a _SiO2 layer 118 on the silicon substrate 120, and a silicon waveguide 122 that provides low-loss routing. Additionally, a SiO ₂ bonding layer 116 is added over the waveguide 122 . SOI wafers are fabricated by forming and patterning silicon waveguides, and then the SOI wafers are plasma cleaned. For simplicity of description, other layers and circuits in the SOI wafer are omitted, but those skilled in the art will readily understand that the SOI wafer may include multiple circuits and layers.

In addition, the compound semiconductor 102 is grown independently. In some exemplary embodiments, compound semiconductor 102 uses type III-V materials (a type of material that can produce high-efficiency lasers, modulators, and detectors).

In some example embodiments, compound semiconductor 102 includes a base of an InP substrate and additional layers are added. In the exemplary embodiment of the first figure, the layers include an InGaAs layer 110 , another InP layer, a quantum well (QWs) layer 112 , another InP layer 114 , a superlattice 106 , and an InP bonding layer 108 .

It should be noted that large III-V semiconductors can be formed and then singulated into multiple epitaxial dies prior to bonding. The epitaxial die is referred to herein as compound semiconductor 102, and the epitaxial die is bonded to an SOI wafer.

The combination of compound semiconductor 102 and SOI wafer 104 is desirable because silicon provides low loss waveguide routing and III-V materials provide efficient optical properties. Because they are different types of materials, the compound semiconductor 102 and the SOI wafer 104 are bonded together. Bonding materials of different oxide types can be used to connect the two semiconductors together.

In some example embodiments, compound semiconductor 102 and SOI wafer 104 are placed together, and pressure and heat are then applied to bond them together. Then, they can be plasma cleaned and further steps can be taken to form circuits on the compound semiconductor 102. That is, at this point, silicon patterning is complete, but III-V patterning is still in progress. In other bonding methods, a polymer (eg, benzocyclobutene, which is often abbreviated as BCB) is used to bond, allowing III-V to link to the silicon using the polymer.

It should be noted that the embodiment illustrated in the first figure is an example and not every possible embodiment is described. Other embodiments may utilize different, additional, or fewer layers on compound semiconductor 102 and SOI wafer 104 . Accordingly, the embodiments illustrated in the first figure should not be construed as proprietary or restrictive, but rather illustrative.

A second graph illustrates damage to compound semiconductors due to acids utilized during processing of bonded structures, according to some illustrative embodiments. After the two semiconductors are bonded together, additional processing of the compound semiconductor 102 is performed. Some operations may include sharpening the compound semiconductor substrate 202 with an acid to reduce compound semiconductor thickness.

However, when an acid is used, the acid may sharpen it at the bottom 204 of the compound semiconductor 102 or may cause damage along the silicon waveguide 122 . Because there is damage 204 at the edge, the edge must be removed, which limits how small the semiconductor can be.

A third diagram illustrates the addition of protective material via ALD 304 according to some embodiments. In some illustrative embodiments, a thin film of protective material 306 is deposited on compound semiconductor 102 using ALD 304 , resulting in compound semiconductor 302 with protective material 306 . Atomic layer deposition (ALD) is a thin-film deposition technique based on the sequential use of vapor-phase chemical processes. ALD is considered a type of chemical vapor deposition. Most ALD reactions use two chemicals commonly referred to as precursors. These precursors react with the surface of the material one at a time in a sequential, self-limiting fashion. Thin films are slowly deposited by repeated exposure to individual precursors.

The example presented here uses Al ₂ O ₃ as the protective material, but other dielectric materials such as SiO ₂ , HfO ₂ , ZrO ₂ , SiN, TiO ₂ or other dielectric films can also be used. Additionally, while ALD is used to describe this embodiment, other deposition methods may be used instead, such as plasma enhanced chemical vapor deposition (PECVD), ion beam deposition (IBD), and radio frequency (RF) sputtering.

The height of the deposited layer is in the range of 1 to 50 nm, but other values are possible. In some exemplary embodiments, 10 nm layers are used.

One of the advantages of using ALD is that it improves the shear strength of the bond because, among other reasons, it provides a substantially defect-free layer that is more suitable for bonding. ALD films are fully conformal because there are no discontinuities or discontinuities in the film, and the thickness of the film can be easily controlled so that layers can be as small as a single monolayer (nearly nanometers), all the way up down to tens or hundreds of nanometers. The result of using Al ₂ O ₃ deposited with LAD is that it greatly improves the bonding quality.

A fourth diagram illustrates the creation of bonded structures by bonding compound semiconductors and SOI wafers, according to some example embodiments. After deposition of Al ₂ O ₃ , compound semiconductor 302 and SOI wafer 104 are bonded together to produce bonded structure 304 . For example, two semiconductors can be bonded together by placing them together and then applying pressure and heat.

This combination forms oxides on III-V and oxides on silicon, and these oxides keep compound semiconductor 302 and SOI wafer 104 connected.

A fifth figure illustrates compound structures without superlattices according to some exemplary embodiments. The disadvantage of incorporating Al ₂ O ₃ on compound semiconductors is the increased separation of the III-V from the silicon waveguide. Optical operations in PICs require the transmission of optical modes (ie, light) from one material to another; it would therefore be desirable to be able to reduce the separation.

In photonic integrated circuits, light is routed around a wafer in silicon waveguides, and then active optical functions (such as lasers, detectors, and modulators) occur in III-V materials. Therefore, in an active device, there is a coupling between silicon and III-V. Al ₂ O ₃ increases the thickness of the gap between silicon and III-V, so the performance of coupling is reduced. The smaller the gap between the silicon and the active layer of the III-V, the better the coupling between the two materials.

In some example embodiments, the solution is to reduce the distance of optical coupling, such as by eliminating superlattices in compound semiconductor 502 . A superlattice consists of two materials grown one after the other in very thin layers. For example, a superlattice layer can be on the order of 10 nm, while other layers can be within tens or hundreds of nanometers. The purpose of a superlattice is to prevent defects from moving up into the material from the bottom surface. The superlattice layer acts as a defect prevention mechanism and improves device reliability. The removal of the superlattice exposes the compound semiconductor to the risk of bonding defects, however it also improves the coupling properties between the silicon and the compound semiconductor.

However, the _Al2O3 layer provides similar protection by moving the bonding interface away from the _compound semiconductor surface. At the same time, the distance of the III-V to the silicon waveguide (ie, the optical confinement) is reduced, which improves the coupling performance, but also improves the quality of the bonding. Removing the superlattice is a compromise, but overall performance is better with an Al ₂ O ₃ layer.

In simulations, the detector responsivity and modulator insertion loss _were better with a ₁₀ nm _Al2O3 layer and no superlattice compared to a compound semiconductor with a superlattice, but no _Al2O3 layer of.

The sixth figure illustrates how the Al ₂ O ₃ enhanced bonding structure 504 provides better protection during processing, according to some example embodiments. After adding Al ₂ O ₃ 306 to compound structure 502, it should be observed that the damage from the acid utilized during etching 602 is greatly reduced. Damage is reduced at the edge of the compound semiconductor as well as along the silicon waveguide.

In some laboratory tests, and presented by way of example and not limitation, the damage observed at the edge of the layer with 10 nm Al ₂ O ₃ was practically eliminated. At 2nm as well as at 5nm, some damage at the edges is observed, but less damage _than without the _Al2O3 layer. In addition, the shear strength of the bond is also improved. More sample results are provided below, see Figure 7.

Figure 7 illustrates some of the results of the improvements obtained by utilizing protective layers according to some example embodiments. Some tests were performed with and without Al ₂ O ₃ semiconductors and the damage on the bonded edges was measured.

Picture 702 depicts the image taken for the bonded structure without ALD _Al2O3 , while picture 704 depicts the image taken for the bonded structure with _{ALD Al2O3 10} nm thick. Panel 702 shows damage at the edges of the bond (due to material loss), while the bond structure with _{ALD Al2O3} shows no observable damage. The edges of ALD Al ₂ O ₃ are continuous and undamaged, and there is no underetching.

Shear strength is measured by examining the amount of force required to separate the bonded structures. In some tests, the shear strength of the ALD Al ₂ O ₃ semiconductor was approximately 2.5 times that of the semiconductor without Al ₂ O ₃ .

In other tests, the performance of the detectors with respect to photoresponsivity was measured for different semiconductor structures. Since the superlattice has been eliminated from the compound structure, the photoresponsivity is improved because the _Al2O3 layer is thinner _than the superlattice, which results in tighter optical coupling.

An eighth graph illustrates the yield enhancement gains obtained with Al ₂ O ₃ layers according to some embodiments. The benefits of ALD Al ₂ O ₃ semiconductors include: (a) reduction or elimination of plasma cleaning required on the III-V block prior to bonding, which allows higher throughput; (b) reduction from III-V edge-to-component back-off, so smaller III-V blocks can be bonded; (c) reduced die size because current die size is limited by the size of III-V bonding blocks, and per wafer There are more dies; and (d) greatly reduced III-V surface defect growth after bonding.

Element 802 does not use a semiconductor circuit in which Al ₂ O ₃ is bonded. Element 802 includes four compound semiconductors 806 bonded on top of an SOI wafer. Due to damage on the edges of compound semiconductor 806, only a smaller portion 808 can be used for the final PIC.

Element 804 includes four compound semiconductors 810 bonded on top of an SOI wafer. Since the compound semiconductor 810 is undamaged by the protection provided by the Al2O3 layer, there are complete _compound semiconductors that can be used in the PIC.

It should also be noted that because compound semiconductors are not damaged, III-V blocks can be placed more closely together, which results in smaller PICs and improved III-V usage, which results in better performance for III-V semiconductors. Less waste and lower costs. In addition, there is less waste on SOI wafers due to less waste on III-V semiconductors, resulting in reduced silicon costs.

In some examples, simpler processes can be used because compound semiconductors are not sensitive to acidic chemicals.

The ninth figure is a flow diagram of a method 900 of heterogeneous integration of photons and electrons using ALD combining. At operation 902, a compound semiconductor material is grown; and at operation 904, a protective material is deposited on the compound semiconductor grown in operation 902. In some exemplary embodiments, ALD is used for deposition and the protective material is Al ₂ O ₃ , although other protective materials are possible.

At operation 906, the III-V wafer is then diced for bonding to the SOI wafer. At operation 908, the epitaxial die is plasma cleaned, ensuring that the surfaces are very clean prior to bonding.

At operation 910, the SOI wafer is patterned and fabricated, including silicon waveguides; and at operation 912, the SOI wafer is plasma cleaned.

At operation 914, an epitaxial die is placed on the SOI wafer surface, and at operation 916, pressure and heat are applied to the epitaxial die on top of the SOI wafer to improve bonding.

From operation 916, the method proceeds to operation 918, where the epitaxial die substrate is removed by grinding and chemical etching steps (with improved properties provided by the protective material layer). At operation 920, additional steps are performed on the heterojunction structure for epitaxial die and element patterning.

Tenth Figure is a flow diagram of a method 1000 for fabricating a bonding structure in accordance with some illustrative embodiments. Although the various operations in the flowcharts of Figures 9 and 10 are presented and described sequentially, one of ordinary skill in the art will appreciate that some or all of the operations may be performed in a different order, combined or is omitted or executed concurrently.

At operation 1002, a compound semiconductor (eg, compound semiconductor 502 of the fifth figure) is formed. From operation 1002, the method proceeds to operation 1004, where a continuous film of protective material (eg, the _Al2O3 layer 306 of the fifth figure ₎ is deposited on the first surface of the compound semiconductor.

Also, at operation 1006 , an SOI wafer (eg, SOI wafer 104 of FIG. 5 ) is formed, wherein the SOI wafer includes one or more waveguides 122 . From operation 1006, the method proceeds to operation 1008 to bond the compound semiconductor at the first surface to the SOI wafer to form a bonded structure.

From operation 1008, the method proceeds to operation 1010 to process the combined structure. The protective material protects the compound semiconductor acidic etchant during processing of the bonded structure.

In one example, depositing the continuous film system is performed by atomic layer deposition.

In some examples, the protective material is Al ₂ O ₃ . In other examples, the protective material is one of: SiO ₂ , HfO ₂ , ZrO ₂ , SiN or TiO ₂ .

In some examples, the continuous film has a height between 2 nm and 50 nm, although other heights of the protective layer are possible (eg, in the range from 1 nm to 100 nm).

In some exemplary embodiments, the compound semiconductor is a III-V wafer.

In some exemplary embodiments, bonding the compound semiconductor to the SOI wafer further includes: placing the compound semiconductor on the SOI wafer; applying pressure and heat to the compound semiconductor and the SOI wafer; and removing the pressure and heat.

In some examples, the SOI wafer includes a SiO ₂ layer directly over one of the one or more waveguides, wherein the SiO ₂ layer is placed in contact with the first surface of the compound semiconductor for bonding.

In some examples, the compound semiconductor does not include a superlattice layer to compensate for the increased size of the compound semiconductor with the continuous film of protective material.

In some examples, processing the bonded structure further includes: removing the epitaxial substrate from the compound semiconductor through grinding and chemical steps; and patterning the elements on the compound semiconductor.

Throughout this specification, multiple instances may implement a component, operation, or structure as described by a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently and are not required to be performed in the order illustrated. Structure and functionality presented as separate components in the example configurations may be implemented as a combined structure or component. Similarly, structure and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions and improvements fall within the scope of the subject matter herein.

The embodiments illustrated herein are described in sufficient detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of the present disclosure. Therefore, the specific embodiments are not to be taken in a limiting sense, and the scope of the various embodiments is defined solely by the appended claims, along with the full scope of equivalents to which such claims are entitled.

As used herein, the term "or," may be interpreted in either an inclusive or exclusive sense. Furthermore, multiple instances may be provided for resources, operations or structures described herein as a single instance. Furthermore, The boundaries between the various resources, operations, modules, engines, and data storage devices are somewhat arbitrary, and particular operations are illustrated in the context of particular illustrative configurations. Other assignments of functionality are envisioned and may fall within the scope of Within the scope of various embodiments of the present disclosure. Generally speaking, the structure and function that are presented as separate resources in the example configuration can be implemented as a combined structure or resource. Similarly, the structures presented as a single resource and Functions can be implemented as separate resources. These and other variations, modifications, additions and improvements fall within the scope of embodiments of the present disclosure as represented by the appended claims. Therefore, description and accompanying drawings will be considered as In an illustrative rather than a restrictive sense.

104‧‧‧SOI wafer

122‧‧‧Silicon Waveguide

306‧‧‧Protective Materials

502‧‧‧Compound Semiconductors

504‧‧‧Combination structure

602‧‧‧Etching

Claims (20)

A semiconductor manufacturing method, comprising: forming a compound semiconductor; depositing a continuous film of a protective material on a first surface of the compound semiconductor; forming a silicon-on-insulator (SOI) wafer, the SOI wafer comprising one or more waveguides; the continuous film of the protective material is formed by placing the compound semiconductor at the first surface to the SOI wafer to form a bonded structure contacting the SOI wafer and applying heat; and processing the bond structure, the protective material protecting the compound semiconductor from an acidic etchant during the processing of the bond structure. The method of claim 1, wherein depositing the continuous film is performed by atomic layer deposition. The method of claim 1, wherein the protective material is Al ₂ O ₃ . The method of claim 1, wherein the protective material is one of SiO ₂ , HfO ₂ , ZrO ₂ , SiN or TiO ₂ . The method of claim 1, wherein the continuous film has a height of between 2 nanometers and 50 nanometers. The method of claim 1, wherein the compound semiconductor is a III-V wafer. The method of claim 1, wherein placing the compound semiconductor onto the SOI wafer further comprises: placing the compound semiconductor on the SOI wafer; applying pressure and heat to the compound semiconductor and the SOI wafer; and removing the pressure and heat. The method of claim 1, wherein the SOI wafer includes a layer of _SiO2 directly over one of the one or more waveguides, wherein the layer of _SiO2 is positioned to The first surface of the compound semiconductor for the bonding is in contact. The method of claim 1, wherein the compound semiconductor does not include a superlattice layer to compensate for an increased size of the compound semiconductor with the continuous film of the protective material. The method of claim 1, wherein processing the bonded structure further comprises: removing an epitaxial substrate from the compound semiconductor through grinding and chemical steps; and patterning elements on the compound semiconductor. A semiconductor bonding structure comprising: a compound semiconductor including a continuous film of a protective material deposited on a first surface of the compound semiconductor; and a silicon-on-insulator (SOI) wafer, the SOI crystal A circle includes one or more waveguides, wherein the semiconductor structure is formed by placing the compound semiconductor at the first surface onto the SOI wafer such that the continuous film of the protective material is connected to the SOI wafer. the SOI wafer is contacted and heat is applied, wherein the bonding structure is processable to pattern circuits on the compound semiconductor, the protective material protects the compound semiconductor from acid during the processing of the bonding structure Etchant effect. The bonding structure of claim 11, wherein the protective material is Al ₂ O ₃ . The bonding structure of claim 11, wherein the protective material is one of SiO ₂ , HfO ₂ , ZrO ₂ , SiN or TiO ₂ . The bonding structure of claim 11, wherein the continuous film has a height between 2 nanometers and 50 nanometers. The bonding structure of claim 11, wherein the compound semiconductor is a III-V wafer. The bonding structure of claim 11, wherein the SOI wafer includes a layer of _SiO2 directly on one of the one or more waveguides, wherein the layer of _SiO2 is positioned as in contact with the first surface of the compound semiconductor for the bonding. A semiconductor manufacturing method, comprising: forming a III-V group-based semiconductor; depositing a continuous film of Al ₂ O ₃ on a first surface of the III-V group-based semiconductor; dividing the III-V group-based semiconductor to generate an epitaxial die; plasma clean the epitaxial die; form a silicon-on-insulator (SOI) wafer including one or more waveguides; The first surface is placed on the SOI wafer; by placing the epitaxial die on the SOI wafer to form a bonded structure, the continuous film is brought into contact with the SOI wafer and heat is applied ; removing a substrate of the epitaxial die by grinding and chemical operations; and processing the bonded structure, the Al ₂ O ₃ protecting the epitaxial die from Affected by acid etchants. The method of claim 17, wherein depositing the continuous film is performed by atomic layer deposition. The method of claim 17, wherein bonding the epitaxial die to the SOI wafer system further comprises: applying pressure and heat to the epitaxial die and the SOI wafer; and The pressure and heat are removed. 17. The method of claim 17, wherein the SOI wafer includes a layer of _SiO2 directly over one of the one or more waveguides, wherein the layer of _SiO2 is positioned with the The first surface of the compound semiconductor for the bonding is in contact.

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