TWI749331B - Memory with processing in memory architecture and operating method thereof - Google Patents

Abstract

A memory with processing in memory architecture and an operating method thereof are provided. The memory includes a memory array, a mode register, an artificial intelligence core, and a memory interface. The memory array includes a plurality of memory regions. The mode register stores a plurality of memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to a special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory regions are selectively addressed to the special function processing core and the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core respectively access different memory regions in the memory array according to the plurality of memory mode settings.

Description

Memory body with in-memory operation structure and operation method thereof

The present invention relates to a circuit architecture, and particularly relates to a memory with a Processing In Memory (PIM) architecture and an operation method thereof.

With the evolution of artificial intelligence (AI) computing, artificial intelligence computing has become more and more widely used, such as image data analysis, voice data analysis, and voice data analysis through neural network models. Neural network operations such as natural language processing. Moreover, as the computational complexity of neural networks is getting higher and higher, the current computer equipment used to perform artificial intelligence calculations has gradually been unable to cope with the current neural network calculation requirements to provide effective and fast calculation performance.

Therefore, at present, a dedicated processing core has been designed to use the dedicated processing core to perform neural network operations. However, although the neural network operations are independently executed by the dedicated processing cores to give full play to the computing capabilities of the processing cores, the processing speed of the dedicated processing cores is still limited by the data access speed. Since the exclusive processing core and other special function processing cores read the data of the memory through the same general bus (Bus), the exclusive processing core cannot be real-time when other special function processing cores occupy the general bus. To obtain the data needed to perform artificial intelligence operations. In view of this, how to design a processing architecture that can quickly execute artificial intelligence operations, the following will propose solutions in several embodiments.

The present invention provides a memory with an in-memory arithmetic architecture and an operation method thereof, which can directly read the execution neural network stored in the memory chip by the artificial intelligence (AI) core integrated in the memory (Neural network) The data required for computing to achieve the effect of fast neural network computing.

The memory with an in-memory arithmetic architecture of the present invention includes a memory array, a pattern register, a memory interface, and an artificial intelligence core. The memory array includes a plurality of memory regions. The mode register is used to store multiple memory mode settings. The memory interface is coupled to the memory array and the mode register, and externally coupled to the special function processing core. The artificial intelligence core is coupled to the memory array and the pattern register. The plurality of memory areas are respectively selectively addressed to the special function processing core and the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core are based on what The multiple memory mode settings are used to respectively access different memory areas in the memory array.

In an embodiment of the present invention, the above-mentioned special function processing core and artificial intelligence core respectively access different memory areas of the memory array via their own dedicated memory bus.

In an embodiment of the present invention, the aforementioned plurality of memory regions includes a first memory region and a second memory region. The first memory area is used for exclusive access by the artificial intelligence core. The second memory area is used for exclusive access by the special function processing core.

In an embodiment of the present invention, the above-mentioned multiple memory areas further include multiple data buffer areas. The artificial intelligence engine and the memory interface alternately access different data to the multiple data buffer areas.

In an embodiment of the present invention, when the artificial intelligence core executes neural network operations as described above, the artificial intelligence core reads the input data of one of the plurality of data buffer areas as input parameters, and reads the first The weight data of a memory area. The artificial intelligence core outputs characteristic data to the first memory area.

In an embodiment of the present invention, when the artificial intelligence core executes the neural network operation, the artificial intelligence core reads the characteristic data of the first memory area as the next input parameter, and reads the data of the first memory area Another weight data. The artificial intelligence core outputs the next feature map data to one of the multiple data buffers to overwrite one of the multiple data buffers.

In an embodiment of the present invention, the aforementioned multiple data buffer areas can be alternately addressed to the special function processing core and the artificial intelligence core, so that the first memory space corresponding to the artificial intelligence core includes the first The memory area and one of the plurality of data buffer areas, and the second memory space corresponding to the special function processing core includes a second memory area and the other of the plurality of data buffer areas.

In an embodiment of the present invention, the width of the aforementioned bus dedicated to the artificial intelligence core and the plurality of memory regions is greater than the width of the external bus between the special function processing core and the memory interface.

In an embodiment of the present invention, the above-mentioned plurality of memory regions respectively correspond to a plurality of column buffer blocks, and the plurality of memory regions respectively include a plurality of memory banks. The width of a bus dedicated to the artificial intelligence core and the plurality of memory regions is greater than or equal to the number of data in a whole row of the plurality of memory banks.

In an embodiment of the present invention, the aforementioned memory is a dynamic random access memory chip.

The memory operation method with in-memory arithmetic architecture of the present invention is suitable for a memory including a memory array, a pattern register, a memory interface and an artificial intelligence core. The method includes the following steps: separately selectively addressing a plurality of memory regions in the memory to a special function processing core and an artificial intelligence core according to the plurality of memory mode settings of the mode register; and The special function processing core and the artificial intelligence core respectively access different memory areas in the memory array according to the multiple memory mode settings.

In an embodiment of the present invention, the above-mentioned special function processing core and artificial intelligence core respectively access different memory areas of the memory array via their own dedicated memory bus.

In an embodiment of the present invention, the above-mentioned plurality of memory areas includes a first memory area and a second memory area, the first memory area is used for exclusive access by the artificial intelligence core, and the second memory area The body area is used for exclusive access by the special function processing core.

In an embodiment of the present invention, the aforementioned multiple memory areas further include multiple data buffer areas, and the artificial intelligence engine and the memory interface alternately access different data to the multiple data buffer areas.

In an embodiment of the present invention, when the artificial intelligence core executes neural network operations, the special function processing core and the artificial intelligence core store each according to the multiple memory mode settings of the mode register. The step of obtaining different memory areas in the memory array includes: reading the input data of one of the plurality of data buffer areas by an artificial intelligence core as an input parameter; and reading the first memory by the artificial intelligence core Weight data of the body area; and output characteristic data to the first memory area through the artificial intelligence core.

In an embodiment of the present invention, when the artificial intelligence core executes neural network operations, the special function processing core and the artificial intelligence core store each according to the multiple memory mode settings of the mode register. The step of obtaining different memory areas in the memory array further includes: reading the characteristic data of the first memory area by the artificial intelligence core as the next input parameter; and reading the other memory area of the first memory area by the artificial intelligence core A weighting data; and outputting the next feature map data to one of the plurality of data buffers by the artificial intelligence core to overwrite one of the plurality of data buffers.

In an embodiment of the present invention, the aforementioned multiple data buffer areas can be alternately addressed to the special function processing core and the artificial intelligence core, so that the first memory space corresponding to the artificial intelligence core includes the first The memory area and one of the plurality of data buffer areas, and the second memory space corresponding to the special function processing core includes a second memory area and the other of the plurality of data buffer areas.

In an embodiment of the present invention, the width of the aforementioned bus dedicated to the artificial intelligence core and the plurality of memory regions is greater than the width of the external bus between the special function processing core and the memory interface.

In an embodiment of the present invention, the above-mentioned plurality of memory regions respectively correspond to a plurality of column buffer blocks, and the plurality of memory regions respectively include a plurality of memory banks. The width of the bus dedicated to the artificial intelligence core and the plurality of memory regions is greater than or equal to the number of data in the entire row of the plurality of memory banks.

In an embodiment of the present invention, the aforementioned memory is a dynamic random access memory chip.

Based on the above, the memory and the operating method of the present invention enable the external special function processing core and the artificial intelligence core set in the memory to simultaneously access different memory areas in the memory array. Therefore, the memory of the present invention can quickly perform neural network operations.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

In order to make the content of the present invention more comprehensible, the following embodiments are specifically cited as examples on which the present invention can indeed be implemented. In addition, wherever possible, elements/components/steps with the same reference numbers in the drawings and embodiments represent the same or similar parts.

FIG. 1 is a schematic block diagram of a memory according to an embodiment of the present invention. 1, the memory 100 includes a memory array 110, a pattern register 120, an artificial intelligence (AI) core 130, and a memory interface 140. The memory array 110 is coupled to the artificial intelligence core 130 and the memory interface 140. The mode register 120 is coupled to the memory array 110, the artificial intelligence core 130 and the memory interface 140. The memory array 110 includes a plurality of memory regions. The multiple memory areas are respectively used for storing specific data (or called a data set (Dataset)). Moreover, in an embodiment, the memory 100 may further include a plurality of dedicated memory control units. The multiple dedicated memory control units correspond to the multiple memory areas one-to-one to perform data access operations respectively. In this embodiment, the memory interface 140 may be externally coupled to the special function processing core. Moreover, the plurality of memory areas are selectively addressed in the special function processing core and the artificial intelligence core 130 according to the settings of the plurality of memory modes recorded in the mode register 120, so as to make special The function processing core and the artificial intelligence core 130 can respectively access different memory areas in the memory array 110 according to the multiple memory mode settings. In addition, the memory 100 of this embodiment has the ability to perform artificial intelligence operations.

In this embodiment, the memory 100 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM) chip, and may be, for example, a control logic, arithmetic logic, and a cache unit and other circuit elements. Constructed of Processing In Memory (PIM) architecture. The artificial intelligence core 130 can be integrated in the peripheral circuit area of the memory 100 to directly access multiple memory banks of the memory array 110 through a dedicated memory controller and a dedicated bus (Bus) . In addition, the artificial intelligence core 130 can be pre-designed to have the function and characteristics of performing a specific neural network (Neural network) operation. In other words, the memory 100 of this embodiment has the function of performing artificial intelligence operations, and the artificial intelligence core 130 and the external special function processing core can simultaneously access the memory array 110 to provide high-efficiency data access and operation effects.

In this embodiment, the special function processing core may be, for example, a central processing unit (Central Processing Unit, CPU) core, an image signal processor (Image Signal Processor, ISP) core, or a digital signal processor (Digital Signal Processor, DSP) core. ) Core, Graphics Processing Unit (GPU) core or other similar special function processing core. In this embodiment, the special function processing core is coupled to the memory interface 140 via a universal bus (or a standard bus) to access the memory array 110 via the memory interface 140. In this regard, the artificial intelligence core 130 accesses the memory array 110 through a dedicated bus inside the memory, so it is not limited to the width or speed of the memory interface 140, and the artificial intelligence core 130 can access according to specific data Mode to quickly access the memory array 130.

FIG. 2 is a schematic diagram illustrating the architecture of a memory and a plurality of special function processing cores according to an embodiment of the present invention. 2, the memory 200 includes memory areas 211 and 213, column buffer blocks 212 and 214, a mode register 220, an artificial intelligence core 230, and a memory interface 240. In this embodiment, the mode register 220 is coupled to the artificial intelligence core 230 and the memory interface 240 to provide a plurality of memory mode settings to the artificial intelligence core 230 and the memory interface 240, respectively. The artificial intelligence core 230 and the memory interface 240 operate independently to access the memory array respectively. The memory array includes memory areas 211 and 213 and column buffer blocks 212 and 214. The memory areas 211 and 213 each include a plurality of memory banks. The memory areas 211 and 213 may be data buffer areas. In this embodiment, the memory interface 240 is externally coupled to another memory interface 340. The memory interface 340 is, for example, coupled to the central processing unit core 351, the graphics processor core 352, and the digital signal processor core 353 via a bus.

In this embodiment, when the central processing unit core 351, the graphics processor core 352, and the digital signal processor core 353 need to access the column buffer block 212 or the column buffer block 214, the central processing unit core 351, graphics processor core The core 352 and the digital signal processor core 353 need to access the column buffer block 212 or the column buffer block 214 through the memory interfaces 240 and 340 sequentially or in a queue. However, regardless of the current access to the memory array of the various special function processing cores described above, the artificial intelligence core 230 can simultaneously access different memory regions in the memory array. In one embodiment, the memory area 211 or the memory area 213 may be suitable for accessing digital input data, weight data, or feature map (Feature map) required for performing neural network operations or other machine learning operations, for example. ) Information, etc.

It is worth noting that the above-mentioned various special function processing cores and artificial intelligence core 230 simultaneously access different memory areas of the memory array through their own dedicated memory bus. That is, when the aforementioned various special function processing cores access the data in the memory area 211 through the column buffer block 212, the artificial intelligence core 230 can access the data in the memory area 213 through the column buffer block 214. Moreover, when the aforementioned various special function processing cores access data in the memory area 213 via the column buffer block 214, the artificial intelligence core 230 can access the data in the memory area 211 via the column buffer block 212. In other words, the aforementioned various special function processing cores and artificial intelligence core 230 can alternately access different data to the memory areas 211 and 213 as data buffer areas. In addition, in an embodiment, the artificial intelligence core 230 may further include a plurality of caches or queues, and the artificial intelligence core 230 may use the plurality of caches or the plurality of queues. The data in the memory area 211 or the memory area 213 is quickly accessed in a pipeline manner.

FIG. 3 is a schematic diagram illustrating the structure of a memory and a plurality of special function processing cores according to another embodiment of the present invention. 3, the processor 400 of this embodiment includes memory areas 411, 413, 415, 417, column buffer blocks 412, 414, 416, 418, a mode register 420, an artificial intelligence core 430, and a memory interface 440 . In this embodiment, the mode register 420 is coupled to the artificial intelligence core 430 and the memory interface 440 to provide a plurality of memory mode settings to the artificial intelligence core 430 and the memory interface 440, respectively. The memory interface 440 is, for example, coupled to the central processing unit core 351, the graphics processor core 352, and the digital signal processor core 353 via a bus. In this embodiment, the artificial intelligence core 430 and the memory interface 440 operate independently to access the memory array respectively. The memory array includes memory areas 411, 413, 415, and 417 and column buffer blocks 412, 414, 416, and 418, and the memory areas 411, 413, 415, and 417 each include a plurality of memory banks.

In this embodiment, the memory areas 413 and 415 may be data buffer areas. The memory area 411 is exclusively accessed by the aforementioned various special function processing cores, where the various special function processing cores may be, for example, a central processing unit core 351, a graphics processor core 352, and a digital signal processor core 353. The memory area 417 is exclusively accessed by the artificial intelligence core 430. That is to say, when the aforementioned various special function processing cores and artificial intelligence core 430 exclusively access the memory area 411 and the memory area 417, the aforementioned various special function processing cores and artificial intelligence core 430 will not affect each other. Access action. For example, taking a neural network operation as an example, a whole row of the multiple memory banks in the memory area 417 can store multiple weight values of weight data, for example. The artificial intelligence core 430 can sequentially and alternately read each row of the multiple memory banks dedicated to the memory area 417 of the artificial intelligence core 430 through the column buffer block 418 to quickly obtain and execute the neural network Data required for calculation.

4A and 4B are schematic diagrams illustrating the swap addressing of different memory blocks in different memory spaces according to an embodiment of the present invention. Please refer to Figure 3, Figure 4A and Figure 4B. Hereinafter, a method of accessing the memory 400 will be described by taking the continuous execution of neural network operations on multiple image data as an example, and in conjunction with FIG. 4A and FIG. 4B. The artificial intelligence operations performed by the artificial intelligence core 430 can be, for example, Deep Neural Networks (DNN) operations, Convolutional Neural Networks (CNN) operations, or Recurrent Neural Networks (RNN). ) Calculations, etc., the present invention is not limited. In an implementation scenario, the memory area 417 includes sub-memory areas 417_1 and 417_2. The sub-memory area 417_1, for example, is used to store weight data having multiple weight values, and the sub-memory area 417_2, for example, is used to store feature map data having multiple feature values. In this implementation scenario, the memory area 413 is, for example, addressed to the special function processing core 354, and the memory area 415 is, for example, addressed to the artificial intelligence core 430. The special function processing core 354 may be, for example, the central processing unit core 351, the graphics processor core 352 or the digital signal processor core 353 of FIG. 3. Therefore, as shown in FIG. 4A, the memory space 450 corresponding to the special function processing core 354 includes memory areas 411 and 413, and the memory space 460 corresponding to the artificial intelligence core 430 includes memory areas 415 and 417.

In this implementation scenario, it is assumed that the special function processing core 354 is the digital signal processor core 353 of FIG. 3, so the memory area 415 can store the digital input data previously stored by the digital signal processor core 353, such as image data. The artificial intelligence core 430 may, for example, perform neural network operations to perform image recognition on the current image data stored in the memory area 415. The artificial intelligence core 430 can read the weight data of the memory area 417 through a dedicated bus, and read the image data of the memory area 415 as input parameters required for neural network operations to perform neural network operations. At the same time, the digital signal processor core 353 can store the next image data in the memory area 413 via the memory interfaces 340 and 440.

Then, after the image data in the memory area 415 is recognized by the artificial intelligence core 430, the address objects of the memory areas 413 and 415 can be exchanged through the setting mode register 420 to exchange the memory areas 413 and 415. Memory space. Therefore, after the memory areas 413 and 415 are exchanged with addresses, as shown in FIG. 4B, the memory space 450' corresponding to the digital signal processor core 353 includes the memory areas 411 and 415 and corresponds to the memory of the artificial intelligence core 430 The volume space 460 ′ includes memory areas 413 and 417. At this time, the artificial intelligence core 430 can continue to perform neural network operations to perform image recognition on the new image data stored in the memory area 413. The artificial intelligence core 430 can read the weight data of the memory area 417-1 through a dedicated bus, and read the next image data of the memory area 413 as the input parameters required for the neural network operation to perform the neural network Operation. At the same time, the digital signal processor core 353 can overwrite the memory area 415 via the memory interfaces 340 and 440 to store the next image data in the memory area 415. Accordingly, the memory 400 of the present embodiment can provide high-efficiency data access operations, and the memory 400 can implement neural network operations with high-speed execution effects.

5A and 5B are schematic diagrams illustrating the swap access of different memory blocks in the same memory space according to an embodiment of the present invention. Please refer to Figure 3, Figure 5A and Figure 5B. Hereinafter, a neural network operation performed on image data will be taken as an example, and another method of accessing the memory 400 will be described in conjunction with FIG. 4A and FIG. 4B. In the above scenario, at the input layer stage of the neural network operation, the memory space 550 corresponding to the artificial intelligence core 430 may, for example, include the memory area 415, the sub-memory areas 417_1, 417_2. The artificial intelligence core 430 can read the memory area 415 to obtain input data and use it as an input parameter. The memory area 415 stores image data previously stored by the digital signal processor core 353. In addition, the artificial intelligence core 430 reads the weight data of the sub-memory area 417_1. Therefore, the artificial intelligence core 430 performs neural network operations according to the input parameters and weight data to generate feature map data, and the artificial intelligence core 430 stores the feature map data in the sub-memory area 417_2.

Then, in the next hidden layer stage of neural network operation, the memory space 550' corresponding to the artificial intelligence core 430 includes a memory area 415, sub-memory areas 417_1, 417_2. The artificial intelligence core 430 reads the feature map data previously stored in the sub-memory area 417_2 as input parameters of the current hidden layer, and reads the weight data of the sub-memory area 417_1. Therefore, the artificial intelligence core 430 performs neural network operations according to the input parameters and weight data to generate new feature map data, and the artificial intelligence core 430 replicates the new feature map data to the memory area 415. In other words, the memory area addressed in the artificial intelligence core 430 remains unchanged, but the read and storage target addresses of the artificial intelligence core 430 are exchanged. By analogy, the artificial intelligence core 430 of this embodiment can use the memory area 415 and the sub-memory area 417_2 to alternately read the previously generated feature map data and store the artificial intelligence core 430 currently performing neural network operations. The current feature map data generated in the process. Since each memory area has its own independent bus, the artificial intelligence core 430 of this embodiment can quickly obtain input data and weight data, and quickly perform neural network operations and store output data.

FIG. 6 is a flowchart of a memory operation method according to an embodiment of the present invention. Referring to FIG. 6, the memory operation method of this embodiment can be at least applicable to the memory 100 of FIG. 1, so that the memory 100 executes steps S610 and S620. The memory interface 140 of the memory 100 can be externally coupled to a special function processing core. In step S610, according to the multiple memory mode settings of the mode register 120, the multiple memory regions of the memory array 110 are respectively selectively addressed to the memory spaces of the special function processing core and the artificial intelligence core 130. . In step S620, the special function processing core and the artificial intelligence core 130 respectively access different memory areas in the memory array 110 according to the multiple memory mode settings. Therefore, the memory operation method of this embodiment enables the memory 100 to be accessed by the special function processing core and the artificial intelligence core 130 at the same time, so as to provide a highly efficient memory operation effect.

In addition, with regard to the relevant internal components, implementations, and technical details of the memory 100 of this embodiment, reference can be made to the description of the above-mentioned embodiments of FIG. 1 to FIG.

In summary, the memory and operation method of the present invention can be designed with multiple specific memory mode settings through the mode register, so that multiple memory regions of the memory array can be based on the multiple specific The memory mode is set to be selectively addressed to the external special function processing core and artificial intelligence core respectively, so that the external special function processing core and artificial intelligence core can simultaneously access different memory areas in the memory array. Therefore, the artificial intelligence core set in the memory can quickly perform neural network operations.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100, 200, 400: memory 110: memory array 120, 220, 420: mode register 130, 230, 430: artificial intelligence core 140, 240, 440: memory interface 211, 213, 411, 413, 415, 417: memory area 212, 214, 412, 414, 416, 418: column buffer block 340: Memory Interface 351: Central Processing Unit Core 352: graphics processor core 353: Digital Signal Processor Core 354: Special function processing core 417_1, 417_2: sub-memory area 450, 450’, 460, 460’, 550, 550’: memory space S610, S620: steps

FIG. 1 is a schematic block diagram of a memory according to an embodiment of the present invention. FIG. 2 is a schematic diagram illustrating the architecture of a memory and a plurality of special function processing cores according to an embodiment of the present invention. FIG. 3 is a schematic diagram illustrating the structure of a memory and a plurality of special function processing cores according to another embodiment of the present invention. 4A and 4B are schematic diagrams illustrating the swap addressing of different memory blocks in different memory spaces according to an embodiment of the present invention. 5A and 5B are schematic diagrams illustrating the swap access of different memory blocks in the same memory space according to an embodiment of the present invention. FIG. 6 is a flowchart of a memory operation method according to an embodiment of the present invention.

100: memory

110: memory array

120: Mode register

130: Artificial Intelligence Core

140: memory interface

Claims (10)

A memory with an in-memory arithmetic architecture, comprising: a memory array including a plurality of memory regions; a mode register for storing a plurality of memory mode settings; and a memory interface coupled to the memory Array and the mode register, and externally coupled to a special function processing core; and an artificial intelligence core, coupled to the memory array and the mode register, wherein the memory areas are based on the mode register The memory mode settings are selectively addressed to the special function processing core and the artificial intelligence core, respectively, so that the special function processing core and the artificial intelligence core respectively access the Different memory areas in the memory array, wherein the special function processing core and the artificial intelligence core respectively access different memory areas of the memory array simultaneously through their own dedicated memory bus, which are exclusive to the artificial intelligence The width of a bus between the core and the memory regions is greater than the width of an external bus between the special function processing core and the memory interface, wherein the memory regions include a first memory region and A second memory area, the first memory area is used for exclusive access by the artificial intelligence core, and the second memory area is used for exclusive access by the special function processing core, wherein the memory areas are more Including multiple data buffer areas, and the artificial intelligence engine and the memory interface alternately access the data buffer areas with different Data, wherein when the artificial intelligence core executes a neural network operation, the artificial intelligence core reads an input data of one of the data buffer areas as an input parameter, and reads the first memory area A weight data, wherein the artificial intelligence core outputs a feature data to the first memory area. The memory according to claim 1, wherein when the artificial intelligence core executes the neural network operation, the artificial intelligence core reads the characteristic data of the first memory area as the next input parameter, and Read another weight data of the first memory area, wherein the artificial intelligence core outputs the next feature map data to one of the data buffers to overwrite one of the data buffers. For the memory described in claim 1, wherein the data buffer areas can be alternately addressed to the special function processing core and the artificial intelligence core, so that a first memory corresponding to the artificial intelligence core The volume space includes the first memory area and one of the data buffer areas, and a second memory space corresponding to the special function processing core includes the second memory area and one of the data buffer areas The other. As for the memory described in claim 1, wherein the memory areas respectively correspond to a plurality of row buffer blocks, and the memory areas each include a plurality of memory banks, which are exclusive to the artificial intelligence The width of a bus between the core and the memory areas is greater than or equal to the number of data in a whole row of the memory banks. The memory described in item 1 of the scope of patent application, wherein the memory is a dynamic random access memory chip. A memory operation method with an in-memory arithmetic architecture. The memory includes a memory array, a pattern register, a memory interface, and an artificial intelligence core, wherein the method includes: the pattern register according to the The memory mode is set to selectively address multiple memory regions in the memory to the special function processing core and the artificial intelligence core; and according to the special function processing core and the artificial intelligence core The memory modes are set to respectively access different memory areas in the memory array, wherein the special function processing core and the artificial intelligence core respectively access different memory arrays via their own dedicated memory bus. A memory area, where the width of a bus dedicated to the artificial intelligence core and the memory areas is greater than the width of an external bus between the special function processing core and the memory interface, wherein the memories The body area includes a first memory area and a second memory area. The first memory area is used for the exclusive access of the artificial intelligence core, and the second memory area is used for the special function processing core. Access, wherein the memory areas further include a plurality of data buffer areas, and the artificial intelligence engine and the memory interface alternately access different data to the data buffer areas, When the artificial intelligence core executes a neural network operation, the special function processing core and the artificial intelligence core access different memory arrays according to the memory mode settings of the mode register. The steps of the memory area include: reading an input data of one of the data buffer areas by the artificial intelligence core as an input parameter; reading a weight of the first memory area by the artificial intelligence core Data; and output a characteristic data to the first memory area by the artificial intelligence core. For example, in the memory operation method described in item 6 of the scope of patent application, when the artificial intelligence core executes the neural network operation, the special function processing core and the artificial intelligence core are based on the pattern registers. The step of setting the memory mode to separately access different memory areas in the memory array further includes: reading the characteristic data of the first memory area by the artificial intelligence core as the next input parameter; The artificial intelligence core reads another weighted data of the first memory area; and the artificial intelligence core outputs the next feature map data to one of the data buffers to overwrite the data of the data buffers one of them. For example, in the memory operation method described in item 6 of the scope of patent application, the data buffer areas can be alternately addressed to the special function processing core and the artificial intelligence core, so that the data corresponding to the first artificial intelligence core A memory empty The space includes the first memory area and one of the data buffer areas, and a second memory space corresponding to the special function processing core includes the second memory area and one of the data buffer areas another. In the memory operation method described in item 6 of the scope of patent application, the memory regions correspond to a plurality of column buffer blocks, and the memory regions respectively include a plurality of memory banks, which are exclusive to the The width of a bus between the artificial intelligence core and the memory regions is greater than or equal to the number of data in a whole row of the memory banks. In the memory operation method described in item 6 of the scope of patent application, the memory is a dynamic random access memory chip.

Images