TWI746411B - Clock generating circuit and calibration circuit thereof - Google Patents

Abstract

The invention related to a clock generating circuit and a calibration circuit thereof. The clock generating circuit inputs a reference clock signal generated from a reference clock circuit to an input divider and a fractional PLL circuit, thereby, the input divider generates an input dividing signal to a counter and a gain error estimator to make counter generate a counting signal in responsive to the input dividing signal and a spread signal. The gain error estimator generates a N parameter and an parameter in responsive to the counting signal and the input dividing signal, for the fractional PLL circuit generating a clock output signal. Wherein the input divider, the counter and the gain error estimator are formed as the calibration circuit to calibrate the fractional PLL generating the clock output signal.

Description

Clock generation circuit and its compensation circuit

The present invention relates to a clock generation circuit and its compensation circuit, in particular, frequency division integer parameters and frequency division decimal parameters are combined with spread spectrum signals and reference clock signals for frequency division to output appropriate output clock signals.

Today's integrated circuits (ICs) have at least one phase-lock loop (PLL) to provide various frequency clocks required by the integrated circuits. In addition, today's integrated circuits are evolving with the process accuracy of semiconductor manufacturing processes, resulting in process complexity, the operational complexity of integrated circuits, and the various clocks during operation may not be an integer multiple of the relationship, for example, the same integrated circuit (IC) may need to use 66MHz, 100MHz, 133MHz clock. It is the most economical way to use a phase-locked circuit to generate the clocks of various frequencies required in an integrated circuit. That is, the pulse signal with a fixed frequency output by the phase-locked circuit undergoes a frequency division action to make the phase-locked circuit in A fixed frequency provides pulse signal output, but in order to obtain pulse signal output of different frequencies, it is necessary to set multiple lock circuits to provide pulse signal output of multiple frequencies. As such a large circuit area is occupied and power consumption is high, a single phase-locked circuit is developed to connect multiple frequency dividers to provide pulse signal output of different frequencies.

Nowadays, many electronic circuits, even miniature electronic circuits, such as IC, need a clock source as the basic brake of the signal. Therefore, designing a high-frequency crystal oscillator in a microprocessor (MCU) circuit is a very common circuit design. However, the circuit design of the high-frequency crystal oscillator not only provides a high-frequency clock signal, but also needs to input a considerable current into the circuit to drive the high-frequency crystal oscillator. For power-sensitive applications, a relatively low power requirement is therefore required, and even lower frequency clocks are derived from the timing function. Therefore, a 32.768kHz quartz crystal oscillator was developed in response to this demand. The oscillation signal generated by the quartz crystal oscillator can be divided by 15 times by the frequency divider inside the quartz clock generator. Obtain a 1Hz clock signal, 1Hz means that the second hand moves every second, therefore, the frequency divider inside the quartz clock can only divide the frequency 15 times. If 32.768kHz is replaced with another frequency oscillation signal, the oscillation signal will pass After 15 times of frequency division, it is not a 1Hz frequency division signal, and the time indicated by the electronic clock is inaccurate. 32.768k=32768=2 to the 15th power, so it can provide electronic devices for data transmission and provide more convenient and accurate timing.

For example: Embedded microcontroller (MCU) systems have always relied on a low-frequency 32.768 kHz quartz crystal oscillator to generate low-frequency oscillation signals to drive the internal oscillator of the MCU for time keeping and fault recovery functions. An on-chip 32.768kHz clock generator with background calibration function is proposed to achieve good frequency accuracy. By reusing the system clock (HFXO) to intermittently assist in background calibration, frequency accuracy can be achieved. However, the above frequency dividing method requires HFXO to be set, and the frequency divider needs to be kept in an enabled state even in sleep mode, so the clock generation circuit will cause greater power consumption.

Based on the above-mentioned problems, the present invention provides a clock generation circuit and its compensation circuit. The counter is set up, and the input frequency divider signal is combined with the spread spectrum signal to generate the counting signal to a gain error circuit to generate the corresponding frequency divider. The integer parameter and the frequency-dividing decimal parameter are transferred to a fractional phase-locked circuit, so that the fractional phase-locked circuit generates a corresponding output pulse signal after the compensation of the frequency-dividing integer parameter and the frequency-dividing decimal parameter. This further reduces the power consumption of the clock generating circuit in the enabled state.

An object of the present invention is to provide a clock generation circuit that combines an input frequency divider signal with a spread spectrum signal to generate a counting signal to a gain error circuit, thereby generating corresponding frequency division integer parameters and frequency division decimal parameters to a fraction The phase lock circuit is used to compensate the fractional phase lock circuit to generate a corresponding output pulse signal. This further reduces the power consumption of the clock generating circuit in the enabled state.

The present invention discloses a clock generation circuit, which includes a reference clock generation circuit, an input frequency divider, a counter, a gain error circuit and a fractional phase lock circuit. The reference clock generating circuit generates a reference clock signal to the input frequency divider and the fractional phase lock circuit, and the input frequency divider generates an input frequency dividing signal to the counter and the gain error circuit according to the reference clock signal , The counter generates a counting signal to the gain error circuit by receiving the input frequency division signal and a spread signal, so that the gain error circuit receives the input frequency division signal and the counting signal to generate a frequency division integer parameter and A frequency-dividing decimal parameter. As a result, the compensation circuit of the present invention is not kept in the enabled state, and the frequency-dividing integer parameter and the frequency-dividing decimal parameter provided by the compensation circuit of the present invention are equivalent to those generated by the reference clock signal. Therefore, the compensation of the present invention The circuit reduces power consumption.

The present invention provides an embodiment in which the fractional phase-locked circuit includes a phase/frequency detector, a charge pump element, a loop filter, a voltage-controlled oscillator, an output frequency divider, and a multi-divisor Frequency converter and a modulator. The phase/frequency detector is coupled to the reference clock generating circuit and a timing control circuit. The timing control circuit generates a timing control signal and an energy signal. The phase/frequency detector receives the reference clock signal and the timing control circuit. A timing control signal to correspondingly generate a charge and discharge control signal; the charge pump element is coupled to the phase/frequency detector and the timing control circuit to receive the charge and discharge control signal and the enable signal for charge and discharge; The loop filter is coupled to the charge pump element and generates a potential signal according to the charge and discharge of the charge pump element; the voltage-controlled oscillator is coupled to the loop filter and receives the potential signal to correspondingly generate a voltage-controlled oscillation Signal; the output frequency divider, coupled to the voltage-controlled oscillator, receives the voltage-controlled oscillation signal to correspondingly generate an output clock signal; the multi-divider frequency divider receives the voltage-controlled oscillation signal and a sum signal , To correspondingly generate a feedback frequency divider signal to the timing control circuit, so that the timing control circuit generates the timing control signal and the enable signal; and the modulator is coupled to the multi-divider frequency divider and a totalizer Unit, the modulator and the summing unit are coupled to the gain error circuit, and the modulator receives the feedback frequency division signal and the frequency division decimal parameter to generate a modulation signal to the summation unit, The summation unit receives the frequency division integer parameter and the modulation signal to generate the summation signal to the multi-divider frequency divider.

The present invention provides an embodiment in which the clock generating circuit further includes a spread-spectrum clock generator, which is coupled to the counter to generate the spread-spectrum signal to the counter.

The present invention provides an embodiment in which the gain error circuit further generates a spread-spectrum enabling signal to the spread-spectrum clock generator to control the spread-spectrum clock generator to be enabled.

The present invention provides an embodiment in which the compensation circuit further includes a temperature sensor coupled to the gain error circuit to sense an ambient temperature to generate a temperature compensation signal to the gain error circuit, and the gain error circuit is more based on The temperature compensation signal generates the frequency division decimal parameter and the frequency division integer parameter.

The present invention provides an embodiment in that the gain error circuit is provided with a look-up table unit, a gain summation unit and an arithmetic unit. The look-up table unit is coupled to the temperature sensor and generates a temperature compensation parameter according to the temperature compensation signal; the gain summation unit is coupled to the look-up table unit, the counter and a storage unit, and the storage unit stores a frequency dividing parameter , The gain summation unit receives the temperature compensation parameter, the frequency division parameter, and the counting signal to generate a summation operation parameter correspondingly; and the operation unit is coupled to the gain summation unit to generate the summation parameter The frequency division decimal parameter and the frequency division integer parameter.

The present invention provides an embodiment, in that the gain error circuit is provided with a gain summation unit and an arithmetic unit. The gain summation unit is coupled to the counter and a storage unit. The storage unit stores a frequency division parameter. The gain summation unit receives the temperature compensation parameter, the frequency division parameter and the counting signal to generate a summation operation parameter correspondingly And the arithmetic unit is coupled to the gain summation unit to generate the frequency division decimal parameter and the frequency division integer parameter according to the summation operation parameter.

The present invention also provides a compensation circuit, which generates a frequency division integer parameter and a frequency division decimal parameter to a fractional phase lock circuit, so that the fractional phase lock circuit is based on a reference clock signal, the frequency division decimal parameter and the frequency division circuit The integer parameter generates an output clock signal, and the compensation circuit includes an input frequency divider, a counter, and a gain error circuit. The input frequency divider generates an input frequency division signal to the counter and the gain error circuit according to the reference clock signal, and the counter generates a count signal to the gain by receiving the input frequency division signal and a spread frequency signal The error circuit enables the gain error circuit to receive the input frequency division signal and the count signal to generate the frequency division integer parameter and the frequency division decimal parameter. As a result, the compensation circuit of the present invention is not kept in the enabled state, and the frequency-dividing integer parameter and the frequency-dividing decimal parameter provided by the compensation circuit of the present invention are equivalent to those generated by the reference clock signal. Therefore, the compensation of the present invention The circuit reduces power consumption.

In order to enable your reviewer to have a further understanding and understanding of the features of the present invention and the effects achieved, the following examples and accompanying descriptions are provided. The description is as follows:

In view of the fact that in the conventional clock generating circuit, the frequency divider remains in the enabled state, which increases the power consumption, the present invention proposes a clock generating circuit and its compensation circuit to solve the problem caused by the conventional technology. The frequency divider remains enabled, which leads to the problem of more power consumption.

In the following, the characteristics and the structure of a clock generating circuit disclosed in the present invention will be further explained:

First, please refer to the first figure, which is a block diagram of a clock generating circuit according to an embodiment of the present invention. As shown in the figure, the clock generating circuit 10 of the present invention includes a fractional phase lock circuit 20 and a compensation circuit 40. The compensation circuit 40 generates a frequency division integer parameter N and a frequency division fractional parameter α to the fractional phase lock circuit 20. , The fractional phase lock circuit 20 _{generates an output clock signal f OUT according to a reference clock signal f OSC} , the frequency division decimal parameter α, and the frequency division integer parameter N. In addition, the clock generating circuit 10 is further coupled to a reference clock circuit 12, which generates the reference clock signal f _OSC .

Wherein, the fractional phase lock circuit 20 includes a phase/frequency detector 22, a charge pump element 24, a loop filter 26, a voltage-controlled oscillator 28, an output frequency divider 30, and a multi-divider The frequency converter 32, a timing control circuit 34, a modulator 36 and an adding unit 38. The phase/frequency detector 22 is coupled to a reference clock generating circuit 12 and the timing control circuit 34, the charge pump element 24 is coupled to the loop filter 26, and the loop filter 26 is coupled to the voltage controlled oscillator 28. The voltage-controlled oscillator 28 is coupled to the output frequency divider 30 and the multi-divider frequency divider 32, and the multi-divider frequency divider 32 is coupled to the timing control circuit 34, the modulator 36 and the multiplier The total unit 38, the modulator 36 and the total unit 38 are further coupled to the compensation circuit 40.

The timing control circuit 34 generates a timing control signal T _EN and a consistent energy signal CP _EN , and the phase/frequency detector 22 receives the reference clock signal f _OSC and the timing control signal T _EN to correspondingly generate a charge and discharge control Signal V _PF , the charge pump element 24 receives the charge and discharge control signal V _PF and the enable signal CP _EN to charge and discharge, thereby forming a charge and discharge signal V _CP , especially a potential signal in the loop filter 26 V _Filter , and control the voltage-controlled oscillator 28 by the potential signal V _Filter to generate a voltage-controlled oscillation signal V _VCO . The output frequency divider 30 and the multi-divider frequency divider 32 receive voltage control respectively The voltage-controlled oscillation signal V _VCO generated by the oscillator 28, the output frequency divider 30 generates a corresponding output clock signal f _OUT according to the voltage-controlled oscillation signal V _VCO , and the multi-divisor frequency divider 32 receives the The voltage-controlled oscillation signal V _VCO and one of the summing signals generated by the summing unit 38 correspondingly generate a feedback frequency divider signal V _MMD to the timing control circuit 34, so that the timing control circuit 34 generates the timing control signal T _EN and the enabling signal CP _EN . The modulator 36 receives the feedback frequency division signal V _MMD and the frequency division decimal parameter α to generate a modulation signal Σ _OUT to the summing unit 38, and the summing unit 38 receives the frequency division integer parameter N and The modulated signal Σ _{OUT is used} to generate the sum signal SUM to the multi-divisor 32. It can be seen from the above description that the multi-divider frequency divider 32 to the timing control circuit 34, the timing control signal T _EN , the enabling signal CP _EN , the feedback frequency dividing signal V _MMD and the voltage-controlled oscillation signal The signal transmission of the V _VCO is equivalent to that the voltage controlled oscillator 28 performs feedback control on the phase/frequency detector 22 and the charge pump element 24.

Please also refer to the second figure. The compensation circuit 40 of the present invention includes an input frequency divider 42, a counter 44, and a gain error circuit 46. In addition, the compensation circuit 40 is further coupled to a spread spectrum generating circuit 14. The input frequency divider 42 is coupled to the reference clock generation circuit, the counter 44 and the gain error circuit 46. In particular, the input frequency divider 42 is coupled to the enable port EN of the counter 44, and the input frequency divider 42 The reference clock signal f _{OSC is} received to correspondingly generate an input frequency divider signal V _M ; the counter 44 receives the input frequency divider signal V _M of the input frequency divider 42 and receives the spread frequency generating circuit 14 The spreading signal f _MO correspondingly generates a counting signal k, so that the gain error circuit 46 receives the input frequency dividing signal V _M and the counting signal k to generate the frequency division integer parameter N and the frequency division decimal parameter α, _{So that the aforementioned fractional phase lock circuit 20 generates a corresponding clock output signal f OUT} according to the frequency-dividing integer parameter N and the frequency-dividing decimal parameter α.

In detail, the gain error circuit 46 is provided with a gain summation unit 462, a storage unit 464, and an arithmetic unit 466. The gain summation unit 462 is coupled to the counter and a storage unit, and the storage unit stores a frequency dividing parameter. k _32k , the gain summation unit 462 receives the frequency division parameter k _32k and the count signal k to generate a summation parameter Δcode correspondingly, and the calculation unit is coupled to the gain summation unit 462 to respond to the summation parameter Δcode generates the frequency-dividing integer parameter N and the frequency-dividing decimal parameter α to be output to the fractional phase lock circuit 20. In particular, the frequency-dividing decimal parameter α is output to the modulator 36, and the frequency-dividing integer parameter N is output to the summing unit 38. Therefore, the frequency division integer parameter N and the frequency division decimal parameter α in this embodiment correspond to the frequency division parameter k _32k and the counting signal k.

It can be seen that the compensation circuit 40 of the present invention compensates the fractional phase lock circuit 20 by the frequency division integer parameter N and the frequency division fractional parameter α, so that the fractional phase lock circuit 20 can generate the corresponding output clock signal f _OUT , meanwhile, the spread-spectrum signal f _{MO is} compensated for the fractional phase lock circuit 20 by the compensation circuit 40, instead of the spread-spectrum signal f _MO directly input to the fractional phase lock circuit 20, the fractional phase lock circuit 20 can be Intermittent operation, that is, the fractional phase lock circuit 20 does not need to be continuously enabled, thereby reducing power consumption. The reference clock generating circuit 12 and the spread-spectrum clock generating circuit 14 of the above embodiments are externally connected to the fractional phase lock circuit 20 and the compensation circuit, and another embodiment is the reference clock generating circuit 12 and the spread-spectrum clock generating circuit. The circuit 14 is built in the reference clock generating circuit 12 or the spread spectrum clock generating circuit 14.

In addition to the compensation circuit 40, the clock generating circuit 10 is further provided with a reference clock generating circuit 12 and a spread spectrum clock generating circuit 14. However, the ambient temperature will also affect the operation of the clock generating circuit 10. A temperature compensation mechanism can be further set up to compensate for the temperature-induced error.

Please refer to FIG. 3, which is a block diagram of a clock generating circuit according to another embodiment of the present invention. The difference between the first figure and the third figure is that the compensation circuit 40 of the third figure is further provided with a temperature sensor 48 to complement the temperature compensation mechanism of the compensation circuit 40. Wherein, the gain error circuit 46 is coupled to the temperature sensor 48, and generates a temperature enable signal TP to the temperature sensor 48 _{when the input frequency dividing signal V M fails to match the counting signal k} , So as to enable the temperature sensor 48, the temperature sensor 48 will detect the environment (not shown) in which the clock generating circuit 10 is located, and correspondingly generate a temperature sensing signal TC to the gain error circuit 46 , To perform temperature compensation on the frequency-dividing integer parameter N and the frequency-dividing decimal parameter α.

In detail, please refer to the fourth figure. The difference from the second figure is that the gain error circuit 46 of the fourth figure is further provided with a comparison table unit 466, which is coupled to the temperature sensor 48 and thus receives the temperature sensor. The measurement signal TC is used to find the corresponding temperature compensation parameter K _TC according to the temperature sensing signal TC, and input to the gain summation unit 462. Therefore, the gain summation unit 462 of this embodiment is generated _{based on the temperature compensation parameter K TC} The sum operation parameter Δcode is sent to the operation unit 466. Therefore, the frequency division integer parameter N and the frequency division decimal parameter α of this embodiment correspond to the temperature compensation parameter K _TC to avoid the influence of errors caused by excessively high ambient temperature. The accuracy of the pulse output signal f _OUT.

Therefore, the present invention is really novel, progressive, and available for industrial use. It should meet the patent application requirements of my country's patent law. Undoubtedly, I filed an invention patent application in accordance with the law. I pray that the Bureau will grant the patent as soon as possible.

However, the above are only the preferred embodiments of the present invention, and are not used to limit the scope of implementation of the present invention. For example, the shapes, structures, features and spirits described in the scope of the patent application of the present invention are equally changed and modified. , Should be included in the scope of patent application of the present invention.

10: Clock generation circuit 12: Reference clock generation circuit 14: Spread-spectrum clock generation circuit 20: Fractional phase lock circuit 22: Phase/frequency detector 24: Charge pump component 26: Loop filter 28: Voltage control Oscillator 30: output frequency divider 32: multiple divisor frequency divider 34: timing control circuit 36: modulator 38: summing unit 40: compensation circuit 42: input frequency divider 44: counter 46: gain error circuit 462 : Gain summation unit 464: Storage unit 466: Operation unit 468: Comparison table unit 48: Temperature sensor α: Divider decimal parameter Σ: Out modulation signal CP _EN : Enable signal f _IN : Input pulse signal f _OUT : output pulse signal f _MO : spread spectrum signal k: counting signal k _32k : frequency division parameter k _TC : temperature compensation parameter N: frequency division integer parameter SUM: sum signal TC: temperature sensing signal T _EN : timing control Signal V _PF : Charge and discharge control signal V _CP : Charge and discharge signal V _Filter : Potential signal V _VCO : Voltage-controlled oscillation signal V _M : Input frequency elimination signal V _MMD : Feedback frequency elimination signal

Figure 1: It is a block diagram of a clock generating circuit according to an embodiment of the present invention; Figure 2: It is a block diagram of the detailed circuit of the compensation circuit according to an embodiment of the present invention; Figure 3: It is a block diagram of a clock generating circuit according to another embodiment of the present invention; and Figure 4: It is a block diagram of the detailed circuit of the compensation circuit of another embodiment of the present invention.

10: Clock generation circuit

12: Reference clock circuit

14: Spread spectrum clock circuit

20: Fractional phase lock circuit

22: Phase/frequency detector

24: Charge pump component

26: Loop filter

28: Voltage Controlled Oscillator

30: Output divider

32: Multi-divisor frequency divider

34: timing control circuit

36: Integral-differential modulation circuit

38: Sum unit

40: Compensation circuit

42: Input frequency divider

44: counter

46: gain error circuit

f _OSC : Reference clock signal

f _MO : Spread spectrum signal

f _OUT : Clock output signal

CP _EN : Charge-enable signal

T _EN : Enabling signal

V _PF : Detection signal

V _Filter : Filter the signal

VCO: voltage control signal

V _MMD : feedback frequency elimination signal

SUM: Sum signal

Σout: Modulation signal

Claims (11)

A clock generation circuit, which includes: A reference clock generating circuit to generate a reference clock signal; An input frequency divider, coupled to the reference clock generating circuit, receives the reference clock signal to generate an input frequency divider signal; A counter, coupled to the input frequency divider, receives the input frequency divider signal, and receives a spread spectrum signal to correspondingly generate a counting signal; A gain error circuit, coupled to the input frequency divider and the counter, receives the input frequency division signal and the count signal to generate a frequency division integer parameter and a frequency division decimal parameter; and A fractional phase lock circuit is coupled to the reference clock generation circuit and the gain error circuit, receives the reference clock signal, the frequency division integer parameter and the frequency division decimal parameter, and generates a clock output signal correspondingly. The clock generating circuit according to claim 1, wherein the fractional phase lock circuit includes: A phase/frequency detector, coupled to the reference clock generation circuit and a timing control circuit, the timing control circuit generates a timing control signal and an energy signal, the phase/frequency detector receives the reference clock signal and The timing control signal is used to correspondingly generate a charge and discharge control signal; A charge pump element coupled to the phase/frequency detector and the timing control circuit to receive the charge and discharge control signal and the enable signal for charge and discharge; A loop filter, coupled to the charge pump element, generates a potential signal according to the charge and discharge of the charge pump element; A voltage-controlled oscillator, coupled to the loop filter, receives the potential signal to correspondingly generate a voltage-controlled oscillation signal; An output frequency divider, coupled to the voltage-controlled oscillator, receives the voltage-controlled oscillation signal, and correspondingly generates an output clock signal; A multi-divisor frequency divider receives the voltage-controlled oscillation signal and a sum signal to correspondingly generate a feedback frequency divider signal to the timing control circuit, so that the timing control circuit generates the timing control signal and the enable signal ;as well as A modulator, coupled to the multi-divisor frequency divider and an summing unit, the modulator and the summing unit are coupled to the gain error circuit, the modulator receives the feedback frequency divider signal and The frequency-dividing decimal parameter generates a modulation signal to the summing unit, and the summing unit receives the frequency-dividing integer parameter and the modulation signal to generate the sum signal to the multi-divider frequency divider. The clock generating circuit described in claim 1 further includes a spread-spectrum clock generator, which is coupled to the counter to generate the spread-spectrum signal to the counter. The clock generating circuit according to claim 3, wherein the gain error circuit further generates a spread-spectrum enabling signal to the spread-spectrum clock generator to control the spread-spectrum clock generator to be enabled. The clock generation circuit of claim 1, wherein the compensation circuit further includes a temperature sensor coupled to the gain error circuit to sense an ambient temperature to generate a temperature compensation signal to the gain error circuit, the The gain error circuit further generates the frequency division decimal parameter and the frequency division integer parameter according to the temperature compensation signal. The clock generating circuit according to claim 5, wherein the gain error circuit is provided with: A comparison table unit, coupled to the temperature sensor, to generate a temperature compensation parameter according to the temperature compensation signal; A gain summation unit, coupled to the comparison table unit, the counter, and a storage unit, the storage unit stores a frequency division parameter, and the gain summation unit receives the temperature compensation parameter, the frequency division parameter and the counting signal corresponding to each other Generate a summation operation parameter; and An arithmetic unit, coupled to the gain summation unit, generates the frequency division decimal parameter and the frequency division integer parameter according to the summation operation parameter. The clock generating circuit according to claim 1, wherein the gain error circuit is provided with: A gain summation unit coupled to the counter and a storage unit, the storage unit stores a frequency division parameter, and the gain summation unit receives the frequency division parameter and the counting signal and generates a sum operation parameter correspondingly; and An arithmetic unit, coupled to the gain summation unit, generates the frequency division decimal parameter and the frequency division integer parameter according to the summation operation parameter. A compensation circuit generates a frequency division integer parameter and a frequency division decimal parameter to a fractional phase lock circuit, so that the fractional phase lock circuit generates a frequency division integer parameter based on a reference clock signal, the frequency division decimal parameter and the frequency division integer parameter Output clock signal, the compensation circuit includes: An input frequency divider that receives the reference clock signal to generate an input frequency divider signal; A counter receiving the input frequency divider signal and a spread spectrum signal to correspondingly generate a counting signal; and A gain error circuit receives the input frequency division signal and the count signal to generate the frequency division integer parameter and the frequency division decimal parameter correspondingly. The compensation circuit according to claim 8, wherein the compensation circuit is further coupled to a spread-spectrum clock generator, and the spread-spectrum clock generator generates the spread-spectrum signal to the counter. The compensation circuit according to claim 8, wherein the compensation circuit is further coupled to a temperature sensor, the temperature sensor senses an ambient temperature and generates a temperature compensation signal to the pulse signal to the gain error circuit, the gain The error circuit further generates the frequency division decimal parameter and the frequency division integer parameter according to the temperature compensation signal. The compensation circuit according to claim 8, wherein the fractional phase lock circuit includes: A phase/frequency detector, coupled to a reference clock generation circuit and a timing control circuit, receives the reference clock signal of the reference clock generation circuit and a timing control signal of the timing control circuit to generate a corresponding Charge and discharge control signal; A charge pump element, coupled to the phase/frequency detector, to receive the charge and discharge control signal and the uniform energy signal for charge and discharge; A loop filter, coupled to the charge pump element, generates a potential signal according to the charge and discharge of the charge pump element; A voltage-controlled oscillator, coupled to the loop filter, receives the potential signal to correspondingly generate a voltage-controlled oscillation signal; An output frequency divider, coupled to the voltage-controlled oscillator, receives the voltage-controlled oscillation signal, and correspondingly generates an output clock signal; A multi-divisor frequency divider receives the voltage-controlled oscillation signal and a sum signal to correspondingly generate a feedback frequency divider signal, and the timing control circuit generates the timing control signal to the phase according to the feedback frequency divider signal. Frequency detector and generate the enabling signal to the charge pump element; and A modulator, coupled to the multi-divisor frequency divider and an summing unit, the modulator and the summing unit are coupled to the gain error circuit, the modulator receives the feedback frequency divider signal and The frequency-dividing decimal parameter generates a modulation signal to the summing unit, and the summing unit receives the frequency-dividing integer parameter and the modulation signal to generate the sum signal to the multi-divider frequency divider.

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