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TWI742780B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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Publication number
TWI742780B
TWI742780B TW109125328A TW109125328A TWI742780B TW I742780 B TWI742780 B TW I742780B TW 109125328 A TW109125328 A TW 109125328A TW 109125328 A TW109125328 A TW 109125328A TW I742780 B TWI742780 B TW I742780B
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Taiwan
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stop structure
slot
layer material
etch stop
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TW109125328A
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TW202110296A (zh
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曹博昭
黃裕華
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聯發科技股份有限公司
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Abstract

本發明提供了一種半導體元件及其製造方法。半導體元件包括基板和焊盤。焊盤位於基板上並且具有上表面和狹槽，其中，狹槽相對于上表面向內凹進。本發明中在焊盤上包括狹槽，可以使得在焊接過程中容納焊盤部分的變形和/或減小或釋放焊盤的應力，可以縮小相鄰兩個焊盤之間的間距。

Description

半導體元件及其製造方法
本發明涉及一種半導體元件(semiconductor component)及其製造方法，更具體地，涉及一種具有狹槽(slot)的半導體元件及其製造方法。
傳統的半導體元件包括多個焊盤。將焊線(solder wire)接合到焊盤上後，對焊盤施加力，會使得焊盤破裂或變形而接觸到相鄰的焊盤(導致電氣短路)。
有鑑於此，本發明提供了一種半導體元件及其製造方法，以解決上述現有技術的問題或缺點。
在本發明的一個實施例中，提供了一種半導體元件。半導體元件包括基板和焊盤。焊盤位於基板上並且具有上表面和狹槽，其中，狹槽相對于上表面向內凹進。
在本發明的另一個實施例中，提供了一種用於半導體元件的製造方法。該製造方法包括以下步驟：在基板上形成焊盤結構和蝕刻停止結構，其中蝕刻停止結構覆蓋焊盤結構，其中焊盤結構包括焊盤部分和圍繞焊盤部分的週邊部分；去除蝕刻停止結構的週邊部分，以形成蝕刻停止結構的保留 部分，用於覆蓋焊盤結構的焊盤部分，其中焊盤結構的週邊部分從保留部分暴露出；以及在焊盤結構的週邊部分上形成狹槽以形成焊盤，其中狹槽相對於焊盤的上表面向內凹進。
本發明中在焊盤上包括狹槽，可以使得在焊接過程中容納焊盤部分的變形和/或減小或釋放焊盤的應力，可以縮小相鄰兩個焊盤之間的間距。
當結合附圖閱讀以下對本發明實施例的詳細描述時，本發明的許多目的、特徵和優點將顯而易見。然而，本文採用的附圖是出於描述的目的，並且不應被視為限制。
100:半導體元件
120:焊盤
110:基板
130:鈍化層
111:基底
112:導電層
113:電介質層
114:導電通孔
121:焊盤層
122:阻擋層
113u:電介質層的上表面
121s:焊盤層的第一側面
122s:焊盤層的第二側面
120u:焊盤的上表面
120r:狹槽
121A:焊盤部分
121B:週邊部分
10:焊線
130a:鈍化層的開口
130w:第一內側壁
120w:第二內側壁
122":阻擋層材料
121":第一焊盤層材料
121':第二焊盤層材料
20':蝕刻停止結構材料
113a:電介質層的開口
120':焊盤結構
121A':焊盤部分
21,121B':週邊部分
20:蝕刻停止結構
22:保留部分
1221":阻擋層材料的去除部分
130':鈍化層材料
131':暴露部分
130s:開口的內側壁
120r':凹部
附圖被包括進來以提供對本發明的進一步理解，附圖被結合在本說明書中並構成本說明書的一部分。附圖示出了本發明的實施例，並且與說明書一起用於解釋本發明的原理。在附圖中：第1A圖示出了根據本發明實施例的半導體元件的示意圖。
第1B圖示出了第1A圖的半導體元件的俯視圖。
第1C圖示出了接合在第1A圖的半導體元件的焊盤上的焊線的示意圖。
第2A圖至第2I圖示出了第1A圖的半導體元件的製造工藝。
參照第1A圖至第1C圖，第1A圖示出了根據本發明實施例的半導體元件100的示意圖，第1B圖示出了第1A圖的半導體元件100的俯視圖，第1C圖示出了接合在第1A圖的半導體元件100的焊盤120上的焊線的示意圖。在一個實施例中，半導體元件100可以例如是半導體基板、半導體晶片等。
半導體元件100包括基板110、至少一個焊盤120和鈍化層130。
基板110包括基底(base)111、多個導電層112、多個電介質層(dielectric layer)113和多個導電通孔114。基底111例如是矽晶圓(silicon wafer)。通過使用半導體工藝在基底111上形成導電層112、電介質層113和導電通孔114。相鄰的兩個導電層112通過一個電介質層113彼此分開，並且通過至少一個導電通孔114電連接。
如第1A圖所示，焊盤120可以是多層結構。例如，焊盤120包括焊盤層121和阻擋層(barrier layer)122。焊盤層121例如由鋁、金、銀、銅或其組合形成。阻擋層122例如由鎳(Ni)、鎳合金、氮化鈦(TiN)或其組合形成。阻擋層122的至少一部分形成在最上面的電介質層113的開口113a內，焊盤層121形成在阻擋層122上。焊盤層121突出(project)在電介質層113的上表面113u之外。焊盤層121具有第一側面121s，阻擋層122具有第二側面122s，其中第一側面121s和阻擋層122彼此對齊，例如，第一側面121s和阻擋層122彼此齊平(flush)。
每個焊盤120具有上表面120u和狹槽(slot)120r，其中狹槽120r相對於上表面120u向內凹進(recess)並且朝向基板110延伸。焊盤120包括焊盤部分121A和週邊部分(periphery portion)121B，例如，焊盤120的焊盤層121包括焊盤部分121A和週邊部分121B，其中週邊部分121B圍繞焊盤部分121A，並且狹槽120r形成在焊盤部分121A和週邊部分121B之間。
如第1C圖所示，焊線10接合在相應的焊盤120上。焊線10接合在焊盤120上之後，焊線10部分地形成在狹槽120r內，並且狹槽120r的至少一部分由焊線10填充。狹槽120r可以為焊盤部分121A的變形部分提供用於容納焊盤部分121A的變形部分的空間。此外，在將焊線10接合在焊盤120上的過程期間，狹槽120r可以容納(receive)焊盤部分121A的變形(由焊接工具施加在焊盤120上的壓力導致)，因此，如此可以防止由於過度變形和/或鈍化層130損壞而導致的焊盤破裂或者接觸相鄰焊盤。換句話說，狹槽 120r可容納焊盤部分121A的變形和/或減小或釋放焊盤的應力。因此，相鄰兩個焊盤120之間的間距(pitch)可以縮小。在實施例中，與不具有狹槽121r的相鄰兩個焊盤之間的間距相比，相鄰兩個焊盤120之間的間距可縮小5%至15%。
如第1B圖所示，狹槽120r是環形(ring-shaped)狹槽，例如，閉合的(closed)環形狹槽或敞開的(open)環形狹槽。另外，狹槽120r以多邊形、圓形、橢圓形等延伸。狹槽120r的寬度W1在0.1微米(mm)至2.0mm之間，例如0.1mm。然而，這種示例並不意味著對本發明的限制。
如第1C圖所示，狹槽120r位於焊盤部分121A和週邊部分121B之間。焊盤部121A被構造為承接(carry)焊線10。當焊接工具向焊盤120施加力時，焊盤部分121A向外變形，並且狹槽120r可以容納變形的焊盤部分121A。因此，即使焊盤120變形，變形的焊盤120也不會接觸相鄰的焊盤或相鄰的電子元件。
如第1A圖所示，鈍化層130具有至少一個開口130a。開口130a的第一內側壁(inner sidewall)130w與狹槽120r的第二內側壁120w對齊，例如，開口130a的第一內側壁130w與狹槽120r的第二內側壁120w齊平。
第2A圖至第2I圖示出了第1A圖的半導體元件100的製造工藝。
如第2A圖所示，通過使用沉積技術(deposition technology)形成覆蓋基板110的阻擋層材料122"。可用的技術包括但不限於物理氣相沉積(physical vapor deposition，PVD)、化學氣相沉積(chemical vapor deposition，CVD)、電化學沉積(electrochemical deposition，ECD)、分子束外延(molecular beam epitaxy，MBE)以及近來的原子層沉積(atomic layer deposition，ALD)等。然後，通過使用後端(back end of line，BEOL)技術形成覆蓋阻擋層材料122"的第一焊盤層材料121"。然後，通過沉積技術形成覆蓋第一焊盤層材料121"的蝕刻停止結構(etching stop structure)材料20'。可用的技術包括但 不限於物理氣相沉積、化學氣相沉積、電化學沉積、分子束外延以及近來的原子層沉積等。
然後，如第2A圖中所示，通過使用沉積技術形成覆蓋一部分蝕刻停止結構材料20'的第一圖案化光刻膠(first patterned photoresist)PR1。可用的技術包括但不限於物理氣相沉積、化學氣相沉積、電化學沉積、分子束外延以及近來的原子層沉積等。第一圖案化光刻膠PR1限定了保留部分(retained portion)PR12以及連接到保留部分PR12並圍繞保留部分PR12的週邊部分PR11。第一圖案化光刻膠PR1位於最上層電介質層113的開口113a的正上方。
接著，如第2B圖中所示，通過第一圖案化光刻膠PR1，去除蝕刻停止結構材料20'的一部分，形成蝕刻停止結構20。例如，去除蝕刻停止結構材料20'的未被第一圖案化光刻膠PR1覆蓋的部分，以形成蝕刻停止結構20。
如第2B圖所示，使用蝕刻技術通過第一圖案化光刻膠PR1去除第一焊盤層材料121"的一部分，以形成焊盤結構120'的第二焊盤層材料121'。焊盤結構120'還包括阻擋層材料122"。在本實施例中，阻擋層材料122"可以作為蝕刻停止層，因此對第一焊盤層材料121"(如第2A圖所示)的蝕刻可以在阻擋層材料122"處停止。如第2B圖所示，第二焊盤層材料121'包括焊盤部分121A'以及連接到焊盤部分121A'並圍繞焊盤部分121A'的週邊部分121B'。
在本實施例中，通過同一第一圖案化光刻膠PR1在同一蝕刻工藝中形成蝕刻停止結構20和焊盤結構120'。
如第2C圖所示，使用蝕刻工藝去除第一圖案化光刻膠PR1的週邊部分PR11，以暴露蝕刻停止結構20的週邊部分21。在蝕刻工藝中，覆蓋 蝕刻停止結構20的保留部分22的第一圖案化光刻膠PR1的保留部分PR12被保留。
如第2D圖所示，利用蝕刻工藝通過第一圖案化光刻膠PR1的保留部分PR12，去除蝕刻停止結構20的週邊部分21，以暴露第二焊盤層材料121'的週邊部分121B'，並且保留覆蓋焊盤部分121A'的保留部分22。
在第2D圖中，通過使用蝕刻工藝去除阻擋層材料122"的去除部分1221"以暴露電介質層113，並且保留覆蓋電介質層113的阻擋層材料122"的阻擋層122。
在一個實施例中，在同一蝕刻工藝中(或同時)去除蝕刻停止結構20的週邊部分21以及阻擋層材料122"的去除部分1221"。另外，在蝕刻之後，第二焊盤層材料121'具有第一側面121s，阻擋層122具有第二側面122s，其中第一側面121s和阻擋層122彼此對齊，例如，第一側面121s和阻擋層122彼此齊平。
如第2E圖所示，利用蝕刻工藝去除第一圖案化光刻膠PR1的保留部分PR12，以暴露蝕刻停止結構20的保留部分22。
如第2F圖所示，通過使用沉積技術形成覆蓋保留部分22、第二焊盤層材料121'和電介質層113的鈍化層材料130'。可用的技術包括但不限於物理氣相沉積、化學氣相沉積、電化學沉積、分子束外延、以及近來的原子層沉積等。
如第2G圖所示，通過使用沉積技術形成覆蓋鈍化層材料130'的第二圖案化光刻膠PR2。可用的技術包括但不限於物理氣相沉積、化學氣相沉積、電化學沉積、分子束外延以及近來的原子層沉積等。第二圖案化光刻膠PR2具有至少一個開口PR2a，該開口PR2a暴露出鈍化層材料130'的暴露部分131'，其中暴露部分131'位於保留部分22的正上方。
在第2G圖中，保留部分22具有第一寬度L1，開口PR2a具有第二寬度L2，其中第二寬度L2大於第一寬度L1。例如，第一寬度L1和第二寬度L2之間的寬度差在0.05mm至2mm之間的範圍內。
如第2H圖所示，通過第二圖案化光刻膠PR2的開口PR2a在鈍化層材料130'上形成開口130a，以利用蝕刻工藝形成鈍化層130。鈍化層130的開口130a暴露第二焊盤層材料121'的焊盤部分121A'和保留部分22，例如暴露整個保留部分22。在蝕刻之後，第二圖案化的光刻膠PR2具有內側壁PRs，鈍化層130的開口130a具有內側壁130s，其中內側壁PRs和內側壁130s彼此對齊，例如，內側壁PRs和內側壁130s彼此齊平。
在第2H圖中，在蝕刻工藝中，形成通過第二圖案化光刻膠PR2的開口PR2a和鈍化層130的開口130a從第二焊盤層材料121'的焊盤部分121A'的上表面120u(在第2G圖中示出)向基板110延伸的凹部(recess)120r'。凹部120r'具有第一深度D1。
如第2I圖所示，通過使用蝕刻工藝去除蝕刻停止結構20的保留部分22。在蝕刻工藝中，凹部120r'朝著基板110延伸以形成狹槽(slot)120r。
狹槽120r具有第二深度D2，第二深度D2大於凹部120r'的第一深度D1。在同一蝕刻工藝中，形成狹槽120r並且去除保留部分22。換句話說，在去除保留部分22的過程中形成狹槽120r，並且不需要附加的光罩(photo mask)。
然後，去除第二圖案化光刻膠PR2以暴露鈍化層130，接著形成半導體元件100。
儘管已經根據目前被認為是最實際和優選的實施例描述了本發明，但是應該理解，本發明不限於所公開的實施例。相反，本發明旨在覆蓋所附申請專利範圍的精神和範圍內包含的各種修改和類似佈置，這些修改和類似佈置與最寬泛的解釋相一致，從而涵蓋所有這類修改和類似結構。
100:半導體元件
120:焊盤
110:基板
130:鈍化層
111:基底
112:導電層
113:電介質層
114:導電通孔
121:焊盤層
122:阻擋層
113u:電介質層的上表面
121s:焊盤層的第一側面
122s:焊盤層的第二側面
120u:焊盤的上表面
120r:狹槽
121A:焊盤部分
121B:週邊部分

Claims (17)

  1. 一種半導體元件，包括：基板；焊盤，位於所述基板上並且具有上表面和狹槽；以及鈍化層，所述鈍化層覆蓋所述焊盤的一部分，並且所述鈍化層具有開口，其中，所述狹槽相對於所述上表面向內凹進，其中，所述鈍化層的開口的第一內側壁與所述狹槽的第二內側壁對齊。
  2. 如請求項1之半導體元件，其中，所述焊盤包括焊盤部分和圍繞所述焊盤部分的週邊部分，並且所述狹槽位於所述焊盤部分和所述週邊部分之間。
  3. 如請求項1之半導體元件，其中，所述狹槽是環形狹槽。
  4. 如請求項3之半導體元件，其中，所述狹槽是閉合的環形狹槽或者敞開的環形狹槽。
  5. 如請求項1之半導體元件，其中，所述狹槽的寬度在0.1微米至2.0微米之間。
  6. 如請求項1之半導體元件，其中，還包括：部分形成在所述狹槽內的焊線。
  7. 如請求項6之半導體元件，其中，所述狹槽的至少一部分填充有所述焊線。
  8. 一種用於半導體元件的製造方法，包括：在基板上形成焊盤結構和蝕刻停止結構，其中所述蝕刻停止結構覆蓋所述焊盤結構，其中所述焊盤結構包括焊盤部分和圍繞所述焊盤部分的週邊部分； 去除所述蝕刻停止結構的週邊部分，以形成所述蝕刻停止結構的保留部分，用於覆蓋所述焊盤結構的所述焊盤部分，其中所述焊盤結構的所述週邊部分從所述保留部分暴露出；以及在所述焊盤結構的所述週邊部分上形成狹槽以形成焊盤，其中所述狹槽相對於所述焊盤的上表面向內凹進。
  9. 如請求項8之製造方法，其中，還包括：在所述基板上形成阻擋層材料；形成第一焊盤層材料以覆蓋所述阻擋層材料；形成蝕刻停止結構材料以覆蓋所述第一焊盤層材料；去除所述第一焊盤層材料的一部分，以形成所述焊盤結構的第二焊盤層材料，其中所述第二焊盤層材料包括所述焊盤部分和所述週邊部分；以及去除所述蝕刻停止結構材料的一部分，以形成所述蝕刻停止結構。
  10. 如請求項9之製造方法，其中，去除所述第一焊盤層材料的一部分以形成所述焊盤結構的所述第二焊盤層材料的步驟包括：形成第一圖案化光刻膠以覆蓋所述蝕刻停止結構材料；通過所述第一圖案化光刻膠去除所述第一焊盤層材料的一部分，以形成所述焊盤結構的所述第二焊盤層材料；其中，去除所述刻蝕停止結構材料的一部分以形成所述刻蝕停止結構的步驟包括：通過所述第一圖案化光刻膠去除所述蝕刻停止結構材料的一部分，以形成所述蝕刻停止結構。
  11. 如請求項10之製造方法，其中，還包括：去除所述第一圖案化光刻膠的週邊部分，其中，保留所述第一圖案化光刻膠的覆蓋所述蝕刻停止結構的所述保留部分的保留部分； 其中，去除所述蝕刻停止結構的所述週邊部分以形成所述蝕刻停止結構的所述保留部分用於覆蓋所述焊盤結構的所述焊盤部分的步驟還包括：通過所述第一圖案化光刻膠的所述保留部分去除所述蝕刻停止結構的所述週邊部分，以形成所述蝕刻停止結構的所述保留部分，並暴露所述第二焊盤層材料的所述週邊部分；以及去除所述第一圖案化光刻膠以暴露所述蝕刻停止結構的所述保留部分。
  12. 如請求項9之製造方法，其中，還包括：去除所述阻擋層材料的去除部分，以形成被所述焊盤結構覆蓋的阻擋層。
  13. 如請求項12之製造方法，其中，去除所述阻擋層材料的所述去除部分的步驟以及去除所述蝕刻停止結構的週邊部分的步驟在同一工藝中執行。
  14. 如請求項8之製造方法，其中，還包括：形成鈍化層材料以覆蓋所述蝕刻停止結構的所述保留部分；在所述鈍化層材料上形成開口；以及形成從所述焊盤的上表面向所述基板延伸的凹部。
  15. 如請求項8之製造方法，其中，還包括：形成鈍化層材料以覆蓋所述蝕刻停止結構的所述保留部分；形成第二圖案化光刻膠以覆蓋所述鈍化層材料，其中所述第二圖案化光刻膠具有開口以暴露所述鈍化層材料的暴露部分；通過所述第二圖案化光刻膠的所述開口在所述鈍化層材料上形成開口，以形成所述鈍化層；通過所述第二圖案化光刻膠的所述開口形成凹部，以通過所述鈍化層的所述開口從所述焊盤的上表面向所述基板延伸。
  16. 如請求項14之製造方法，其中，還包括： 去除所述蝕刻停止結構的所述保留部分；以及延伸所述凹部以形成所述狹槽。
  17. 如請求項15之製造方法，其中，在同一工藝中執行去除所述蝕刻停止結構的所述保留部分的步驟和延伸所述凹部以形成所述狹槽的步驟。
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