TWI632660B - Semiconductor structure and method of manufacturing the same - Google Patents

Abstract

A semiconductor structure includes a substrate, a first well region, a first doped region, a second well region, a second doped region, a field oxide layer, a first conductive layer, a first insulating layer, and a second conductive layer. The substrate has a first conductivity type. The first well region is formed in the substrate and has a second conductivity type. The first doped region is formed in the first well region and has a second conductivity type. The second well region is formed in the substrate and has a first conductivity type. The second doped region is formed in the second well region and has a first conductivity type. The field oxide layer is disposed on the substrate and between the first and second doped regions. The first conductive layer overlaps the field oxide layer. The first insulating layer overlaps the first conductive layer. The second conductive layer overlaps the first insulating layer.

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a stacked structure.

In general, integrated circuits typically include many electronic components. Electronic components include active components and passive components. The active component includes a transistor. In addition, passive components include resistors, capacitors, and inductors. In conventional integrated circuits, a plurality of separate electronic components are connected by metal wires, but the area required for the circuit is increased. In addition, in packaging, a wire is required to connect the two components, resulting in an increase in cost.

The present invention provides a semiconductor structure including a substrate, a first well region, a first doped region, a second well region, a second doped region, a field oxide layer, a first conductive layer, and a first An insulating layer and a second conductive layer. The substrate has a first conductivity type. The first well region is formed in the substrate and has a second conductivity type. The first doped region is formed in the first well region and has a second conductivity type. The second well region is formed in the substrate and has a first conductivity type. The second doped region is formed in the second well region and has a first conductivity type. The field oxide layer is disposed on the substrate and between the first and second doped regions. The first conductive layer overlaps the field oxide layer. The first insulating layer overlaps the first conductive layer. The second conductive layer overlaps the first insulating layer.

The present invention further provides a method of fabricating a semiconductor structure, comprising: providing a substrate having a first conductivity type; forming a first well region in the substrate, wherein the first well region has a second conductivity type; forming a first a doped region is in the first well region, wherein the first doped region has a second conductivity type; forming a second well region in the substrate, wherein the second well region has a first conductivity type; forming a second The doped region is in the second well region, wherein the second doped region has a first conductivity type; a field oxide layer is formed on the substrate, wherein the field oxide layer is located between the first and second doped regions; forming a first A conductive layer is on the field oxide layer; a first insulating layer is formed on the first conductive layer; and a second conductive layer is formed on the first insulating layer.

The present invention further provides a method of fabricating a semiconductor structure, comprising: providing a substrate having a first conductivity type; forming a first well region in the substrate, wherein the first well region has a second conductivity type; forming a The first doped region is in the first well region, wherein the first doped region has a second conductivity type; forming a second well region in the substrate, wherein the second well region has a first conductivity type; forming a first The second doped region is in the second well region, wherein the second doped region has a first conductivity type; a third doped region is formed in the second well region, wherein the third doped region has a second conductivity type Forming a layer of oxide on the substrate, wherein the field oxide layer is between the first and third doped regions; forming a gate on the substrate, wherein the gate overlaps a portion of the field oxide layer and the second well region, and 1. The second and third doped regions constitute a transistor, the first doped region serves as a drain of the transistor, the second doped region serves as a base of the transistor, and the third doped region serves as a source of the transistor Forming a first conductive layer on the field oxide layer, wherein the first conductive layer and the gate Spatially separated from one another; a first insulating layer formed on the first conductive layer; and forming a second conductive layer on the first insulating layer.

100, 200, 300, 400‧‧‧ semiconductor structure

110, 210, 311, 411‧‧‧ base

121, 122, 221, 222, 321~323, 421~423‧‧

131, 132, 231, 232, 331~333, 431~434‧‧‧ doped areas

140, 240, 340, 441, 442‧‧ ‧ field oxide layer

150, 350‧‧‧ stacked structure

151, 152, 251, 252, 351, 352, 451, 452‧‧ ‧ conductive layer

161~163, 261, 262, 361, 362, 461, 462‧‧‧ insulation

E1~E4‧‧‧ Conductive end

171, 172, 371~374‧‧‧ trace

312, 412‧‧‧ epitaxial layer

353, 453‧‧ ‧ gate

V11~V16, V31~V38‧‧‧guide hole

X‧‧‧ direction

W1, W2‧‧‧ width

D1, D2‧‧‧ diode

R1~R4‧‧‧ resistor

GND‧‧‧ Grounding level

HV‧‧‧High voltage signal

Q‧‧‧Optocrystal

Figure 1A is a schematic cross-sectional view of a semiconductor structure of the present invention.

1B and 1C are diagrams of possible top views of the conductive layer of the present invention.

1D is a schematic diagram of an equivalent circuit of the semiconductor structure 100 of the present invention.

2A is another possible cross-sectional view of the semiconductor structure of the present invention.

Fig. 2B is a plan view of the field oxide layer of Fig. 2A.

Figure 3A is another schematic cross-sectional view of the semiconductor structure of the present invention.

3B is a schematic diagram of an equivalent circuit of the semiconductor structure of the present invention.

4A is another schematic cross-sectional view of the semiconductor structure of the present invention.

Figure 4B is a diagram of a possible top view of the semiconductor structure of the present invention.

5A-5C illustrate a method of fabricating a semiconductor structure of the present invention.

6A to 6C are views showing a method of manufacturing a semiconductor structure of the present invention.

The semiconductor structure and its manufacturing method for some embodiments of the present invention are described in detail below. It will be appreciated that the following description provides many different embodiments or examples for implementing the various embodiments of the invention. The specific elements and arrangements described below are merely illustrative of some embodiments of the invention. Of course, these are by way of example only and not as a limitation of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitive examples are merely illustrative of some embodiments of the invention, and are not intended to represent any of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Or, it is possible to have one or more layers of other materials In this case, there may be no direct contact between the first material layer and the second material layer.

Figure 1A is a schematic cross-sectional view of a semiconductor structure of the present invention. As shown, the semiconductor structure 100 includes a substrate 110, well regions 121, 122, doped regions 131, 132, a field oxide layer 140, and a stacked structure 150. The substrate 110 has a first conductivity type. In one possible embodiment, substrate 110 is a germanium or silicon on insulator (SOI) substrate or other suitable semiconductor substrate.

The well region 121 is formed in the substrate 110 and has a second conductivity type. In this embodiment, the second conductivity type is different from the first conductivity type. For example, the first conductivity type is a P type, and the second conductivity type is an N type. In other embodiments, the first conductivity type is N-type and the second conductivity type is P-type. In some embodiments, well zone 121 is a high pressure well zone. Well zone 121 can be formed by an ion implantation step. For example, when the second conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the well region 121 is to be formed to form the well region 121. However, when the second conductivity type is a P-type, boron ions or indium ions may be implanted in a region where the well region 121 is to be formed to form the well region 121.

The well region 122 is formed in the substrate 110 and has a first conductivity type. In one possible embodiment, the doping concentration of the well region 122 is higher than the doping concentration of the substrate 110. In the present embodiment, well zone 122 contacts well zone 121, but is not intended to limit the invention. In other embodiments, the well regions 121 and 122 are spatially spaced apart from each other. The well region 122 can also be formed by an ion implantation step. For example, when the first conductivity type is a P-type, boron ions or indium ions may be implanted in a region where the well region 122 is to be formed to form the well region 122. However, when the first conductivity type is N type, Phosphorus or arsenic ions are implanted in the region where the well region 122 is intended to form to form the well region 122.

The doped region 131 is formed in the well region 121 and has a second conductivity type. In a possible embodiment, the doped region 131 can be formed by an ion implantation step. In the present embodiment, the doping concentration of the doping region 131 is higher than the doping concentration of the well region 121. In another possible embodiment, the doped region 131 can serve as a cathode for a diode.

Doped region 132 is formed in well region 122 and has a first conductivity type. In a possible embodiment, the doped region 132 can be formed by an ion implantation step. In the present embodiment, the doping concentration of the doping region 132 is higher than the doping concentration of the well region 122. In another possible embodiment, the doped region 132 can serve as the anode of a diode.

The field oxide layer 140 is disposed on the substrate 110 and between the doping regions 131 and 132. In the present embodiment, the field oxide layer 140 extends into the well region 121. As shown, the field oxide layer 140 is spatially separated from the doped regions 131, but is not intended to limit the invention. In other embodiments, the field oxide layer 140 may directly contact the doped region 131.

Stack structure 150 is formed over field oxide layer 140 and contacts field oxide layer 140. In the embodiment, the stacked structure 150 includes at least two conductive layers 151, 152 and an insulating layer 161. As shown, a conductive layer 151 is formed over the field oxide layer 140 and directly contacts the field oxide layer 140. The conductive layer 151 overlaps and directly contacts the field oxide layer 140. The conductive layer 151 material can be a metal, a metal oxide, a metal nitride, a metal alloy, a metal halide, any other suitable conductive material, or a combination thereof. For example, the material of the conductive layer 151 is SiCr, metal or Poly. In other embodiments, the conductive layer 151 is a non-doped poly. The present invention does not limit the extended shape of the conductive layer 151. guide The direction in which the electrical layer 151 extends may remain unchanged or change multiple times. For example, the conductive layer 151 extends in a strip shape, a curved shape, or a spiral shape. In this embodiment, the conductive layer 151 can be equivalent to a first resistor. The equivalent impedance of the conductive layer 151 can be controlled by controlling the implantation concentration and the extended shape of the conductive layer 151.

The insulating layer 161 is formed on the well regions 121, 122, the doping regions 131, 132, the field oxide layer 140, and the conductive layer 151, and electrically isolates the conductive layers 151 and 152. The material of the insulating layer 161 includes an oxide, a nitride, an oxynitride, a low dielectric constant material, any other suitable insulating material, or a combination thereof, and may be formed by a chemical vapor deposition step.

The conductive layer 152 is formed over the insulating layer 161 and overlaps the conductive layer 151. The conductive layer 152 material can be a metal, a metal oxide, a metal nitride, a metal alloy, a metal halide, any other suitable conductive material, or a combination thereof. For example, the material of the conductive layer 152 is SiCr, metal or Poly. In other embodiments, conductive layer 152 also uses undoped poly. The invention does not limit the extended shape of the conductive layer 152. In a possible embodiment, the conductive layer 152 extends in a straight line, a curved shape, or a spiral shape. In another possible embodiment, the conductive layer 152 has the same extension shape or different from the extended shape of the conductive layer 151. In this embodiment, the conductive layer 152 can be equivalent to a second resistor. The equivalent impedance of the conductive layer 152 can be controlled by controlling the implantation concentration and the extended shape of the conductive layer 152. In a possible embodiment, the equivalent impedance of the conductive layer 152 is different or the same as the equivalent impedance of the conductive layer 151.

In addition, in other embodiments, when the potentials of the conductive layers 151, 152 are the same, the capacitance of the equivalent capacitance formed by the conductive layer 151, the insulating layer 161 and the conductive layer 152 is almost zero. In other embodiments, the stacked structure 150 is comprised of More conductive layers and insulating layers are formed. For example, assume that the stacked structure 150 has first to third conductive layers. In this example, the first conductive layer directly contacts the field oxide layer 140. A first insulating layer is formed over the first conductive layer. Next, a second conductive layer is formed over the first insulating layer and overlaps the first conductive layer. Thereafter, a second insulating layer is formed over the second conductive layer. Next, a third conductive layer is formed over the second insulating layer and overlaps the second conductive layer. For convenience of explanation, the following only takes two conductive layers as an example.

1B and 1C are diagrams of possible top views of conductive layers 151 and 152 of the present invention. In Fig. 1B, the conductive layers 151 and 152 each extend in a spiral shape. As shown, the conductive layer 151 has conductive ends E1 and E2, and the conductive layer 152 has conductive ends E3 and E4. In a possible embodiment, the width W1 of the conductive layer 151 is approximately equal to the width W2 of the conductive layer 152, but is not intended to limit the present invention. In other embodiments, the width W1 of the conductive layer 151 may be greater or smaller than the width W2 of the conductive layer 152.

In a possible embodiment, the conductive layer 151 completely overlaps the conductive layer 152, so the conductive end E1 of the conductive layer 151 overlaps the conductive end E3 of the conductive layer 152, and the conductive end E2 of the conductive layer 151 overlaps the conductive end E4 of the conductive layer 152. In another possible embodiment, the conductive layer 151 does not completely overlap the conductive layer 152. For example, the conductive layer 151 overlaps a portion of the conductive layer 152.

In other embodiments, the conductive end E1 of the conductive layer 151 does not completely or completely overlap the conductive end E3 of the conductive layer 152. In addition, the conductive end E2 of the conductive layer 151 may not completely or completely overlap the conductive end E4 of the conductive layer 152. In FIG. 1B, the conductive end E1 of the conductive layer 151 completely overlaps the conductive end E3 of the conductive layer 152, and the conductive end E2 of the conductive layer 151 completely overlaps the conductive end E4 of the conductive layer 152.

In FIG. 1C, the shape of the conductive layer 151 is different from that of the conductive layer 152. shape. In the present embodiment, the conductive layer 151 is elongated and extends in the direction X. However, the conductive layer 152 is spiral and its direction of extension is not fixed.

Returning to FIG. 1A, in a possible embodiment, the semiconductor structure 100 further includes insulating layers 162, 163 and traces 171, 172. An insulating layer 162 is formed over the insulating layer 161. Traces 171 and 172 are formed over the insulating layer 162. An insulating layer 163 is formed over the traces 171 and 172.

In this embodiment, the traces 171 are electrically connected to the doped region 132, the conductive end E3 of the conductive layer 152, and the conductive end E1 of the conductive layer 151 through the via holes V11-V13. The trace 172 is electrically connected to the conductive end E4 of the conductive layer 152, the conductive end E2 of the conductive layer 151, and the doped region 131 through the via holes V14-V16. In a possible embodiment, the trace 172 is used to transmit a ground level.

1D is a schematic diagram of an equivalent circuit of the semiconductor structure 100 of the present invention. As shown, the semiconductor structure 100 includes a diode D1 and resistors R1, R2. The trace 171 is electrically connected to the doped region 132, the conductive end E3 of the conductive layer 152 and the conductive end E1 of the conductive layer 151, and the trace 172 is electrically connected to the conductive end E4 of the conductive layer 152 and the conductive end E2 of the conductive layer 151. With the doped region 131, therefore, in the first DD, the diode D1 and the resistors R1, R2 are connected in parallel, but are not intended to limit the present invention. The present invention does not limit the connection relationship between the diode D1 and the resistors R1, R2. In other embodiments, one of the diode D1 and the resistors R1, R2 may be connected in series with the diode D1 and the other of the resistors R1, R2.

In the present embodiment, the doped region 131 of FIG. 1A serves as the cathode of the diode D1, and the doped region 132 serves as the anode of the diode D1. Further, the resistor R1 in Fig. 1D represents the equivalent impedance of the conductive layer 151 of Fig. 1A. Resistor R2 represents the equivalent impedance of conductive layer 152.

2A is another possible cross-sectional view of the semiconductor structure of the present invention. As shown, the semiconductor structure 200 includes a substrate 210, well regions 221, 222, doped regions 231, 232, field oxide layer 240, conductive layers 251, 252, and insulating layers 261, 262. In the present embodiment, the field oxide stratification 240 is a ring structure surrounding the doped region 231. In addition, the shape of the conductive layer 251 is different from the shape of the conductive layer 252. In the embodiment, the conductive layer 251 is a ring structure, and the conductive layer 252 is a spiral structure. Due to the characteristics of the substrate 210, the well regions 221, 222, the doping regions 231, 232, the field oxide layer 240, the conductive layers 251, 252, and the insulating layers 261, 262 of FIG. 2A and the substrate 110 and the well region 121 of the semiconductor structure 100 The characteristics of the 122 and the doped regions 131, 132, the field oxide layer 140, the conductive layers 151, 152, and the insulating layers 161, 162 are similar, and therefore will not be described again.

Fig. 2B is a plan view of the field oxide layer 240 of Fig. 2A. As shown, field oxide 240 is a ring structure surrounding doped region 231. In the present embodiment, the doping region 231 is circular. In addition, the conductive layer 251 is also a ring structure, and the field oxide layer 240 is overlapped. In this example, the conductive layer 252 has a spiral structure, and the conductive layer 251 is overlapped. In other embodiments, the conductive layer 251 is a spiral structure and the conductive layer 252 is a ring structure. In some embodiments, the conductive layers 251 and 252 are both spiral structures, as shown in FIG. 1B, or the conductive layers 251 and 252 are both annular structures.

The shape of the conductive layers 251 and 252 is not limited by the present invention. The shape of the conductive layer 251 may be the same or different from the shape of the conductive layer 252. In addition, when the shapes of the conductive layers 251 and 252 are the same, the areas of the conductive layers 251 and 252 may be the same or different. Moreover, when the shapes of the conductive layers 251 and 252 are the same, the conductive layer 251 may completely overlap or partially overlap the conductive layer 252.

3A is another possible cross-sectional view of the semiconductor structure of the present invention. intention. As shown, the semiconductor structure 300 includes a substrate 311, an epitaxial layer 312, well regions 321-323, doped regions 331-333, a field oxide layer 340, a stacked structure 350, and a gate 353. The substrate 311 has a first conductivity type. Since the characteristics of the substrate 311 are similar to those of the substrate 110 of FIG. 1A, they will not be described again. The epitaxial layer 312 is disposed in the substrate 311 and has a first conductivity type. In other embodiments, the epitaxial layer 312 can be omitted.

The well regions 321 to 323 are formed in the epitaxial layer 312. In the present embodiment, well zones 321 and 322 are spatially separated from one another and well zone 321 is located within well zone 323. In a possible embodiment, after the epitaxial layer 312 is formed by epitaxial growth, a doping process (eg, ion cloth value) and thermal diffusion processes may be sequentially performed in the epitaxial layer 312 to make the well region 321~323. Extending in the epitaxial layer 312. In other embodiments, the well zone 323 is a deep high voltage well.

In the present embodiment, the well regions 321 and 323 have a second conductivity type, and the well region 322 has a first conductivity type. In some embodiments, the well regions 321-323 can be formed by an ion implantation step. Taking the well region 321 as an example, when the second conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the well region 321 is to be formed to form the well region 321. However, when the second conductivity type is a P-type, boron ions or indium ions may be implanted in a region where the well region 321 is to be formed to form the well region 321.

The doped region 331 is formed in the well region 321 and has a second conductivity type. Doped regions 332 and 333 are formed in well region 322. Doped region 333 is located between doped regions 331 and 332. In the present embodiment, the doping region 332 has a first conductivity type, and the doping region 333 has a second conductivity type. In a possible embodiment, the doping regions 331 to 333 can be formed by an ion implantation step. Taking the doping region 331 as an example, when the second conductivity type is N-type, phosphorus ions may be implanted in a region where the doping region 331 is to be formed or Arsenic ions form a doped region 331. However, when the second conductivity type is a P-type, boron ions or indium ions may be implanted in a region where the doping region 331 is to be formed to form the doping region 331. In the present embodiment, the doping concentration of the doping regions 331 and 333 is higher than the doping concentration of the well region 321 , and the doping concentration of the doping region 332 is higher than the doping concentration of the well region 322 .

The field oxide layer 340 is disposed on the substrate 311 and between the doping regions 331 and 333. In the present embodiment, field oxide layer 340 extends into well region 321. Field oxide layer 340 is in direct contact with doped region 331, but is not intended to limit the invention. In other embodiments, the field oxide layer 340 may be spatially separated from the doped regions 331.

Stack structure 350 is formed over field oxide layer 340 and contacts field oxide layer 340. In the present embodiment, the stacked structure 350 includes conductive layers 351, 352 and an insulating layer 361, but is not intended to limit the present invention. In other embodiments, the stacked structure 350 has other numbers of conductive layers as well as insulating layers. Since the characteristics of the stacked structure 350 are similar to those of the stacked structure 150 of FIG. 1, they will not be described again. In a possible embodiment, the potentials of the conductive layers 351 and 352 are the same, so the capacitance of the equivalent capacitance formed by the conductive layer 351, the insulating layer 361 and the conductive layer 352 is almost zero.

A gate 353 is disposed over the substrate 311 between the doped regions 331 and 333 and overlaps a portion of the field oxide layer 340 with a portion of the well region 322. In the present embodiment, the gate 353 and the conductive layer 351 are formed in the same process, and the gate 353 and the conductive layer 351 are spatially separated from each other. In a possible embodiment, the gate 353 is the same material as the conductive layer 351. In this embodiment, the gate 353 and the doping regions 331 333 333 form a transistor, wherein the doping region 331 serves as a drain of the transistor, and the doping region 332 serves as a base of the transistor (bulk) ), doped area 333 Is the source of the transistor.

In the embodiment, the semiconductor structure 300 further includes an insulating layer 362. The insulating layer 362 is formed over the insulating layer 361 and the conductive layer 352. Since the characteristics of the insulating layers 361 and 362 are similar to those of the insulating layers 161 and 162 of FIG. 1A, they will not be described again.

The semiconductor structure 300 further includes traces 371-374. Traces 371 to 374 are formed over the insulating layer 362. The trace 371 is electrically connected to the doped regions 332 and 333 through the via holes V31 and V32. In a possible embodiment, traces 371 are used to transfer ground level GND pre-doped regions 332 and 333.

The trace 372 is electrically connected to the gate 353 and a conductive end E1 of the conductive layer 351 through the via holes V33 and V34. In the present embodiment, in order to facilitate the electrical connection of the conductive terminal E1, the conductive terminal E1 does not overlap the conductive end E3 of the conductive layer 352, but is not intended to limit the present invention. In other embodiments, the conductive end E1 may overlap a portion of the conductive end E3. In a possible embodiment, the trace 372 is further coupled to the cathode of an external diode D2. In this example, the anode of diode D2 may be coupled to trace 371.

The trace 373 is electrically connected to the conductive end E3 of the conductive layer 352 through the via hole V35. In a possible embodiment, trace 373 transmits ground level GND to conductive terminal E3. The trace 374 is electrically connected to the conductive end E4 of the conductive layer 352 and the conductive end E2 of the conductive layer 351 through the via holes V36 and V37. In addition, the trace 374 is electrically connected to the doped region 331 through the via hole V38. In a possible embodiment, trace 374 is used to receive a high voltage signal HV.

FIG. 3B is a schematic diagram of an equivalent circuit of the semiconductor structure 300 of the present invention. As shown, the semiconductor structure 300 includes a transistor Q, resistors R3 and R4. In this embodiment, the transistor Q is composed of a gate 353 and doped regions 331 to 333. The composition is such that the doped region 331 serves as the drain of the transistor Q, the doped region 332 serves as the base of the transistor Q, and the doped region 333 serves as the source of the transistor Q. In addition, the resistor R3 represents the equivalent impedance of the conductive layer 351. Resistor R4 represents the equivalent impedance of conductive layer 352. In this embodiment, the drain of the transistor Q receives the high voltage signal HV through the traces 371-374, and is coupled to the resistors R3 and R4. In addition, the gate of the transistor Q is electrically connected to the resistor R3 and the cathode of the diode D2. The source and base of the transistor Q receive the ground level GND.

In a possible embodiment, the diode D2 is independent of the semiconductor structure 300. As shown, the cathode of the diode D2 is coupled to the gate of the transistor Q, and the anode of the diode D2 receives the ground level GND. In a possible embodiment, the diode D2 is a high voltage component. In addition, since the resistor R3 is connected in series with the diode D2, the crystal Q can be electrically conducted. Furthermore, since the resistor R4 is connected in parallel with the transistor Q, the leakage current of the transistor Q can be reduced. In the present embodiment, the resistors R3, R4 and the transistor Q are integrated in the same semiconductor structure.

4A is another schematic cross-sectional view of the semiconductor structure of the present invention. 4A is similar to FIG. 3A except that the field oxide layer 441 of the semiconductor structure 400 is a ring-shaped structure that surrounds the field oxide layer 442 and the doped region 431. In addition, the doped region 431 is also a ring structure surrounding the field oxide layer 442. In the present embodiment, the conductive layers 451 and 452 are spirally extended on the field oxide layer 441, but the invention is not limited thereto. As long as the conductive oxide layers 451 and 452 overlap the field oxide layer 441, the shapes of the conductive layers 451 and 452 may be the same or different. Since the characteristics of the conductive layers 451 and 452 are similar to those of the conductive layers 351 and 352 of FIG. 3, they will not be described again. In addition, the characteristics of the substrate 411, the epitaxial layer 412, the well regions 421 to 423, the doped regions 431 to 433, the field oxide layer 441, and the gate 453 of FIG. 4 are the same as those of the substrate 311 and the epitaxial layer 312 of FIG. , The characteristics of the well regions 321 to 323, the doped regions 331 to 333, the field oxide layer 340, and the gate 353 are similar, and therefore will not be described again.

FIG. 4B is a diagram of a possible top view of the semiconductor structure 400 of the present invention. As shown, the field oxide layer 442 is circular. In this example, doped region 431 is an annular structure that surrounds field oxide layer 442. The field oxide layer 441 is a ring structure surrounding the doped region 431. In the present embodiment, the conductive layers 451 and 452 are both spiral, and the field oxide layer 441 is overlapped. The gate 453 is an annular structure surrounding the field oxide layer 441 and overlapping a portion of the field oxide layer 441. The well region 422 is a ring structure that surrounds the gate 453. As shown, doped region 433 in well region 422 surrounds gate 453. Doped region 432 in well region 422 surrounds doped region 433.

5A-5C illustrate a method of fabricating the semiconductor structure 100 of the present invention. Referring to FIG. 5A, a substrate 110, such as a germanium substrate or an insulating layer overlying germanium (SOI) substrate or other suitable semiconductor substrate having a first conductivity type is provided. Then, the well regions 121 and 122 may be formed in the substrate 110 by processes such as doping process (for example, ion cloth value) and thermal diffusion, wherein the conductivity type of the well region 121 is different from the substrate 110, and the well region 122 The conductivity type is the same as the substrate 110.

Referring to FIG. 5B, a doping region 131 is formed in the well region 121 by a doping process (such as ion cloth value), and a doping region 132 is formed in the well region 122. In the present embodiment, the doping region 131 has the same conductivity type as the well region 121, and the doping region 132 has the same conductivity type as the well region 122. In a possible embodiment, the doping concentration of the doping region 131 is higher than the doping concentration of the well region 121, and the doping concentration of the doping region 132 is higher than the doping concentration of the well region 122. In addition, an isolation structure (such as field oxide layer 140) is formed on the substrate 110. In the present embodiment, field oxide layer 140 extends into well region 121 and is located between doped regions 131 and 132.

Referring to FIG. 5C, a conductive layer 151 is formed on the field oxide layer 140, and then an insulating layer 161 is formed over the conductive layer 151. Next, a conductive layer 152 is formed over the insulating layer 161, and an insulating layer 162 is formed over the conductive layer 152. In the present embodiment, the conductive layer 152 overlaps the conductive layer 151. In other embodiments, a plurality of traces and interconnects can be formed in the semiconductor structure 100. Since the present invention does not limit the interconnect structure of the semiconductor structure 100, the 5C diagram does not show the interconnect structure of the semiconductor structure 100 (such as the traces 171 and 172 and the vias V11 to V16 in FIG. 1).

6A-6C illustrate a method of fabricating the semiconductor structure 300 of the present invention. Referring to FIG. 6A, a substrate 311, such as a germanium or insulating layer overlying (SOI) substrate or other suitable semiconductor substrate having a first conductivity type is provided. An epitaxial layer 312 is formed on the substrate 311, which also has a first conductivity type. After the epitaxial layer 312 is formed by epitaxial growth, the well regions 323 and 322 are formed in the epitaxial layer 312 by processes such as doping process (for example, ion cloth value) and thermal diffusion. In the present embodiment, the well region 323 is a deep well region having a second conductivity type. The second conductivity type is different from the first conductivity type. Well zone 322 has a first conductivity type. Additionally, a well zone 321 is formed within the well zone 323. In the present embodiment, the well region 321 has a second conductivity type.

Referring to FIG. 6B, a doping region 331 is formed in the well region 321 by a doping process (eg, ion cloth value), and doped regions 332 and 333 are formed in the well region 322. In the present embodiment, the doping regions 331 and 333 have the same conductivity type as the well region 321, and the doping region 332 has the same conductivity type as the well region 322. In a possible embodiment, the doping concentrations of the doping regions 331 and 333 are higher than the doping concentration of the well region 321 , and the doping concentration of the doping region 332 is higher than the doping concentration of the well region 322 . In addition, an isolation structure (such as field oxide layer 340) is formed on the substrate 311. In the present embodiment, field oxide layer 340 extends into well region 321 and is located between doped regions 331 and 333.

Referring to FIG. 6C, a conductive layer 351 is formed on the field oxide layer 340. In addition, the gate 353 is formed over the substrate 311. In the present embodiment, the gate 353 overlaps a portion of the well region 322 and a portion of the field oxide layer 340. In a possible embodiment, the gate 353 and the conductive layer 351 are formed by the same process, except that the gate 353 and the conductive layer 351 are insulated from each other. Next, an insulating layer 361 is formed over the conductive layer 351 and the gate 353, and a conductive layer 352 is formed over the insulating layer 361. In the present embodiment, the conductive layer 352 overlaps the conductive layer 351, but is not intended to limit the present invention. In other embodiments, conductive layer 352 may overlap a portion of conductive layer 351. Thereafter, an insulating layer 362 is formed over the conductive layer 352. Since the present invention does not limit the connection relationship between the conductive layers 351 and 352 and other structures (such as the doped regions 331 to 332 or the gate 353), the 6C diagram does not show the interconnect structure (eg, FIG. 3A). Guide holes V31~V38 and traces 371~374).

According to the above embodiment, since a plurality of conductive layers are formed over the field oxide layer, a plurality of resistors may be integrated in the same semiconductor substrate with at least one diode or at least one transistor. Furthermore, by controlling the number of conductive layers, the number and resistance of the resistors can be provided. In addition, the equivalent impedance of the resistor can be controlled by controlling the doping concentration and the extension shape of the conductive layer. In addition, by properly controlling the potential of the conductive layer, the capacitance of the equivalent capacitance between the conductive layers is approximately equal to zero.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning In addition, unless explicitly stated, the definition of vocabulary in a general dictionary should be interpreted as The articles in the related art have the same meaning and should not be interpreted as an ideal state or an excessively formal voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. . For example, the system, apparatus or method of the embodiments of the present invention may be implemented in a physical embodiment of a combination of hardware, software or hardware and software. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (20)

A semiconductor structure comprising: a substrate having a first conductivity type; a first well region formed in the substrate and having a second conductivity type; a first doped region formed in the first well And having the second conductivity type; a second well region formed in the substrate and having the first conductivity type; and a second doping region formed in the second well region And having the first conductivity type; a field oxide layer disposed on the substrate and located between the first and second doped regions; a first conductive layer overlapping the field oxide layer; a first insulating layer, Overlap the first conductive layer; and a second conductive layer overlapping the first insulating layer, wherein the first conductive layer directly contacts the field oxide layer. The semiconductor structure of claim 1, wherein the first well region contacts the second well region. The semiconductor structure of claim 1, wherein the first conductive layer has the same shape or different from the second conductive layer. The semiconductor structure of claim 1, wherein at least one of the first and second conductive layers extends in a spiral shape. The semiconductor structure of claim 1, wherein the first conductive layer has a first conductive end and a second conductive end, the second conductive layer has a third conductive end and a fourth conductive end. For example, the semiconductor structure described in claim 5 includes: a first trace for transmitting a ground potential to the first conductive end, the third conductive end and the second doped region; and a second trace coupled to the second and fourth conductive ends and The first doped region. The semiconductor structure of claim 6, further comprising: a second insulating layer overlapping the second conductive layer; and a third conductive layer overlapping the second insulating layer, wherein the first and second The trace is located above the third conductive layer. The semiconductor structure of claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type. The semiconductor structure of claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type. The semiconductor structure of claim 1, further comprising: an epitaxial layer disposed in the substrate and having the first conductivity type, wherein the first and second well regions are located in the epitaxial layer Among them. The semiconductor structure of claim 1, wherein the first well region and the second well region are spatially separated from each other. The semiconductor structure of claim 11, further comprising: a third doped region disposed in the second well region and located between the field oxide layer and the second doped region, and Having the second conductivity type; a gate disposed on the substrate between the field oxide layer and the third doped region, and overlapping part of the field oxide layer, wherein the gate, the first doping The impurity region and the third doped region constitute a transistor. The semiconductor structure of claim 12, wherein the gate and the first conductive layer are formed in the same process, the gate and the first guide The electrical layers are spatially isolated from one another. The semiconductor structure of claim 12, wherein the first conductive layer has a first conductive end and a second conductive end, the second conductive layer has a third conductive end and a fourth conductive end. The semiconductor structure of claim 14, further comprising: a first trace for coupling the second and third doped regions; a second trace for coupling the gate and a first conductive end; a third trace for coupling the third conductive end; and a fourth trace for coupling the second conductive end, the fourth conductive end, and the first doping Area. The semiconductor structure of claim 1, further comprising: a fourth doped region disposed in the first well region, below the field oxide layer, and having the first conductivity type. The semiconductor structure of claim 1, wherein the material of the first conductive layer is SiCr, metal or Poly. A method of fabricating a semiconductor structure, comprising: providing a substrate having a first conductivity type; forming a first well region in the substrate, wherein the first well region has a second conductivity type; forming a first a doped region in the first well region, wherein the first doped region has the second conductivity type; forming a second well region in the substrate, wherein the second well region has the first conductivity type ; Forming a second doped region in the second well region, wherein the second doped region has the first conductivity type; forming a field oxide layer on the substrate, wherein the field oxide layer is located in the first and the first Between the two doped regions; forming a first conductive layer on the field oxide layer, wherein the first conductive layer directly contacts the field oxide layer; forming a first insulating layer on the first conductive layer; and forming a The second conductive layer is on the first insulating layer. A method of fabricating a semiconductor structure, comprising: providing a substrate having a first conductivity type; forming a first well region in the substrate, wherein the first well region has a second conductivity type; forming a first a doped region in the first well region, wherein the first doped region has the second conductivity type; forming a second well region in the substrate, wherein the second well region has the first conductivity type Forming a second doped region in the second well region, wherein the second doped region has the first conductivity type; forming a third doped region in the second well region, wherein the first doping region a third doped region having the second conductivity type; forming a field oxide layer on the substrate, wherein the field oxide layer is between the first and third doped regions; forming a gate on the substrate, wherein the gate Forming a portion of the field oxide layer and the second well region, and forming a transistor with the first, second, and third doped regions, The first doped region serves as a drain of the transistor, the second doped region serves as a base of the transistor, and the third doped region serves as a source of the transistor; forming a first conductive layer at the a field oxide layer, wherein the first conductive layer and the gate are spatially separated from each other, wherein the first conductive layer directly contacts the field oxide layer; forming a first insulating layer on the first conductive layer; and forming A second conductive layer is on the first insulating layer. The method of fabricating a semiconductor structure according to claim 19, wherein the first and second conductive layers extend in a spiral shape.