TWI630709B - Three-dimensional semiconductor device and method of manufacturing the same - Google Patents

Abstract

A three-dimensional semiconductor device comprising: a substrate comprising an array region and a step region adjacent to the array region, wherein the step region comprises N steps, N is an integer greater than or equal to 1; a stack having a multi-layer structure stacked thereon On the substrate, the multi-layer structure includes an active layer and an insulating layer staggered above the substrate. The stack includes a plurality of sub-stacks formed on the substrate, and the sub-stacks are disposed corresponding to the N steps of the stepped regions to respectively form contact regions, wherein An uppermost active layer layer stacked in each of the contact regions includes a metal germanide layer; and a multilayer structure connector respectively located in the corresponding contact regions, and the multilayer structure connector extends downward to electrically connect the respective sub-stacks a metal telluride layer.

Description

Three-dimensional semiconductor component and method of manufacturing same

The present invention relates to a three-dimensional semiconductor device and a method of fabricating the same, and more particularly to a three-dimensional semiconductor device having a metal silicide and a method of fabricating the same.

A very important feature of non-volatile memory components is the ability to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cells with memory cells to achieve a memory structure with higher storage capacity. For example, some NAND type flash memory structures have been proposed for multilayer thin film transistor stacks. Related companies have proposed three-dimensional memory components of various structures, such as memory cells with single-gate, double-gate memory cells, and memory cells of a surrounding gate. Three-dimensional semiconductor components.

It is hoped by the relevant designers that a three-dimensional semiconductor structure can be constructed, which not only has many layer stacking planes (memory layers) but also achieves higher storage capacity and superior electronic characteristics (for example, good data storage reliability and operation speed). ), so that the memory can be stabilized and fast as operations such as erasing and programming. In general, a conventional three-dimensional semiconductor device deposits an etch stop layer (for example, a tantalum nitride layer) in a staircase area to cover a multi-layered layer of a contact region, so that all the corresponding contact regions are The contact holes are uniformly stopped on the etch stop layer. Thereafter, all of the contact holes are synchronized through the etch stop layer to their corresponding active layers (eg, polysilicon layers). However, the formation of the etch stop layer affects the contact landing windows. If more pairs of oxide-polysilicon layers (ie, known as OP layers) are required to be formed in the development of a three-dimensional semiconductor device, a thicker etch stop layer needs to be formed, and the thicker etch stop layer is formed. It has a greater adverse effect on the contact landing window. Moreover, when the size of the three-dimensional semiconductor component is reduced, the presence of the etch stop layer leaves less space for contacting the landing window, which causes problems for both the process and the structure.

The present invention relates to a three-dimensional semiconductor device and a method of fabricating the same. According to the three-dimensional semiconductor element of the embodiment, the contact landing windows can be greatly increased by forming a metal silicide.

According to an embodiment, a three-dimensional semiconductor device is provided, comprising: a substrate comprising an array area and a staircase area adjacent to the array area, wherein the step area comprises N steps, N An integer greater than or equal to 1; a stack having multi-layers stacked on the substrate, and the multilayer structure including an active layer and an insulating layer interleaved over the substrate, the stack including a plurality of sub-stacks (sub -stacks) formed on the substrate, the sub-stacks being disposed corresponding to the N steps of the stepped regions to respectively form contact regions, wherein an uppermost active layer is stacked in each of the contact regions a system comprising a metal silicide layer; and a multilayered connector, respectively located in the corresponding contact regions, and the multilayer structure connector extending downwardly to electrically connect the metal halides of each of the sub-stacks Floor.

According to an embodiment, a method for fabricating a three-dimensional semiconductor device is provided, comprising: providing a substrate having an array region and a step region of an adjacent array region, wherein the step region includes N steps, and N is an integer greater than or equal to 1; Forming a multi-layered structure stacked on the substrate, and the multi-layer structure includes an active layer and an insulating layer staggered above the substrate, the stack comprising a plurality of sub-stacks formed on the substrate, and the N stacks and the step regions The steps are correspondingly arranged to respectively form contact regions, wherein an uppermost active layer layer stacked in each of the contact regions comprises a metal telluride layer; and the multilayer structure connector is respectively located in the corresponding contact region, and the multilayer structure connector system Extending downwardly to electrically connect the stacked metal halide layers.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

Embodiments of the present disclosure propose a three-dimensional semiconductor component and a method of fabricating the same. According to the embodiment, the contact landing windows are greatly increased by forming a metal silicide in the three-dimensional semiconductor element, regardless of the number of layers of the OP layer stack of the three-dimensional semiconductor element or the three-dimensional semiconductor element. Whether the size is reduced or not is suitable for the application embodiment. Therefore, the design of the metal halide according to the embodiment can provide a wide enough contact drop window for the applied three-dimensional semiconductor component, thereby enhancing the electronic characteristics and performance of the applied component.

The disclosure can be applied to a plurality of three-dimensional semiconductor components having different memory cell array types, such as vertical-channel (VC) three-dimensional semiconductor components and vertical-gate (VG) three-dimensional semiconductor components. There is no particular limitation on the application form of the embodiment. Figure 1 is a perspective view of a three-dimensional semiconductor component. The figure shows a vertical channel type three-dimensional semiconductor component as an example. A three-dimensional semiconductor device comprising a stack (Stack) has a multilayer structure (multi-layers) is stacked on a substrate 10, substrate 10 includes an array area (array area) R _A and R _A one array region adjacent the stepped regions (Staircase Area) R _S , wherein the step region R _S includes N steps, and N is an integer greater than or equal to 1. The multilayer structure includes a plurality of active layers 112 (ie, a memory layer, for example, a control gate included in the VC element) and an insulating layer 113 interleaved over the substrate 10. The three-dimensional semiconductor component further includes a plurality of upper selection lines 12U (the upper selection line may be a common source line (the Common Source Line) is located above the active layer 112 (ie memory layer) in parallel with each other, and the plurality of strings ( The strings are perpendicular to the active layer 112 and the upper select line 12U, wherein the series are electrically connected to the corresponding upper select line 12U. Further, the three-dimensional semiconductor component further includes a plurality of wires 18 (eg, bit lines BLs) located at The upper selection line 12U is above, and the wires 18 are parallel to each other and perpendicular to the upper selection line 12U. The plurality of memory cell systems are respectively defined by the series, the upper selection line 12 U and the wire 18, and the memory cells can be arranged in a plurality of columns. (rows) and complex rows (columns) to form a memory array. Further, a plurality of string contacts 17 are perpendicular to the active layer 112 and the upper selection line 12U, and the arrangement of each string of contacts 17 corresponds to In each column of the memory cell, the serial contact 17 is electrically connected to the corresponding upper selection line 12U and the corresponding wire 18. The three-dimensional semiconductor component further includes other components, and the memory layer has a lower selection below. The lower select lines 12L are formed (the lower selection line may be an inversion gate (IG)).

Furthermore, the stack of the embodiment includes a plurality of sub-stacks formed on the substrate 10, and the sub-stacks are disposed corresponding to the N steps of the step region R _S to form contact regions R _{C , respectively.} . The three-dimensional semiconductor device of the embodiment further includes a plurality of multilayered connectors (not shown in FIG. 1 but can refer to the multilayer structure connectors CT1 - CT8 of FIG. 2 ), respectively located in the corresponding contact regions R _C. According to an embodiment, an uppermost active layer of each sub-stack in the contact region R _C includes a metal silicide layer to cover the landing region (ex: a contact pad, such as a word line A word line pad, and the multilayer structure connector extends downwardly to electrically connect (eg, directly contact) each of the stacked metal halide layers. In one embodiment, the step corresponding to the region R _S R _C times the contact region of the active layer stacked array region R _A system from the active layer (e.g., a polysilicon layer as a word line) which extends embodiment. Hereinafter, a description will be given of one of the three-dimensional semiconductor elements in which the metal germanide is formed in the step region R _S as an example of the three-dimensional semiconductor device of the embodiment, but the disclosure is not limited thereto.

Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings to describe the related configurations and manufacturing methods. Relevant structural details such as related layers and spatial configurations are as described in the following examples. However, the disclosure is not limited to the description, and the disclosure does not show all possible embodiments. The same or similar reference numerals in the embodiments are used to designate the same or similar parts. Furthermore, other implementations not presented in this disclosure may also be applicable. Variations and modifications of the structure of the embodiments can be made in the relevant embodiments without departing from the spirit and scope of the disclosure. The drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to scale in terms of actual products. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

Furthermore, the terms used in the specification and the claims, such as "first", "second", "third" and the like, are used to modify the elements of the claim, which are not intended to be Any previous ordinal does not represent the order of a request element and another request element, or the order of the manufacturing method. The use of these ordinals is only used to make one request element with a certain name the same as the other. Named request elements can make a clear distinction.

FIG. 2 is a cross-sectional view showing a stepped region of a three-dimensional semiconductor device according to an embodiment of the present invention. 3A to 3L illustrate a method of fabricating a three-dimensional semiconductor device in which a metal telluride is formed in a step region according to an embodiment. In Fig. 2 and Figs. 3A to 3L, an embodiment is described by taking 8 pairs of active layers and insulating layers and 8 contact regions (P1-P8; N=8) as an example. Of course, the number of contact regions and the number of active layers in pairs with the insulating layer can be varied as required by the conditions of the actual application. Furthermore, for the purpose of clearly illustrating and illustrating the configuration of the embodiment, some known layers (for example, oxidation) located under 8 pairs of active layers and insulating layers are omitted in FIGS. 2 and 3A to 3L. Drawing of layers, selection line layers, and substrates).

As shown in FIG. 2, the stack of the embodiment includes a plurality of sub-stacks formed over the substrate, and the sub-stacks are disposed in the corresponding contact regions P1, P2 in the step region (such as R _S shown in FIG. 1). , P3, P4, P5, P6, P7 and P8 (ie 8 steps; N=8). Its active layers (such as 212-1, 212-2, 212-3, 212-4, 212-5, 212-6, 212-7) and insulating layers (such as 213-1, 213-2, 213-3, 213-4, 213-5, 213-6, 213-7) are alternately disposed in the stepped region of the three-dimensional semiconductor element of the embodiment. In the step region, the three-dimensional semiconductor device of the embodiment further includes a multilayer structure connector such as CT1, CT2, CT3, CT4, CT5, CT6, CT7 and CT8 respectively located in the corresponding contact regions P1 - P8. Moreover, according to an embodiment, an uppermost active layer of each of the stacked regions in the contact region includes a metal silicide layer; for example, as shown in FIG. 2, the metal halide layer 24- 1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7, and 24-8 are formed in the contact regions P1, P2, P3, P4, P5, P6, P7, and P8, respectively. In one embodiment, for each sub-stack of the contact regions, the active layers under the metal telluride layer may all be polycrystalline germanium layers. Multi-layered structural connectors such as CT1, CT2, CT3, CT4, CT5, CT6, CT7, and CT8 extend downwardly to electrically connect (eg, directly contact) each of the stacked metal halide layers, such as 24-1, 24-2. , 24-3, 24-4, 24-5, 24-6, 24-7, and 24-8.

It should be noted that FIG. 2 only shows one embodiment, that is, the uppermost active layers of each sub-stack are 24-1, 24-2, 24-3, 24-4, 24-5, 24- 6, 24-7 and 24-8, all of which are metal telluride layers, wherein a metal germanide layer can be obtained by completely converting one of the uppermost polycrystalline germanium layers of each sub-stack in the process. However, the disclosure is not limited thereto. In some embodiments, the uppermost active layer of each sub-stack may further include a polysilicon layer and a metal germanide layer formed over the polysilicon layer (for example, by converting a portion of the uppermost polycrystalline layer of each sub-stack, The structural details are described in Figure 4 and related paragraphs).

Furthermore, the three-dimensional semiconductor component further includes a dielectric layer 26 (such as an interlayer dielectric layer (ILD)) formed on the sub-stack of the contact regions (ex: P1-P8). The multilayer structure connectors (ex: CT1, CT2, CT3, CT4, CT5, CT6, CT7, and CT8) extend downwardly in the dielectric layer 26, wherein the dielectric layer 26 directly contacts the metal halide layer 24 of each sub-stack. -1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7 and 24-8. As shown in Fig. 2, the metal halide layers 24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-4 are stacked in the contact regions (P1-P8). 7 and 24-8 are used as landing areas for each sub-stack, and all landing areas (the upper surface of the IE metallization layer) are directly covered by the dielectric layer 26 except for the portion that is contacted by the multilayer structure connectors CT1-CT8. .

Furthermore, according to the three-dimensional semiconductor component of an embodiment, the lateral ends of the active layers of the sub-stacked active layers 212 in the contact regions (ex: P1-P8) include a metal halide portion (silicide) Portions). For example, the metal halide portions 240-3, 240-4, 240-5, 240-6, 240-7, and 240-8 in the contact regions P3-P8 are shown in Fig. 2, respectively. The dielectric layer 26 is in direct contact with the metal halide portions 240-3, 240-4, 240-5, 240-6, 240-7 and 240-8 of the active layer. According to an embodiment, the metal telluride layers 24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7, and 24-8 and the metal telluride portions 240-3, 240 -4, 240-5, 240-6, 240-7, and 240-8 include the same material.

3A to 3L are views showing a method of manufacturing a three-dimensional semiconductor element in which a metal halide is formed in a step region as shown in Fig. 2. Figures 3A through 3F illustrate how one of the N steps can be formed (N = 8 in the figure). It should be noted that the steps shown in Figures 3A through 3F are provided for illustrative purposes only, and other etching methods may be applied to produce corresponding sub-stacks of N steps of the step region.

As shown in FIG. 3A, a multilayer structure includes active layers (eg, 212-1, 212-2, 212-3, 212-4, 212-5, 212-6, 212-7, and 212-8) and insulation. The layers (such as 213-1, 213-2, 213-3, 213-4, 213-5, 213-6, 213-7, and 213-8) are staggered over the substrate (not shown) (for example, including 8 pairs) a polycrystalline germanium layer and an oxide layer; and a conventional OP pair), and a first patterned photo-resist layer PR1 is disposed on the multilayer structure and corresponds to the contact regions P8, P6, P4, and P2. Next, the active layer 212-8 and the insulating layer 213-8 are patterned with the first patterned photoresist layer PR1 to remove the active layer 212-8 and the insulating layer 213 of the corresponding contact regions P1, P3, P5, and P7. -8, as shown in Figure 3B. Thereafter, the first patterned photoresist layer PR1 is removed.

As shown in FIG. 3C, a second patterned photoresist layer PR2 is disposed on the multilayer structure and corresponds to the contact regions P8, P4, P3, and P7. Next, the multilayer structure of the 3Cth layer is patterned by the second patterned photoresist layer PR2 to remove the two pairs of active layers and insulating layers corresponding to the contact regions P6, P2, P1, and P5, as shown in FIG. 3D. . Thereafter, the second patterned photoresist layer PR2 is removed.

As shown in FIG. 3E, a third patterned photoresist layer PR3 is disposed on the multilayer structure and corresponds to the contact regions P8, P6, P5, and P7. Next, the multilayer structure of FIG. 3E is patterned by the third patterned photoresist layer PR3 to remove four pairs of active layers and insulating layers corresponding to the contact regions P4, P2, P1, and P3, as shown in FIG. 3F. . Thereafter, the third patterned photoresist layer PR3 is removed. So far, the N steps (N=8) in the stepped region have been produced and stacked in the corresponding contact regions P1-P8.

As shown in FIG. 3G, the uppermost insulating layer (for example, an oxide layer) of each of P1-P8 stacked in the contact region is completely removed, for example, by etching an oxide. That is, the uppermost insulating layers 213-8, 213-6, 213-4, 213-2, 213 located in the contact regions P8, P6, P4, P2, P1, P3, P5, and P7 (Fig. 3F), respectively. -1, 213-3, 213-5, 213-7 are all completely removed to expose the uppermost active layer.

As shown in FIG. 3H, a metal layer 25 is deposited on an uppermost active layer (eg, a polysilicon layer) stacked in each of the contact regions P1-P8, and the metal layer 25 is also deposited on the exposed sidewalls of the sub-stack (exposed sidewalls). )on. Therefore, the metal layer 25 is carpet-covered on the secondary stack of the contact regions P1 - P8 of the 3H. In one embodiment, the metal layer 25 may comprise cobalt (Co), nickel (Ni), titanium (Ti), or other suitable metallic materials.

Thereafter, as shown in FIG. 3I, the structure is thermally annealed to form metal telluride layers 24-1, 24-2, 24-3, 24-4 in each of the contact regions P1-P8. , 24-5, 24-6, 24-7, and 24-8; in an application example, for example, but not limited to, thermal annealing treatment is performed at a high temperature ranging from 600 ° C to 1000 ° C. Since the metal layer 25 is also deposited on the exposed sidewalls of the sub-stack, after being thermally annealed, it is attached to the active layer of the sub-stack corresponding to the exposed sidewalls (for example, 212-2, 212-3, 212-4, 212-5, The metal halide portions (e.g., 240-3, 240-4, 240-5, 240-6, 240-7, and 240-8) are formed at the respective side ends of 212-6 and 212-7).

In one embodiment, the metal telluride layer comprises at least one of a cobalt-containing telluride, a nickel-containing telluride, a titanium-containing telluride, a molybdenum-containing telluride, and a tungsten-containing telluride. For example, the metal telluride layer may include cobalt telluride (CoSi), cobalt dichloride (CoSi ₂ ), or a mixture of the two. In other embodiments, the metal telluride layer may include titanium telluride (TiSi), titanium dititanide (TiSi ₂ ), or a mixture thereof. In other embodiments, the metal telluride layer may include nickel telluride (NiSi), nickel telluride (NiSi _X , x≠1), or a mixture of the two. For example, materials of other applicable metal telluride layers may also include molybdenum disilicide (MoSi ₂ ), tungsten tungsten silicide (WSi ₂ ). The material of the metal telluride layer varies depending on the thermal annealing treatment conditions in practical use, and the present disclosure does not limit this. The metal halide formed in the examples has a high etching selectivity for the oxide.

As shown in FIG. 3J, the unreacted metal layer 25 (eg, a portion of non-deuterium cobalt) is removed to expose the sub-stacked metal halide layers such as 24-1, 24-2, 24-3, 24-4, 24 -5, 24-6, 24-7 and 24-8, and metal halide parts such as 240-3, 240-4, 240-5, 240-6, 240-7 and 240-8.

Next, an insulating layer such as an interlayer dielectric layer (ILD) is deposited on the sub-stack and subjected to chemical mechanical polishing (CMP) to form the dielectric layer 26, as shown in FIG. 3K. The dielectric layer 26 is in direct contact with each of the stacked metal halide layers 24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7, and 24-8 and direct contact metal deuteration Object parts 240-3, 240-4, 240-5, 240-6, 240-7 and 240-8.

As shown in FIG. 3L, a plurality of multilayer structure connectors CT1, CT2, CT3, CT4, CT5, CT6, CT7, and CT8 are formed to extend downward in the dielectric layer 26 to be deuterated with the metal of each of the contact regions P1-P8. The layers 24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7 and 24-8 are in direct contact. As shown in FIG. 3L/FIG. 2, in an embodiment, a landing area of each sub-stack has a first width (first width) along a first direction (ex: X direction). D1, the metal halide layers 24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7 and 24-8 stacked in each of the contact regions P1-P8 are There is a second width d2 in the first direction, wherein the first width d1 is substantially equal to the second width d2. According to the three-dimensional semiconductor element proposed in the embodiment, since the sub-stacked metal telluride layer in each contact region is used as a landing region, the three-dimensional semiconductor device of the embodiment has a larger size than the conventional three-dimensional semiconductor device. Contact landing windows, in particular for the contact area P1 having only one active layer at the bottom end, the contact drop window is increased more.

FIG. 4 is a cross-sectional view showing a stepped region of a three-dimensional semiconductor device according to another embodiment of the present disclosure. The foregoing FIG. 2 and FIG. 3A-3L are diagrams showing one embodiment, that is, the uppermost active layers of each sub-stack (for example, 212-1, 212-2, 212-3, 212-4, 212-5). , 212-6, 212-7 and 212-8) are all metal telluride layers, wherein the uppermost polycrystalline germanium layer of each sub-stack can be completely used in the thermal annealing treatment step (such as the step shown in FIG. 3I). Converted to get. However, this disclosure is not limited to this. Figure 4 shows that the top active layer of each sub-stack includes a polysilicon layer (for example, 212-8/212-7/212-6/212-5/212-4/212-3/212-2/212- 1) and a metal telluride layer (for example, 24-1'/24-2'/24-3'/24-4'/24-5'/24-6'/24-7'/24-8') Formed above the polysilicon layer. As shown in Fig. 4, metal telluride layers 24-1', 24-2', 24-3', 24-4', 24-5', 24-6', 24-7' and 24-8' It can be obtained by partially converting the uppermost polycrystalline germanium layer of each sub-stack, while the unreacted polycrystalline germanium is located below the metal germanide layer. Furthermore, the metal halide portions 240-3', 240-4', 240-5', 240-6', 240-7', and 240-8' are also formed in each sub-stack (refer to the above embodiment). Content and Figure 2 and Figure 3A-3L). In an example (but not limiting), the uppermost polysilicon layer has a thickness of about 300 Å before the thermal annealing process, and after thermal annealing, a metal telluride layer 24-1 having a thickness of about 200 Å is produced. ', 24-2', 24-3', 24-4', 24-5', 24-6', 24-7' and 24-8', and a polycrystalline layer of approximately 100 Å thick below the metal telluride layer . According to the disclosure, whether the uppermost polysilicon layer of each sub-stack is completely converted or partially converted into metal telluride can be controlled by adjusting the parameters of the thermal annealing process, depending on the requirements of the actual application.

According to the disclosure of the above embodiments, the contact drop window can be greatly increased by forming a metal silicide in the three-dimensional semiconductor element. According to an embodiment, the uppermost active layer of each of the contact regions P1-P8 comprises a metal telluride. For example, in the process, the exposed active layer, such as a polysilicon layer, may be thermally annealed to form a metal telluride layer. According to an embodiment, each of the metal halide layers stacked in each contact region is used as a landing region of each sub-stack, and these landing regions have the same width (d1) to cause the multilayer structure connector to fall, compared to the conventional three-dimensional The semiconductor device (ie uses a tantalum nitride layer as an etch stop layer so that all contact holes corresponding to the respective contact regions can uniformly stop on the etch stop layer), and the three-dimensional semiconductor device of the embodiment has a larger contact drop window . Furthermore, if the number of OP layer stack layers required for the conventional three-dimensional semiconductor element is larger, the thicker the etching stop layer (ex: SiN) is required, which makes the contact drop window of the contact region smaller, especially For the contact area P1 having only one active layer at the bottom end, the contact drop window is shrunk more. However, according to the three-dimensional semiconductor element proposed in the embodiment, it is not necessary to form an etch stop layer to uniformly stop all the contact holes, so that the number of OP layer stack layers required for the developed three-dimensional semiconductor element, or the size of the three-dimensional semiconductor element Whether or not the reduction is made, the landing area of each contact area has a sufficient width (for example, the width d1 or d2 shown in Fig. 2/3L/4) to cause the multilayer structure connector to fall.

Other embodiments, such as known components of components, may have different arrangements and arrangements, and may be applied, depending on the actual needs and conditions of the application, and may be appropriately adjusted or changed. Therefore, the structures shown in the specification and drawings are for illustrative purposes only and are not intended to limit the scope of the disclosure. In addition, it is to be understood by those skilled in the art that the shapes and positions of the components in the embodiments are not limited to those illustrated in the drawings, and the requirements and/or manufacturing steps according to actual applications are not deviated from the spirit of the disclosure. In the case of the situation can be adjusted accordingly.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧Substrate
R _A ‧‧‧Array area
R _S ‧‧‧ ladder area
R _C , P1 , P2 , P3 , P4 , P5 , P6 , P7 , P8‧‧‧ contact areas
12U‧‧‧ top selection line
12L‧‧‧ selection line below
17‧‧‧ Serial contact
18‧‧‧Wire
112, 212-1, 212-2, 212-3, 212-4, 212-5, 212-6, 212-7, 212-8‧‧‧ active layer
113, 213-1, 213-2, 213-3, 213-4, 213-5, 213-6, 213-7, 213-8‧‧‧ insulation
CT1, CT2, CT3, CT4, CT5, CT6, CT7, CT8‧‧‧ multilayer structure connectors
24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7, 24-8, 24-1', 24-2', 24-3', 24-4 ', 24-5', 24-6', 24-7', 24-8'‧‧‧ metal telluride layer
240-3, 240-4, 240-5, 240-6, 240-7, 240-8, 240-3', 240-4', 240-5', 240-6', 240-7', 240 -8'‧‧‧Metal Telluride Part
25‧‧‧metal layer
26‧‧‧Dielectric layer
PR1‧‧‧First patterned photoresist layer
PR2‧‧‧Second patterned photoresist layer
PR3‧‧‧The third patterned photoresist layer
D1‧‧‧first width
D2‧‧‧ second width

Figure 1 is a perspective view of a three-dimensional semiconductor component. FIG. 2 is a cross-sectional view showing a stepped region of a three-dimensional semiconductor device according to an embodiment of the present invention. 3A to 3L illustrate a method of fabricating a three-dimensional semiconductor device in which a metal telluride is formed in a step region according to an embodiment. FIG. 4 is a cross-sectional view showing a stepped region of a three-dimensional semiconductor device according to another embodiment of the present disclosure.

Claims (10)

A three-dimensional semiconductor component, comprising: a substrate comprising an array area and a staircase area adjacent to the array area, wherein the step area comprises N steps, N is greater than or equal to An integer of 1; a stack having multi-layers stacked on the substrate, and the multilayer structure includes an active layer and an insulating layer interleaved over the substrate, the stack including a plurality of sub-stacks Formed on the substrate, the sub-stacks are disposed corresponding to the N steps of the stepped region to respectively form contact regions, wherein the uppermost active layers of the sub-stacks are respectively stacked in the contact regions (an uppermost active layer) includes a metal silicide layer; and a multilayered connector, respectively located in the corresponding contact regions, and the multilayer structure connectors are extended downward to be electrically The metal halide layers stacked one after the other are connected. The three-dimensional semiconductor device of claim 1, further comprising a dielectric layer formed on the sub-stacks of the contact regions, and the plurality of structural connectors are connected to the dielectric The layer extends downwardly, wherein the dielectric layer directly contacts the metal halide layer of each of the plurality of sub-stacks. The three-dimensional semiconductor device of claim 2, wherein the metal silicide layers stacked in the contact regions are used as landing regions of the sub-stacks, and all The landing areas are directly covered by the dielectric layer except for portions that are in contact with the multilayer structure connectors. The three-dimensional semiconductor device of claim 1, wherein the lateral ends of the active layers of the sub-stacks in the contact regions comprise a metal halide portion (silicide) Portions). A method of fabricating a three-dimensional semiconductor device, comprising: providing a substrate having an array region and a step region adjacent to the array region, wherein the step region includes N steps, and N is an integer greater than or equal to 1; Forming one of having multi-layers stacked on the substrate, and the multilayer structure includes an active layer and an insulating layer interleaved over the substrate, the stack including a plurality of sub-stacks formed on the substrate The sub-stacks are disposed corresponding to the N steps of the stepped region to form contact regions respectively, wherein an uppermost active layer of the sub-stacks in the contact regions </ RTI> comprising a metal silicide layer; and forming multilayered connectors are respectively located in the corresponding contact regions, and the plurality of structural connectors are extended downward to electrically connect the respective The metal halide layer is stacked one at a time. The method of claim 5, further comprising forming a dielectric layer on the sub-stacks of the contact regions, and the plurality of structural connectors are in the dielectric layer Extending downwardly, wherein the dielectric layer directly contacts the metal halide layer of each of the plurality of sub-stacks. The method of claim 5, wherein the lateral ends of the active layers of the sub-stacks in the contact regions comprise metal silicide portions . The method of claim 7, wherein the metal halide portions of the active layers are in direct contact with a dielectric layer formed on the sub-stacks of the contact regions. And the plurality of structural connectors extend downward in the dielectric layer. The method of claim 8, wherein the forming the metal silicide layer of each of the sub-stacks comprises: forming the sub-stacks in the contact regions, the sub-stacks comprising a polysilicon layer as The active layer is disposed on the substrate over the substrate; removing an uppermost insulating layer of each of the plurality of contact regions; depositing a metal layer in the contact regions Stacking an uppermost polysilicon layer; and thermally annealing the plurality of sub-stacks and the metal layer to form the metal germanide layer in each of the contact regions. The method of claim 9, wherein the metal layer is also deposited on the exposed sidewalls of the sub-stacks, and after the thermal annealing treatment, the sub-stacks are corresponding to the exposed sidewalls. Each of the active ends of the active layers forms a metal silicide portion.