TWI629764B - Package structure and manufacturing method thereof - Google Patents

Abstract

A package structure and a method of fabricating the same. The package structure includes a circuit substrate, a conductive layer, a wafer, and an encapsulant. The circuit substrate has a line structure, wherein the circuit substrate has a groove at the first surface and a plurality of openings under the groove, the plurality of openings exposing a portion of the line structure, and the first The opposite second surface of the surface exposes a portion of the wiring structure. A conductive layer is disposed on the sidewall and the bottom of the opening. A wafer is disposed in the recess, wherein the wafer has a plurality of bumps, and the plurality of bumps are respectively disposed in corresponding openings. An encapsulant is disposed on the first surface and the wafer.

Description

Package structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a package structure and a method of fabricating the same.

For a package structure in which a wafer is bonded to a wiring substrate by flip chip bonding, the wafer is generally bonded to a wiring substrate, and then a molding process is performed to form a molding compound that coats the wafer.

However, when the wafer is bonded to the circuit substrate by flip-chip bonding, a misalignment between the bump of the wafer and the pad of the circuit substrate is liable to occur, so that the wafer and the circuit substrate cannot be achieved. Effective electrical connection.

In addition, for a thinned package structure, the wafer is thinned prior to bonding the wafer. However, the thinned wafer is liable to have a warpage problem, and thus it is easy to cause the wafer and the wiring substrate to be ineffectively bonded.

In addition, when the encapsulant is formed by a molding process, the encapsulant often cannot completely fill the area between the wafer and the circuit substrate, and a lot of voids are generated in the formed package structure, thereby resulting in reliability of the package structure. reduce.

The present invention provides a package structure in which a wafer is disposed in a recess of a circuit substrate, and a bump of the wafer is disposed in an opening below the recess.

The present invention provides a method of fabricating a package structure for forming the package structure described above.

The package structure of the present invention includes a circuit substrate, a conductive layer, a wafer, and an encapsulant. The circuit substrate has a line structure, wherein the circuit substrate has a groove at the first surface and a plurality of openings under the groove, the plurality of openings exposing a portion of the line structure, and the first The opposite second surface of the surface exposes a portion of the wiring structure. A conductive layer is disposed on the sidewall and the bottom of the opening. A wafer is disposed in the recess, wherein the wafer has a plurality of bumps, and the plurality of bumps are respectively disposed in corresponding openings. An encapsulant is disposed on the first surface and the wafer.

In an embodiment of the package structure of the present invention, a plurality of solder balls are further included, the plurality of solder balls being disposed on the line structure exposed by the second surface.

In an embodiment of the package structure of the present invention, the circuit substrate includes a substrate and a dielectric layer. A portion of the wiring structure is located in the substrate. A dielectric layer is disposed on the substrate, wherein a remaining portion of the wiring structure is located in the dielectric layer, and the dielectric layer has the recess and the plurality of openings.

The manufacturing method of the package structure of the present invention comprises the steps of: providing a circuit substrate having a line structure, wherein the circuit substrate has a groove at a first surface and a plurality of openings under the groove, the plurality of openings Exposing a portion of the wiring structure; forming a conductive layer on sidewalls and a bottom of the opening; providing a wafer having a plurality of bumps; and disposing the wafer in the recess in such a manner that the bump faces the first surface In the slot, wherein the plurality of bumps are respectively located in the corresponding openings; removing a portion of the circuit substrate at a second surface relative to the first surface to expose a portion of the line structure; The first surface forms an encapsulant on the wafer.

In an embodiment of the method for fabricating a package structure of the present invention, the method for forming a circuit substrate includes the steps of: forming a portion of the line structure in a substrate; forming a first dielectric layer on the substrate; Forming a remaining portion of the wiring structure in the first dielectric layer; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has the plurality of openings; Forming a third dielectric layer on the second dielectric layer, wherein the third dielectric layer has the recess.

In an embodiment of the method of fabricating a package structure of the present invention, the conductive layer is formed in the plurality of openings after forming the second dielectric layer and before forming the third dielectric layer.

In an embodiment of the method for fabricating a package structure of the present invention, the method for forming the recess includes the steps of: forming a mask layer in the plurality of openings after forming the conductive layer; Forming a dielectric material layer on the two dielectric layers; forming a mask pattern on the dielectric material layer; removing a portion of the dielectric material layer to form the groove by using the mask pattern as a mask And removing the mask pattern from the mask layer.

In an embodiment of the method of fabricating the package structure of the present invention, after the wafer is disposed in the recess and before the encapsulant is formed, a portion of the wafer may be removed to reduce the The thickness of the wafer.

In an embodiment of the method of fabricating a package structure of the present invention, the surface of the wafer and the first surface are, for example, coplanar.

In an embodiment of the method of fabricating the package structure of the present invention, the method further includes forming a plurality of solder balls on the line structure exposed by the second surface.

Based on the above, in the present invention, since the wafer is not thinned before being bonded to the wiring substrate, the problem that the wafer is warped due to thinning and cannot be effectively bonded to the wiring substrate can be avoided. Further, in the present invention, the encapsulant does not need to be formed between the wafer and the wiring substrate, so that the problem that the encapsulant cannot completely fill the region between the two can be avoided. In addition, in the present invention, the wafer can be accurately bonded to the circuit substrate without being offset by the recess and the opening, so that the wafer can be electrically connected to the wiring substrate.

The above described features and advantages of the invention will be apparent from the following description.

1A-1H are schematic cross-sectional views showing a manufacturing process of a package structure according to an embodiment of the invention. First, referring to FIG. 1A, a line pattern 102 is formed in the substrate 100. The substrate 100 is, for example, a germanium wafer or a glass substrate. The method of forming the line pattern 102 is, for example, first performing a patterning process on the substrate 100 to form the groove pattern 100a in the substrate 100. Then, an electroplating process is performed to form a conductive layer in the groove pattern 100a as the wiring pattern 102. The above conductive layer is, for example, a copper layer.

Then, referring to FIG. 1B, a first dielectric layer 104 covering the line pattern 102 is formed on the substrate 100. The material of the first dielectric layer 104 is, for example, an epoxy resin. Next, a line pattern 106 connected to the line pattern 102 is formed in the first dielectric layer 104. The line pattern 106 includes a wiring layer 106a and a conductive via 106b. The method and materials for forming the line pattern 106 are well known to those skilled in the art and will not be described herein. In the present embodiment, the first dielectric layer 104 has only one wiring layer, but the invention is not limited thereto. In other embodiments, the first dielectric layer 104 can also have multiple layers of circuitry. In the present embodiment, the line pattern 102 located in the substrate 100 and the line pattern 106 located in the first dielectric layer 104 are collectively referred to as a line structure.

Next, referring to FIG. 1C, a second dielectric layer 108 covering the line pattern 106 is formed on the first dielectric layer 104. The material of the second dielectric layer 108 is, for example, an epoxy resin. The second dielectric layer 108 has an opening 108a that exposes a portion of the line pattern 106. The second dielectric layer 108 is formed by, for example, forming a mask pattern prior to the position of the line pattern 106 corresponding to the opening 108a. A layer of dielectric material is then formed in the exposed regions of the mask pattern (eg, using chemical vapor deposition). After that, the mask pattern is removed. As a result, the second dielectric layer 108 having the opening 108a can be formed. In the present embodiment, the sidewall of the opening 108a is inclined to the surface of the first dielectric layer 104, but the invention is not limited thereto. In other embodiments, the sidewall of the opening 108a may also be perpendicular to the surface of the first dielectric layer 104, or the sidewall of the opening 108a may also be curved.

Then, a conductive layer 110 is formed on the sidewalls and the bottom of the opening 108a. The material of the conductive layer 110 is, for example, a conductive resin. The conductive layer 110 is formed by, for example, forming a layer of a conductive material on the second dielectric layer 108 (for example, using a spin coating method), and the conductive material layer fills the opening 108a. Then, a layer of conductive material outside the opening 108a is removed (eg, using a chemical mechanical polishing method). Next, a lithography process and an etch process are performed to remove the layer of conductive material at the central portion of the opening 108a to leave a layer of conductive material on the sidewalls and bottom of the opening 108a. In the present embodiment, since the conductive resin is used as the conductive layer 110, in addition to electrically connecting the elements formed in the opening 108a to the wiring pattern 106, the above-mentioned components can be firmly adhered to the opening. In 108a.

Next, a mask layer 112 is formed in the opening 108a. The material of the mask layer is, for example, a photoresist. The mask layer 112 is formed, for example, by forming a mask material layer on the second dielectric layer 108, and the mask material layer fills the opening 108a. The mask material layer outside the opening 108a is then removed (eg, using chemical mechanical polishing).

Then, referring to FIG. 1D, a third dielectric layer 114 having recesses 114a exposing all of the openings 108a is formed on the second dielectric layer 104. The material of the third dielectric layer 114 is, for example, an epoxy resin. The third dielectric layer 114 is formed by, for example, forming a layer of dielectric material on the second dielectric layer 108 (eg, using chemical vapor deposition). Next, a mask pattern 116 is formed on the dielectric material layer. The material of the mask pattern 116 is, for example, a photoresist. The mask pattern 116 exposes the area where the recess 114a is to be formed. Then, a portion of the dielectric material layer is removed with the mask pattern 116 as a mask (eg, an anisotropic etching process) until the top surface of the conductive layer 110 and the mask layer 112 are exposed.

In particular, the recess 114a is for receiving the wafer to be packaged, so that the recess 114a must have a width no smaller than the width of the wafer to be packaged except that all the openings 108a must be exposed. In addition, since the recess 114a is for accommodating the wafer to be packaged, the depth of the recess 114a (i.e., the thickness of the third dielectric layer 114) is related to the thickness of the finally formed package structure, which will be described later.

Next, referring to FIG. 1E, the mask layer 112 and the mask pattern 116 are removed. In the present embodiment, since the mask layer 112 is the same material as the mask pattern 116 (for example, all of the photoresist), both can be removed simultaneously in the same step. In this way, the fabrication of the circuit substrate 10 having the wiring structure 12 of the present embodiment is completed. That is, in the present embodiment, the circuit substrate 10 includes the substrate 100, the first dielectric layer 104, the second dielectric layer 108, and the third dielectric layer 114, and the circuit substrate 10 has the line pattern 102 and the line pattern. 106 constitutes a line structure 12. In the present embodiment, the surface of the third dielectric layer 114 can be regarded as the first surface 10a of the circuit substrate 10, and the surface of the substrate 100 not provided with the wiring pattern 102 can be regarded as the second surface 10b of the circuit substrate 10.

Then, referring to FIG. 1F, the wafer 117 to be packaged is placed in the recess 114a. In detail, the active area of the wafer 117 has bumps 116a for connection to external components. In this step, the wafer 117 is placed in the recess 114a with the bump 116a facing the first surface 10a of the circuit substrate 10 (that is, in a flip chip manner), and the bump 116a is placed in the opening. In 108a. That is, in the present embodiment, the wafer 117 can be placed in the correct position without being offset by the recess 114a and the opening 108a, thereby enabling the wafer 117 to be electrically connected to the wiring substrate 10 efficiently.

In addition, in the present embodiment, since the conductive layer 110 is disposed on the sidewall and the bottom of the opening 108a, and the material of the conductive layer 110 is a conductive resin, in addition to effectively electrically connecting the wafer 117 and the circuit substrate 10, It is also possible to make the bumps 116a firmly positioned in the opening 108a without being easily separated. Further, in the present embodiment, since the wafer 117 is not thinned before being bonded to the wiring substrate 10, the problem that the wafer is warped due to thinning and thus cannot be effectively bonded to the wiring substrate 10 can be avoided.

Next, referring to FIG. 1G, the second surface 10b is subjected to a polishing process (for example, using a chemical mechanical polishing method), and a portion of the substrate 100 is removed until the wiring pattern 102 is exposed. At this time, the surface of the line pattern 102 and the second surface 10b are coplanar. In addition, in order to meet the requirements of the packaged package structure, the wafer 117 can be selectively subjected to a polishing process (e.g., using chemical mechanical polishing) to reduce the thickness of the wafer 117. In the present embodiment, after the wafer 117 is ground, its surface is coplanar with the first surface 10a. That is, in the present embodiment, the thickness of the polished wafer 117 can be controlled by adjusting the thickness of the third dielectric layer 114, and the final thickness can be controlled by adjusting the thickness of the third dielectric layer 114. The thickness of the package structure meets the requirements. However, the invention is not limited thereto. In other embodiments, the surface of the polished wafer 117 may also be higher than the first surface 10a depending on actual needs.

Thereafter, referring to FIG. 1H, an encapsulant 118 is formed on the first surface 10a. The method of forming the encapsulant 118 is, for example, a molding process. The encapsulant 118 covers the third dielectric layer 114 and the wafer 117. In this embodiment, the bumps 116a of the wafer 117 are located in the opening 108a and are stabilized in the opening 108a by the conductive layer 110. Therefore, the encapsulant 118 does not need to be formed between the wafer 117 and the circuit substrate 10, thereby avoiding the encapsulation. The problem that the gap between the wafer 117 and the wiring substrate 10 is not completely filled and the gap is generated is 118. Thereafter, solder balls 120 are formed on the wiring pattern 102 exposed by the second surface 10b to complete the fabrication of the package structure of the present embodiment.

While the present invention has been described above with reference to the embodiments of the present invention, it is not intended to limit the present invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Package structure
10a‧‧‧ first surface
10b‧‧‧second surface
12‧‧‧Line structure
100‧‧‧Substrate
100a‧‧‧ Groove pattern
102, 106‧‧‧ line pattern
104‧‧‧First dielectric layer
106a‧‧‧Line layer
106b‧‧‧via
108‧‧‧Second dielectric layer
108a‧‧‧ Opening
110‧‧‧ Conductive layer
112‧‧‧ Cover layer
114‧‧‧ Third dielectric layer
114a‧‧‧ Groove
116‧‧‧ mask pattern
116a‧‧‧Bumps
117‧‧‧ wafer
118‧‧‧Package colloid
120‧‧‧ solder balls

1A-1H are schematic cross-sectional views showing a manufacturing process of a package structure according to an embodiment of the invention.

Claims (10)

A package structure comprising: a circuit substrate having a line structure, wherein the circuit substrate has a groove at a first surface and a plurality of openings under the groove, the plurality of openings exposing a portion of the line structure And the second surface opposite to the first surface exposes a portion of the wiring structure; a conductive layer disposed on a sidewall and a bottom of the opening; a wafer disposed in the recess, wherein the wafer has a plurality of And a plurality of bumps respectively disposed in the corresponding openings; and an encapsulant disposed on the first surface and the wafer. The package structure of claim 1, further comprising a plurality of solder balls disposed on the line structure exposed by the second surface. The package structure of claim 1, wherein the circuit substrate comprises: a substrate, wherein a portion of the wiring structure is located in the substrate; and a dielectric layer disposed on the substrate, wherein the A remaining portion of the wiring structure is located in the dielectric layer, and the dielectric layer has the recess and the plurality of openings. A manufacturing method of a package structure, comprising: providing a circuit substrate having a line structure, wherein the circuit substrate has a groove at a first surface and a plurality of openings under the groove, the plurality of openings exposing a portion a wiring structure; forming a conductive layer on the sidewall and the bottom of the opening; providing a wafer having a plurality of bumps; and disposing the wafer in the recess in such a manner that the bump faces the first surface, Wherein the plurality of bumps are respectively located in the corresponding openings; removing a portion of the circuit substrate at a second surface relative to the first surface to expose a portion of the line structure; and An encapsulant is formed on the surface and the wafer. The method for fabricating a package structure according to claim 4, wherein the method for forming the circuit substrate comprises: forming a portion of the line structure in the substrate; forming a first dielectric layer on the substrate; Forming a remaining portion of the wiring structure in the first dielectric layer; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has the plurality of openings; Forming a third dielectric layer on the second dielectric layer, wherein the third dielectric layer has the recess. The method of fabricating a package structure according to claim 5, wherein the conductive is formed in the plurality of openings after forming the second dielectric layer and before forming the third dielectric layer Floor. The method for fabricating a package structure according to claim 6, wherein the forming method of the groove comprises: forming a mask layer in the plurality of openings after forming the conductive layer; Forming a dielectric material layer on the two dielectric layers; forming a mask pattern on the dielectric material layer; removing a portion of the dielectric material layer to form the groove by using the mask pattern as a mask And removing the mask pattern from the mask layer. The method for fabricating a package structure according to claim 4, wherein after the wafer is disposed in the recess and before forming the encapsulant, a portion of the wafer is further removed to reduce The thickness of the wafer. The method of fabricating a package structure according to claim 8 wherein the surface of the wafer is coplanar with the first surface. The method for fabricating a package structure according to claim 4, further comprising forming a plurality of solder balls on the line structure exposed by the second surface.