TWI621335B - Interface transferring module with isolation unit - Google Patents
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Abstract
本發明提供一種具有隔離單元的介面轉換裝置,介面轉換裝置包括一第一介面模組、一介面訊號轉換模組以及一第二介面模組。第一介面模組傳送一第一資料訊號以及一第一時脈訊號通過一隔離單元分別轉換為一第二資料訊號以及一第二時脈訊號。介面訊號轉換模組根據第二資料訊號以及第二時脈訊號,輸出至少一第二介面訊號;第二介面模組電性連接介面訊號轉換模組,傳送至少一第二介面訊號至一電子裝置。 The present invention provides an interface conversion device having an isolation unit. The interface conversion device includes a first interface module, an interface signal conversion module, and a second interface module. The first interface module transmits a first data signal and a first clock signal to be converted into a second data signal and a second clock signal by an isolation unit. The interface signal conversion module outputs at least one second interface signal according to the second data signal and the second clock signal; the second interface module is electrically connected to the interface signal conversion module, and transmits at least one second interface signal to an electronic device .
Description
本發明是有關於一種介面轉換裝置,且特別是一種具有隔離單元的介面轉換裝置。 The present invention relates to an interface conversion device, and more particularly to an interface conversion device having an isolation unit.
由於電子設備若是使用不當則容易造成人身財物等損害,因此各地區的安全規範規定中,對於電子設備的保護等級做出了一些分級,其包括一第一等級(Class I)、第二等級(Class II)以及第三等級(Class III)。第一等級(Class I)的電子設備就是提供接地保護裝置之設備,簡而言之,也就是輸入端的端子具有接地線的。第二等級(Class II)的電子設備,就是未提供接地保護裝置之設備,所以輸入端就可以是未具有接地線的交流連接器。第三等級(Class III)的電子設備則多屬於低壓產品,例如直流直流轉換模組。 If the electronic device is improperly used, it is easy to cause personal property damage. Therefore, in the safety regulations of each region, some classifications are made for the protection level of the electronic device, including a first level (Class I) and a second level ( Class II) and Class III. The Class I electronic device is the device that provides the grounding protection device. In short, the terminal at the input has a grounding wire. The second class (Class II) electronic device is a device that does not provide a grounding protection device, so the input terminal can be an AC connector that does not have a grounding wire. Class III electronic devices are mostly low voltage products, such as DC-DC converter modules.
在安全規範中,有著一次側或是二次側的分別,主要的用意是利用隔離元件將一次側以及二次側離開,以使一次側或是二次側所受到的電擊或是其他問題所引發的損害能夠侷限在單一側中,而不會隨著電路一直蔓延。然而,目前在低壓產品中,特別是介面轉換裝置中,隔離元件多是以光耦合或是電磁耦合的方式來做為隔離元件的信號傳遞方式,光耦合或是電磁耦合方式的隔離元件,則是使用具有一定距離的兩個元件進行光、電訊號以及電訊號的轉換,也就是通過隔離元件的一次側訊號是以非連續式的方式進行傳輸,而不是以連續式的方式進行傳輸,進一步地說,一次側訊號以及二次側訊號之間是經過了至少一次訊號態樣的轉 換。 In the safety specification, there is a difference between the primary side and the secondary side. The main purpose is to use the isolation element to leave the primary side and the secondary side so that the primary side or the secondary side receives an electric shock or other problem. The damage caused can be confined to a single side without spreading along with the circuit. However, in low-voltage products, especially in interface switching devices, the isolation components are mostly optically coupled or electromagnetically coupled as the signal transmission mode of the isolation component, optical coupling or electromagnetic coupling isolation component. The use of two components with a certain distance for the conversion of optical, electrical and electrical signals, that is, the primary side signal through the isolation element is transmitted in a discontinuous manner, rather than in a continuous manner, further Say, there is at least one signal state transition between the primary side signal and the secondary side signal. change.
這類光耦合或是電磁耦合的電磁元件,不僅製程較為複雜,而且成本也較高。此外,若是有較高隔離電壓的需求(例如6KV、10KV),其成本則更為昂貴。 Such optical coupling or electromagnetically coupled electromagnetic components are not only complicated in process but also costly. In addition, if there is a demand for higher isolation voltage (for example, 6KV, 10KV), the cost is more expensive.
因此,提供一種具有低成本隔離元件的介面轉換裝置,則是當今業界的一個重要課題。 Therefore, providing an interface conversion device having a low-cost isolation element is an important issue in the industry today.
有鑑於此,本發明公開了一種具有隔離單元的介面轉換裝置,用於電性連接一控制裝置以及一電子裝置,控制裝置傳送一第一資料訊號以及一第一時脈訊號至介面轉換裝置,介面轉換裝置包括:一第一介面模組,接收從控制裝置傳送的一第一控制裝置發送的發送包括:一第一介面一次側單元,電性連接控制裝置,用於接收第一資料訊號以及第一時脈訊號;一隔離單元,電性連接第一介面一次側單元,第一資料訊號以及第一時脈訊號通過隔離單元分別轉換為一第二資料訊號以及一第二時脈訊號;一介面訊號轉換模組,接收電性連接第一介面模組的隔離單元,接收第二資料訊號以及第二時脈訊號,其中介面訊號轉換模組根據第二資料訊號以及第二時脈訊號,輸出至少一第二介面訊號;一第二介面模組,電性連接介面訊號轉換模組,傳送至少一第二介面訊號至電子裝置。 In view of the above, the present invention discloses an interface switching device having an isolation unit for electrically connecting a control device and an electronic device. The control device transmits a first data signal and a first clock signal to the interface conversion device. The interface switching device includes: a first interface module, and receiving, by the first control device, the transmission sent by the control device includes: a first interface primary side unit, and an electrical connection control device, configured to receive the first data signal and The first clock signal is electrically connected to the primary side primary unit, and the first data signal and the first clock signal are respectively converted into a second data signal and a second clock signal by the isolation unit; The interface signal conversion module receives the isolation unit electrically connected to the first interface module, and receives the second data signal and the second clock signal, wherein the interface signal conversion module outputs according to the second data signal and the second clock signal At least one second interface signal; a second interface module electrically connected to the interface signal conversion module to transmit at least one second interface Number to the electronic device.
其中,隔離單元還包括一第一隔離電路,電性連接第一介面一次側單元,用於接收第一資料訊號;以及一第二隔離電路,電性連接第一介面一次側單元,用於接收第一時脈訊號。 The isolation unit further includes a first isolation circuit electrically connected to the first interface primary side unit for receiving the first data signal, and a second isolation circuit electrically connected to the first interface primary side unit for receiving The first clock signal.
其中,第一隔離電路包括一第一高壓電容,第二隔離電路包括一第二高壓電容。 The first isolation circuit includes a first high voltage capacitor, and the second isolation circuit includes a second high voltage capacitor.
其中,第一高壓電容以及第二高壓電容分別是一耐壓大於0.5千伏特的高壓電容。 The first high voltage capacitor and the second high voltage capacitor are respectively high voltage capacitors with a withstand voltage greater than 0.5 kV.
其中,第一介面一次側單元還包括:一第一介面;以及一第 一放大電路,設置在第一介面以及第二隔離電路之間,用於接收並放大第一資料訊號。 The first interface primary side unit further includes: a first interface; and a first An amplifying circuit is disposed between the first interface and the second isolation circuit for receiving and amplifying the first data signal.
其中,第一介面模組還包括一第二放大電路,設置在第二隔離電路以及介面訊號轉換模組之間,用於接收並放大第二資料訊號。 The first interface module further includes a second amplifying circuit disposed between the second isolation circuit and the interface signal conversion module for receiving and amplifying the second data signal.
其中,第一時脈訊號以及第一資料訊號是通過第一隔離電路以及第二以連續方式傳輸至介面訊號轉換模組。 The first clock signal and the first data signal are transmitted to the interface signal conversion module through the first isolation circuit and the second in a continuous manner.
其中,第一資料訊號以及第二資料訊號是一快捷外設互聯標準資料訊號,第一時脈訊號以及第二時脈訊號是一快捷外設互聯標準時脈訊號。 The first data signal and the second data signal are standard data signals of a fast peripheral interconnection, and the first clock signal and the second clock signal are standard clock signals of a fast peripheral interconnection.
其中,第二介面訊號是一第三代通用序列匯流排介面訊號。 The second interface signal is a third generation universal serial bus interface signal.
其中,第一介面模組、介面訊號轉換模組以及第二介面模組設置在一電路板上。 The first interface module, the interface signal conversion module and the second interface module are disposed on a circuit board.
綜上所述,本發明實施例的介面轉換裝置,具有一可調整耐壓大小的隔離單元,其包括一第一高壓電容以及一第二高壓電容,讓時脈訊號以及資料訊號分別以訊號連續的方式通過第一高壓電容以及第二高壓電容進行傳輸,不僅可以降低隔離單元的成本,更可以降低研發的時間與成本。 In summary, the interface conversion device of the embodiment of the present invention has an isolation unit capable of adjusting the withstand voltage, and includes a first high voltage capacitor and a second high voltage capacitor, so that the clock signal and the data signal are continuously connected by signals. The transmission of the first high-voltage capacitor and the second high-voltage capacitor can not only reduce the cost of the isolation unit, but also reduce the time and cost of development.
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下。 The above described features and advantages of the present invention will be more apparent from the following description.
1‧‧‧介面轉換裝置 1‧‧‧Interface conversion device
2‧‧‧控制裝置 2‧‧‧Control device
11‧‧‧第一介面模組 11‧‧‧First interface module
12‧‧‧第二介面模組 12‧‧‧Second interface module
13‧‧‧介面訊號轉換模組 13‧‧‧Interface signal conversion module
14‧‧‧記憶單元 14‧‧‧ memory unit
111‧‧‧第一介面一次側單元 111‧‧‧First interface primary side unit
113‧‧‧隔離單元 113‧‧‧Isolation unit
CLK1‧‧‧第一時脈訊號 CLK1‧‧‧ first clock signal
CLK2‧‧‧第二時脈訊號 CLK2‧‧‧ second clock signal
S1‧‧‧第一資料訊號 S1‧‧‧ first information signal
S2‧‧‧第二資料訊號 S2‧‧‧Second information signal
D+‧‧‧第二代通用序列匯流排差動訊號正端訊號 D+‧‧‧Second-generation universal serial bus differential signal positive signal
D-‧‧‧第二代通用序列匯流排差動訊號負端訊號 D-‧‧‧Second-generation universal serial bus differential signal negative signal
TX+‧‧‧超高速傳送端差動訊號正端訊號 TX+‧‧‧Super High Speed Transmitter Differential Signal Positive Signal
TX-‧‧‧超高速傳送端差動訊號負端訊號 TX-‧‧‧Super High Speed Transmitter Differential Signal Negative Signal
RX+‧‧‧超高速接收端差動訊號正端訊號 RX+‧‧‧Super High Speed Receiver Differential Signal Positive Signal
RX-‧‧‧超高速接收端差動訊號負端訊號 RX-‧‧‧ super high speed receiver differential signal negative signal
1110‧‧‧第一介面 1110‧‧‧ first interface
1111‧‧‧第一放大電路 1111‧‧‧First Amplifier Circuit
1112‧‧‧第二放大電路 1112‧‧‧second amplification circuit
1131‧‧‧第一隔離電路 1131‧‧‧First isolation circuit
1132‧‧‧第二隔離電路 1132‧‧‧Second isolation circuit
圖1繪示為本發明實施例的介面轉換裝置的示意圖。 FIG. 1 is a schematic diagram of an interface conversion device according to an embodiment of the present invention.
圖2繪示為本發明實施例的介面轉換裝置的部分示意圖。 2 is a partial schematic view of an interface conversion device according to an embodiment of the present invention.
在下文將參看隨附圖式更充分地描述各種例示性實施例,在隨附圖式中展示一些例示性實施例。然而,本發明概念可能以許多不同形式來體現,且不應解釋為限於本文中所闡述之例示性實 施例。確切而言,提供此等例示性實施例使得本發明將為詳盡且完整,且將向熟習此項技術者充分傳達本發明概念的範疇。在諸圖式中,可為了清楚而誇示層及區之大小及相對大小。類似數字始終指示類似元件。 Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as limited to the illustrative embodiments set forth herein. Example. Rather, these exemplary embodiments are provided so that this invention will be in the In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Similar numbers always indicate similar components.
應理解,雖然本文中可能使用術語第一、第二、第三等來描述各種元件,但此等元件不應受此等術語限制。此等術語乃用以區分一元件與另一元件。因此,下文論述之第一元件可稱為第二元件而不偏離本發明概念之教示。如本文中所使用,術語「及/或」包括相關聯之列出項目中之任一者及一或多者之所有組合。 It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the term "and/or" includes any of the associated listed items and all combinations of one or more.
以下將以至少一種實施例配合圖式來說明所述介面轉換裝置,然而,下述實施例並非用以限制本揭露內容。 The interface conversion device will be described below in conjunction with the drawings in at least one embodiment. However, the following embodiments are not intended to limit the disclosure.
〔本發明介面轉換裝置的實施例〕 [Embodiment of Interface Interchange Device of the Present Invention]
請參照圖1以及圖2,圖1繪示為本發明實施例的介面轉換裝置的示意圖。圖2繪示為本發明實施例的介面轉換裝置的部分示意圖。 Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic diagram of an interface conversion device according to an embodiment of the present invention. 2 is a partial schematic view of an interface conversion device according to an embodiment of the present invention.
在本發明實施例中,介面轉換裝置1電性連接一控制裝置2以及一電子裝置(圖未示)。 In the embodiment of the present invention, the interface switching device 1 is electrically connected to a control device 2 and an electronic device (not shown).
介面轉換裝置1包括一第一介面模組11、一第二介面模組12以及一介面訊號轉換模組13。第一介面模組11包括一第一介面一次側單元111以及一隔離單元113。第一介面一次側單元111包括一第一介面1110、一第一放大電路1111以及一第二放大電路1112。在本實施例中午,隔離單元113包括一第一隔離電路1131以及一第二隔離電路1132。在本實施例中,介面轉換裝置1還包括一電路板(圖未示),第一介面模組11、第二介面模組12以及介面訊號轉換模組13皆設置在電路板(圖未示)上。 The interface switching device 1 includes a first interface module 11 , a second interface module 12 , and an interface signal conversion module 13 . The first interface module 11 includes a first interface primary side unit 111 and an isolation unit 113. The first interface primary side unit 111 includes a first interface 1110, a first amplifying circuit 1111, and a second amplifying circuit 1112. At noon in this embodiment, the isolation unit 113 includes a first isolation circuit 1131 and a second isolation circuit 1132. In this embodiment, the interface switching device 1 further includes a circuit board (not shown), and the first interface module 11, the second interface module 12, and the interface signal conversion module 13 are all disposed on the circuit board (not shown) )on.
在本實施例中,介面轉換裝置1通過第一介面模組11的第一介面1110電性連接控制裝置2。第一介面模組11電性連接介面訊號轉換模組13。介面訊號轉換模組13電性連接第二介面模組12。 介面轉換裝置1通過第二介面模組12電性連接至電子裝置(圖未示)。第一介面模組11的第一介面一次側單元111電性連接隔離單元113。隔離單元113則電性連接至介面訊號轉換模組13。 In the embodiment, the interface switching device 1 is electrically connected to the control device 2 through the first interface 1110 of the first interface module 11 . The first interface module 11 is electrically connected to the interface signal conversion module 13 . The interface signal conversion module 13 is electrically connected to the second interface module 12 . The interface switching device 1 is electrically connected to the electronic device (not shown) through the second interface module 12. The first interface primary side unit 111 of the first interface module 11 is electrically connected to the isolation unit 113. The isolation unit 113 is electrically connected to the interface signal conversion module 13 .
在本實施例中,控制裝置2提供一第一資料訊號S1以及一第一時脈訊號CLK1至介面轉換裝置1。在本實施例中,控制裝置2為一具有快捷外設互聯標準介面(Peripheral Component Interconnect Express,PCIE)的電子裝置,在本實施例中,控制裝置2是一具有快捷外設互聯標準介面(Peripheral Component Interconnect Express,PCIE)的電腦設備。 In this embodiment, the control device 2 provides a first data signal S1 and a first clock signal CLK1 to the interface conversion device 1. In this embodiment, the control device 2 is an electronic device having a Peripheral Component Interconnect Express (PCIE). In this embodiment, the control device 2 is a standard interface with a fast peripheral interconnection (Peripheral). Component Interconnect Express, PCIE) computer equipment.
第一介面1110接收到第一時脈訊號CLK1以及第一資料訊號S1之後,則將第一時脈訊號CLK1以及第一資料訊號S1通過第一隔離電路113傳送至介面訊號轉換模組13。 After receiving the first clock signal CLK1 and the first data signal S1, the first interface 1110 transmits the first clock signal CLK1 and the first data signal S1 to the interface signal conversion module 13 through the first isolation circuit 113.
其中,第一時脈訊號CLK1可以經過一第一濾波電路(圖未示),再傳送至第一隔離電路113的第一隔離電路1131進行訊號轉換。 The first clock signal CLK1 can be transmitted to the first isolation circuit 1131 of the first isolation circuit 113 for signal conversion through a first filter circuit (not shown).
在本實施例中,第一資料訊號S1則是可以先經過一第二濾波電路(圖未示)的訊號濾波,再經過第一放大電路1111進行訊號放大,再傳至第二隔離電路1132進行訊號轉換。在本實施例中,第一隔離電路1131以及第二隔離電路1132分別包括一第一高壓電容(圖未示)以及一第二高壓電容(圖未示)。 In this embodiment, the first data signal S1 may be filtered by a second filter circuit (not shown), then amplified by the first amplifier circuit 1111, and then transmitted to the second isolation circuit 1132. Signal conversion. In this embodiment, the first isolation circuit 1131 and the second isolation circuit 1132 respectively include a first high voltage capacitor (not shown) and a second high voltage capacitor (not shown).
在本實施例中,第一時脈訊號CLK1是經過第一隔離電路1131的第一高壓電容(圖未示)的一側,傳至第一高壓電容(圖未示)的另一側,經過訊號轉換而成為第二時脈訊號CLK2。類似於第一時脈訊號CLK1,第一資料訊號S1經過第二隔離電路1132的第二高壓電容(圖未示)的一側,傳至第二高壓電容(圖未示)的另一側,經過訊號轉換後,而成為第二資料訊號S2。 In this embodiment, the first clock signal CLK1 is passed through the side of the first high voltage capacitor (not shown) of the first isolation circuit 1131, and is transmitted to the other side of the first high voltage capacitor (not shown). The signal is converted into a second clock signal CLK2. Similar to the first clock signal CLK1, the first data signal S1 passes through one side of the second high voltage capacitor (not shown) of the second isolation circuit 1132, and is transmitted to the other side of the second high voltage capacitor (not shown). After the signal conversion, it becomes the second data signal S2.
在本實施例中,第一時脈訊號CLK1以及第一資料訊號S1都是具有一高頻載波的電訊號,因此第一時脈訊號CLK1以及第一 資料訊號S1都可以分別以訊號連續的方式,通過第一高壓電容(圖未示)以及第二高壓電容(圖未示),而不是以訊號不連續的方式轉換至隔離電路的另一側。 In this embodiment, the first clock signal CLK1 and the first data signal S1 are both electrical signals having a high frequency carrier, and thus the first clock signal CLK1 and the first The data signal S1 can be switched to the other side of the isolation circuit in a signal continuous manner by a first high voltage capacitor (not shown) and a second high voltage capacitor (not shown) instead of a signal discontinuous manner.
在本實施例中,第一高壓電容(圖未示)以及第二高壓電容(圖未示)是經過安全規範驗證的高壓電容,也就是說第一高壓電容(圖未示)以及第二高壓電容(圖未示)在結構以及耐壓上都是符合安全規範驗證。而第一時脈訊號CLK1以及第一資料訊號S1由於都是具有高頻載波的訊號,因此可以透過一訊號連續方式分別通過第一高壓電容(圖未示)以及第二高壓電容(圖未示)而分別產生一第二時脈訊號CLK2以及一第二資料訊號S2。 In this embodiment, the first high voltage capacitor (not shown) and the second high voltage capacitor (not shown) are high voltage capacitors verified by safety specifications, that is, the first high voltage capacitor (not shown) and the second high voltage. The capacitance (not shown) is verified in accordance with safety regulations in terms of structure and withstand voltage. Since the first clock signal CLK1 and the first data signal S1 are both signals having a high frequency carrier, the first high voltage capacitor (not shown) and the second high voltage capacitor can be respectively passed through a signal continuous manner (not shown) And generating a second clock signal CLK2 and a second data signal S2, respectively.
在本實施例中,第一高壓電容(圖未示)以及第二高壓電容(圖未示)包括一貼片式高壓電容或一陶瓷式高壓電容,在本發明中不作限制。在本實施例中,第一高壓電容(圖未示)以及第二高壓電容(圖未示)的耐壓規格包括:100V、200V、500V、0.75KV、1KV、2KV、3KV、4KV、5KV、6KV、8KV、10KV等不同規格,上述所列規格僅是部分常用規格,在本發明中不作限制。 In the present embodiment, the first high voltage capacitor (not shown) and the second high voltage capacitor (not shown) include a chip type high voltage capacitor or a ceramic high voltage capacitor, which is not limited in the present invention. In this embodiment, the withstand voltage specifications of the first high voltage capacitor (not shown) and the second high voltage capacitor (not shown) include: 100V, 200V, 500V, 0.75KV, 1KV, 2KV, 3KV, 4KV, 5KV, Different specifications such as 6KV, 8KV, and 10KV, the above-listed specifications are only some common specifications, and are not limited in the present invention.
另外,在本實施例中,第一隔離電路1131還包括一溝槽結構(圖未示),設置在第一高壓電容(圖未示)的下方,用於增加安全距離,也就是,設置第一高壓電容(圖未示)的電路板區域中,其下方的電路板是挖空的。相同地,第二隔離電路1132也包括一溝槽結構(圖未示),其設置在第二高壓電容(圖未示)的下方,用於增加安全距離,也就是,設置第二高壓電容(圖未示)的電路板區域,在其下方是挖空的。在本實施例中,第一高壓電容(圖未示)以及第二高壓電容(圖未示)分別是一耐壓6KV的高壓電容,第一高壓電容(圖未示)以及第二高壓電容(圖未示)下方的溝槽結構的寬度,分別具有6mm,也就是在安全規範上的空間距離具有6mm,其可對應6KV的耐壓。在本實施例中,第一隔離電路1131以及第二隔離電路1132的溝槽結構(圖未示)的設計, 是根據第一高壓電容(圖未示)以及第二高壓電容(圖未示)而定,也就是,介面轉換裝置1的隔離電壓規格可以通過適當地更換具有不同耐壓的第一高壓電容(圖未示)以及第二高壓電容(圖未示)以及溝槽結構(圖未示)的設計,即可快速符合不同隔離電壓的安全規範需求。 In addition, in the embodiment, the first isolation circuit 1131 further includes a trench structure (not shown) disposed under the first high voltage capacitor (not shown) for increasing the safety distance, that is, setting the first In the area of the board of a high voltage capacitor (not shown), the board below it is hollowed out. Similarly, the second isolation circuit 1132 also includes a trench structure (not shown) disposed under the second high voltage capacitor (not shown) for increasing the safety distance, that is, setting the second high voltage capacitor ( The area of the board, not shown, is hollowed out below it. In this embodiment, the first high voltage capacitor (not shown) and the second high voltage capacitor (not shown) are respectively a high voltage capacitor with a withstand voltage of 6 kV, a first high voltage capacitor (not shown) and a second high voltage capacitor ( The width of the groove structure below the figure is 6 mm, that is, the space distance on the safety specification has 6 mm, which can correspond to the withstand voltage of 6 kV. In this embodiment, the design of the trench structure (not shown) of the first isolation circuit 1131 and the second isolation circuit 1132, According to the first high voltage capacitor (not shown) and the second high voltage capacitor (not shown), that is, the isolation voltage specification of the interface conversion device 1 can be appropriately replaced by the first high voltage capacitor having different withstand voltage ( The design of the second high-voltage capacitor (not shown) and the trench structure (not shown) can quickly meet the safety specifications of different isolation voltages.
第一時脈訊號CLK1經過第一隔離電路1131的訊號轉換,產生第二時脈訊號CLK2,第二時脈訊號CLK2還可以經過一第三濾波電路(圖未示)進行訊號濾波或是經過一第三放大電路(圖未示)進行訊號放大,才傳送至介面訊號轉換模組13。相同地,第一資料訊號S1經過第二隔離電路1132的訊號轉換,產生第二資料訊號S2,在本實施例中,第二資料訊號S2經過一第二放大電路1112進行訊號放大,才傳送至介面訊號轉換模組13。在其他實施例中,第二資料訊號S2還可以經過一第四濾波電路(圖未示)進行訊號濾波。第四濾波電路(圖未示)可以設置在第二隔離電路1132以及第二放大電路1112之間或是第二放大電路1112以及介面訊號轉換模組之間13,在本發明中不作限制。 The first clock signal CLK1 is converted by the signal of the first isolation circuit 1131 to generate a second clock signal CLK2, and the second clock signal CLK2 can also be subjected to signal filtering or a signal through a third filter circuit (not shown). The third amplifying circuit (not shown) performs signal amplification before being transmitted to the interface signal conversion module 13. Similarly, the first data signal S1 is converted by the second isolation circuit 1132 to generate a second data signal S2. In this embodiment, the second data signal S2 is amplified by a second amplification circuit 1112 before being transmitted to the second data signal S2. Interface signal conversion module 13. In other embodiments, the second data signal S2 can also be subjected to signal filtering through a fourth filter circuit (not shown). The fourth filter circuit (not shown) may be disposed between the second isolation circuit 1132 and the second amplification circuit 1112 or between the second amplification circuit 1112 and the interface signal conversion module, which is not limited in the present invention.
在本實施例中,介面訊號轉換模組13接收第二時脈訊號CLK2以及第二資料訊號S2進行不同介面訊號的轉換,在本實施例中,第一時脈訊號CLK1、第二時脈訊號CLK2、第一資料訊號S1以及第二資料訊號S2皆是快捷外設互聯標準介面(Peripheral Component Interconnect Express,PCIE)的介面訊號格式中的一種介面訊號。第一時脈訊號CLK1以及第二時脈訊號CLK即是快捷外設互聯標準介面(Peripheral Component Interconnect Express,PCIE)的時脈訊號。而第一資料訊號S1以及第二資料訊號S2即是快捷外設互聯標準介面(Peripheral Component Interconnect Express,PCIE)的資料訊號。 In this embodiment, the interface signal conversion module 13 receives the second clock signal CLK2 and the second data signal S2 to perform different interface signal conversion. In this embodiment, the first clock signal CLK1 and the second clock signal are CLK2, the first data signal S1 and the second data signal S2 are all interface signals in the interface signal format of the Peripheral Component Interconnect Express (PCIE). The first clock signal CLK1 and the second clock signal CLK are the clock signals of the Peripheral Component Interconnect Express (PCIE). The first data signal S1 and the second data signal S2 are data signals of the Peripheral Component Interconnect Express (PCIE).
在本實施例中,介面訊號轉換模組13是將快捷外設互聯標準介面(Peripheral Component Interconnect Express,PCIE)的介面 訊號格式轉換為第三代通用序列匯流排(Universal Serial Bus 3.0,USB 3.X)的介面訊號格式。在其他實施例,介面訊號轉換模組13可以是將快捷外設互聯標準介面(Peripheral Component Interconnect Express,PCIE)的介面訊號格式轉換為第二代通用序列匯流排(Universal Serial Bus 2.0,USB 2.0)的介面訊號格式,在本發明中不作限制。 In this embodiment, the interface signal conversion module 13 is an interface of a Peripheral Component Interconnect Express (PCIE) interface. The signal format is converted to the third-generation universal serial bus (Universal Serial Bus 3.0, USB 3.X) interface signal format. In other embodiments, the interface signal conversion module 13 can convert the interface signal format of the Peripheral Component Interconnect Express (PCIE) to the second generation universal serial bus (USB 2.0). The interface signal format is not limited in the present invention.
介面訊號轉換模組13將快捷外設互聯標準介面(Peripheral Component Interconnect Express,PCIE)的介面訊號格式的第二時脈訊號CLK2以及第二資料訊號S2進行介面格式轉換,轉換為第三代通用序列匯流排(Universal Serial Bus 3.0,USB 3.X)的介面訊號格式,也就是一第二代通用序列匯流排差動訊號正端訊號D+、一第二代通用序列匯流排差動訊號負端訊號D-、一超高速傳送端差動訊號正端訊號TX+、一超高速傳送端差動訊號負端訊號TX-、一超高速接收端差動訊號正端訊號RX+以及一超高速接收端差動訊號負端訊號RX-。 The interface signal conversion module 13 converts the second clock signal CLK2 and the second data signal S2 of the interface signal format of the Peripheral Component Interconnect Express (PCIE) into a third generation universal sequence. The interface signal format of the bus (Universal Serial Bus 3.0, USB 3.X), that is, a second-generation universal serial bus differential signal positive signal D+, a second generation universal serial bus differential signal negative signal D-, a super high speed transmission differential signal positive signal TX+, a super high speed transmission differential signal negative signal TX-, an ultra high speed receiving differential signal positive signal RX+ and a super high speed receiving terminal differential Signal negative signal RX-.
介面訊號轉換模組13將上述轉換後的第三代通用序列匯流排介面訊號格式的訊號傳送至第二介面模組12。通過第二介面模組12傳送至電子裝置(圖未示)。 The interface signal conversion module 13 transmits the converted signal of the third generation universal serial bus interface signal format to the second interface module 12. The second interface module 12 is transmitted to an electronic device (not shown).
在本實施例中,第一介面1110是一快捷外設互聯標準介面(Peripheral Component Interconnect Express,PCIE)的連接器,其包括一快捷外設互聯標準介面公座連接器或是一快捷外設互聯標準介面母座連接器。第二介面模組則是一第三代通用序列匯流排(Universal Serial Bus 3.0,USB 3.X)的連接器。 In this embodiment, the first interface 1110 is a connector of a Peripheral Component Interconnect Express (PCIE), which includes a shortcut peripheral interconnect standard interface male connector or a fast peripheral interconnection. Standard interface female connector. The second interface module is a third-generation universal serial bus (USB 3.X) connector.
在本實施例中,介面轉換裝置1還包括一記憶單元14,記憶單元14電性連接介面訊號轉換模組13,用於儲存介面訊號轉換模組的相關資料。 In this embodiment, the interface switching device 1 further includes a memory unit 14 electrically connected to the interface signal conversion module 13 for storing related information of the interface signal conversion module.
〔實施例的可能功效〕 [Possible effects of the examples]
綜上所述,本發明實施例的介面轉換裝置,具有一可調整耐 壓大小的隔離單元,其包括一第一高壓電容以及一第二高壓電容,讓時脈訊號以及資料訊號分別以訊號連續的方式通過第一高壓電容以及第二高壓電容進行傳輸,不僅可以降低隔離單元的成本,更可以降低研發的時間與成本。 In summary, the interface conversion device of the embodiment of the present invention has an adjustable tolerance The pressure-sized isolation unit includes a first high-voltage capacitor and a second high-voltage capacitor, so that the clock signal and the data signal are respectively transmitted through the first high-voltage capacitor and the second high-voltage capacitor in a signal continuous manner, thereby not only reducing isolation The cost of the unit can reduce the time and cost of research and development.
以上所述僅為本發明之實施例,其並非用以侷限本發明之專利範圍。 The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.
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US20040130347A1 (en) * | 2002-05-15 | 2004-07-08 | Moll Laurent R. | Hypertransport/SPI-4 interface supporting configurable deskewing |
US20050091464A1 (en) * | 2003-10-27 | 2005-04-28 | Ralph James | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
US7865661B2 (en) * | 2005-08-05 | 2011-01-04 | Lsi Corporation | Configurable high-speed memory interface subsystem |
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US20040130347A1 (en) * | 2002-05-15 | 2004-07-08 | Moll Laurent R. | Hypertransport/SPI-4 interface supporting configurable deskewing |
US20050091464A1 (en) * | 2003-10-27 | 2005-04-28 | Ralph James | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
US7865661B2 (en) * | 2005-08-05 | 2011-01-04 | Lsi Corporation | Configurable high-speed memory interface subsystem |
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