TWI617030B - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide a thin-film transistor having a small influence on a deviation in alignment of a source electrode and a drain electrode or a variation in pattern width during semiconductor formation. The invented thin film transistor system has a gate electrode, a gate insulating film, and a source electrode and a drain electrode having gaps with each other in a region overlapping the gate electrode when viewed in plan on an insulating substrate. And a thin film transistor having a semiconductor pattern with a region in the gap, the gap has a first region with a fixed interval and a second region with a gradually increasing interval, and the shape of the semiconductor pattern includes the entire region with a constant interval Part of the area.

Description

Thin film transistor and manufacturing method thereof

The invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a thin film transistor suitable for a flexible substrate or a printing method and a manufacturing method thereof.

Based on the transistor or integrated circuit technology using the semiconductor itself as the substrate, manufacture a thin film transistor (TFT) of amorphous silicon (a-Si) or polycrystalline silicon (poly-Si) on a glass substrate, and It is applied to a liquid crystal display and the like (Non-Patent Document 1). As the TFT, for example, as shown in FIG. 13 (the semiconductor shape is not explicitly shown in FIG. 13) is used. Here, the TFT functions as a switch. When the TFT is turned on according to the selection voltage supplied to the gate wiring 2 ′, the signal voltage supplied to the source wiring 4 ′ is written to be connected to the drain electrode 5. Pixel electrode 5 '. The written voltage is held by a storage capacitor composed of the pixel electrode 5 '/ gate insulating film 3 / capacitor electrode 10. The gate insulating film 3 is located higher than the gate electrode 2, the gate wiring 2 ', the capacitor electrode 10, and the capacitor wiring 10', and is located above the source electrode 4, the source wiring 4 ', the drain electrode 5, and the pixel. The electrode 5 'and a semiconductor pattern (not shown) are further lower. A voltage is applied to the capacitor electrode 10 from the capacitor wiring 10 '. Here, in the case of a TFT array, since the roles of the source electrode and the drain electrode change according to the polarity of the written voltage, the source electrode cannot be determined based on the characteristics of the operation. And the name of the drain electrode. Therefore, expediently, one method is called a source electrode and the other is called a drain electrode, and the methods are uniformly called in advance. In the present invention, the one connected to the wiring is referred to as a source, and the one connected to the pixel electrode is referred to as a drain.

[Prior technical literature] [Non-patent literature]

[Non-Patent Document 1] Edited by Masaichi Matsumoto: "Liquid Crystal Display Technology-Active Array LCD" Industry Book, Published November 1996, p.55

In recent years, the emergence of organic semiconductors or oxide semiconductors indicates that TFTs can be manufactured at low temperatures below 200 ° C, and expectations for flexible displays using plastic substrates are rising. In addition to the characteristics of softness, the advantages of light weight, hard damage, and thinness are also expected. In addition, since TFTs are formed by printing, inexpensive and large-area displays are expected.

However, when a flexible substrate or a printing method is used, the alignment deviation becomes larger than when a rigid substrate or a photolithography method is used. The position accuracy of the flexible substrate is poor because of the position accuracy of the substrate itself, and the position accuracy of the printing method is deteriorated due to the movement during printing. In addition, when the viscosity of the ink is small, there is a problem that the pattern width of semiconductor printing is uneven due to the flow after printing.

The size parameters that have the greatest effect on the current characteristics of thin film transistors are the channel length L and the channel width W. A channel is a region in which a current flows in a semiconductor, and a channel length L is a length in a current direction and a channel width W The width in the direction perpendicular to the current. The channel length L is approximately determined by the distance between the source electrode and the drain electrode. If the source electrode and the drain electrode are formed by the same printing, there is no effect of misalignment or semiconductor printing. However, the channel width W is greatly affected by the deviation of the alignment of the source electrode and the drain electrode or the pattern width when the semiconductor is formed. For example, in the case of the pattern design shown in FIGS. 14A to 14C, FIG. 14A is completely designed, but as shown in FIG. 14B, when the semiconductor pattern 6 is shifted to the right, W becomes larger, as shown in FIG. 14C. As shown, when the semiconductor pattern 6 is shifted to the left, W becomes smaller. For example, in the case of the pattern design shown in FIGS. 15A to 15C, FIG. 15A is completely designed, but as shown in FIG. 15B, when the width of the semiconductor pattern 6 becomes larger, W becomes larger, as shown in FIG. 15C. As shown, as the width of the semiconductor pattern 6 becomes smaller, W becomes smaller. As W changes, the current changes proportionally. In addition, the dashed lines indicate the semiconductor edges of the design.

In this manner, unevenness in the channel width due to misalignment of the semiconductors of the source electrode and the drain electrode or pattern width causes the problem of uneven current flow. The change (unevenness) of the current is caused by the need to increase the safety factor (= design current value / required current value) in the transistor of the liquid crystal display or electronic paper, or the scanning transistor of the organic electroluminescence element, that is, set it too large Transistor. In addition, the driving transistor of the organic electroluminescence element has uneven brightness, which deteriorates the image quality.

The present invention was developed in view of the state of the known technology, and an object thereof is to provide a thin film transistor having a small influence on the misalignment of the semiconductors of the source electrode and the drain electrode or the uneven pattern width, and a method for manufacturing the same.

The first invention to solve this problem is a thin-film transistor having a gate electrode, a gate insulating film, and an area overlapping the gate electrode when viewed in a plane in order to be laminated in order. A thin film transistor having a source electrode and a drain electrode having a gap between each other, and a semiconductor pattern having a region in the gap, wherein the gap has a first region with a fixed interval and a second region with an increasing interval. The shape of the semiconductor pattern includes the entire spaced-apart region and a portion of the gradually-increased region.

The second invention is a thin film transistor, and the first invention is an array of thin film transistors in which the gate electrode is connected to the gate wiring, and the source electrode is connected to the source wiring, and the semiconductor pattern is A plurality of thin film transistors are connected along a strip of equal width along the source wiring.

The third invention is a thin film transistor having a gate electrode, a gate insulating film, and a source electrode having a gap with each other in a region overlapping the gate electrode when viewed in plan on an insulating substrate. An electrode and a drain electrode, and a thin film transistor having a semiconductor pattern having a region in the gap, characterized in that the gap has a first region with a fixed interval and a second region with an increasing interval, and the semiconductor pattern is formed on the first 1 area, but the second area is not necessarily formed.

The fourth invention is a thin film transistor, and the third invention is an array of thin film transistors in which the gate electrode is connected to the gate wiring and the source electrode is connected to the source wiring, and the semiconductor pattern is A plurality of thin-film transistor semiconductors are connected along a strip shape along the source wiring.

The fifth invention is a method for manufacturing a thin film transistor, a method for manufacturing a thin film transistor having at least the following steps, and a forming step, which includes a gate electrode, a gate insulating film, And a source electrode and a drain electrode having a gap with each other in a region overlapping the gate electrode when viewed in plan; and a printing step of printing a semiconductor pattern in a region having the gap; the manufacturing method is characterized by the gap The semiconductor pattern has a first region with a fixed interval and a second region with a gradually increasing interval, and the semiconductor pattern is printed so as to include the entirety of the first region and a part of the second region.

A sixth invention is a method for manufacturing a thin film transistor, and in the fifth invention, the printed pattern of the semiconductor pattern is in a strip shape having a constant width along the source wiring.

A seventh invention is a method for manufacturing a thin film transistor, characterized in that in the fifth or sixth invention, the printing of the semiconductor pattern printed so as to include the entirety of the first area and a part of the second area In the pattern, the semiconductor printed on the second region is absorbed by the first region.

An eighth invention is a method for manufacturing a thin film transistor, and in any one of the fifth to seventh inventions, the overlapping portion where the gap in the second region overlaps the printed pattern of the semiconductor pattern has an acute angle.

According to the present invention, it is possible to provide a thin film transistor having a small influence on the misalignment of the semiconductors of the source electrode and the drain electrode or the uneven pattern width, and a method for manufacturing the same.

1‧‧‧ insulating substrate

2‧‧‧Gate electrode

2’‧‧‧Gate wiring

3‧‧‧Gate insulation film

4‧‧‧Source electrode

4’‧‧‧Source wiring

5‧‧‧ Drain electrode

5’‧‧‧pixel electrode

6‧‧‧ semiconductor pattern

6’‧‧‧Printed pattern of semiconductor

7‧‧‧Sealing layer

8‧‧‧ interlayer insulation film

9‧‧‧upper pixel electrode

10‧‧‧Capacitive electrode

10’‧‧‧ capacitor wiring

Fig. 1 is a plan view showing an embodiment of the present invention and a first configuration example of a thin film transistor.

Fig. 2 is a plan view showing an embodiment of the present invention and a second configuration example of a thin film transistor.

FIG. 3A is a diagram illustrating the embodiment of the present invention, and is the first description of the effect of reducing unevenness.

FIG. 3B is a diagram illustrating a second embodiment of the effect of reducing unevenness according to the embodiment of the present invention.

Fig. 4A is a plan view showing an example of the method for manufacturing the thin film transistor of Fig. 2 in the first step.

Fig. 4B is a plan view showing an example of the method for manufacturing the thin film transistor of Fig. 2 in the second step.

FIG. 4C is a plan view showing a third step of an example of the method for manufacturing the thin film transistor of FIG. 2.

FIG. 4D is a plan view showing a fourth step of an example of the method for manufacturing the thin film transistor of FIG. 2.

Fig. 4E is a plan view showing a fifth step of an example of the method for manufacturing the thin film transistor of Fig. 2.

FIG. 4F is a plan view showing the sixth step of an example of the method of manufacturing the thin film transistor of FIG. 2.

Fig. 5 is a plan view showing an embodiment of the present invention and an example of a thin film transistor.

Fig. 6A is a plan view showing an example of the method for manufacturing the thin film transistor of Fig. 5 in the first step.

FIG. 6B is a plan view showing a second step of an example of the method for manufacturing the thin film transistor of FIG. 5. FIG.

FIG. 6C is a plan view showing a third step of an example of the method of manufacturing the thin film transistor of FIG. 5.

Fig. 7 is a plan view showing an embodiment of the present invention and a third configuration example of a thin film transistor.

Fig. 8 is a plan view showing an embodiment of the present invention and a fourth configuration example of a thin film transistor.

Fig. 9A is a plan view showing an embodiment of the present invention and is the first description of the semiconductor flow effect.

Fig. 9B is a plan view showing an embodiment of the present invention, and is the second description of the semiconductor flow effect.

Fig. 10A is a plan view showing an example of the method for manufacturing the thin film transistor of Fig. 8 in the first step.

FIG. 10B is a plan view showing an example of the method of manufacturing the thin film transistor of FIG. 8 in the second step.

Fig. 10C is a plan view showing a third step of an example of the method of manufacturing the thin film transistor of Fig. 8.

FIG. 10D is a plan view showing an example of a method of manufacturing the thin film transistor of FIG. 8 in a fourth step.

Fig. 10E is a plan view showing a fifth step of an example of the method of manufacturing the thin film transistor of Fig. 8.

Fig. 10F is a plan view showing an example of the method of manufacturing the thin film transistor of Fig. 8 in the sixth step.

Figure 10G is an example of a method for manufacturing the thin film transistor of Figure 8 A plan view showing the seventh step.

Fig. 11 is a plan view showing an embodiment of the present invention and an example of a thin film transistor.

FIG. 12A is a plan view showing an example of the method of manufacturing the thin film transistor of FIG. 11 in the first step.

FIG. 12B is a plan view showing an example of the method of manufacturing the thin film transistor of FIG. 11 in the second step.

FIG. 12C is a plan view showing a third step of an example of the method of manufacturing the thin film transistor of FIG. 11.

Fig. 12D is a plan view showing an example of the method for manufacturing the thin film transistor of Fig. 11 in the fourth step.

FIG. 13 is a plan view showing a conventional technique and a configuration example of a thin film transistor.

Fig. 14A is a plan view showing a conventional technique and a first pattern design example of a thin film transistor.

FIG. 14B is a plan view showing the first pattern deviation in the pattern design of FIG. 14A.

Fig. 14C is a plan view showing a second pattern deviation in the pattern design of Fig. 14A.

Fig. 15A is a plan view showing a conventional technique and a second pattern design example of a thin film transistor.

Fig. 15B is a plan view showing the deviation of the first pattern in the pattern design of Fig. 15A.

Fig. 15C is a plan view showing the second pattern deviation in the pattern design of Fig. 15A.

[Form of Implementing Invention]

Hereinafter, embodiments of the present invention will be described in detail using drawings. In addition, in the drawings used below, for easy understanding and explanation, the scale is not drawn correctly.

[First Embodiment]

Examples of the thin film transistor according to the first embodiment of the present invention are shown in plan views in FIGS. 1, 2 and 5. As shown in FIG. 1, FIG. 2, and FIG. 5, the thin film transistor system of this embodiment includes a gate electrode 2, a gate wiring 2 ′, a capacitor electrode 10, and a capacitor wiring 10 ′ on an insulating substrate 1. A gate insulating film 3 is provided thereon, and there are a source electrode 4 and a drain electrode 5, a source wiring 4 ′, and a drain electrode having gaps in an area overlapping with the gate electrode 2 when viewed from above. The pixel electrode 5 ′ to which the electrode electrode 5 is connected has a thin film transistor having a semiconductor pattern 6 having a region as a gap between the source electrode 4 and the drain electrode 5. Further, in the thin film transistor, the gap between the source electrode 4 and the drain electrode 5 has a region with a constant interval and a region with an increasing interval. The shape of the semiconductor pattern 6 includes the entire interval with a constant interval and a gradually increasing interval. Part of the area. The fixed-interval area may be linear as shown in FIG. 5, or may be a polygonal shape having corners as shown in FIG. 1, or may be rounded as shown in FIG. 2. Curve shape. In addition, since the insulating substrate 1 is enlarged to the entirety of the lowermost layer in FIGS. 1, 2, and 5, the boundary line system is not particularly shown, and this is the same in other drawings. The source wiring 4 'refers to a portion that connects each of the source electrode 4 of the thin-film transistor and the output of the source electrode driving circuit. However, the source wiring 4' also serves as a source in the drawing. Since the electrode 4, that is, a part of the source wiring 4 'becomes the source electrode 4, the source electrode 4 is also marked with the symbol 4'.

3A and 3B, the effect of the edge of the semiconductor pattern 6 in a region where the interval is gradually increased will be described. In the case where the edge of the semiconductor pattern 6 is located at a fixed interval L (FIG. 3A) as usual, if the edge (solid line) of the semiconductor pattern 6 is shifted from the design position (dashed line) only by Δx, the channel width The channel length changes only by Δx / L. On the other hand, in the case of this embodiment (FIG. 3B), the channel width / channel length of the portion with increasing intervals becomes W1 / (L1-L) × ln [{(L1-L) / W2 + L} / L], if the edge of the semiconductor pattern is shifted by △ x, the channel width / channel length only changes by △ x / {(L1-L) / W1 × W2 + L}, which is as small as the previous value of L / { (L1-L) / W1 × W2 + L} times (in the case of L1> L). Among them, L is the interval between the fixed portions, L1 is the interval at the widened tip, W1 is the dimension corresponding to the x direction of the slope, and W2 is the design value from the slope starting position to the edge of the semiconductor. For example, in the case of L = 10 μm, L1 = 30 μm, W1 = 20 μm, and W2 = 10 μm, the amount of change in channel width / channel length is one and a half of that in the past. With this effect, unevenness in channel width can be reduced. In FIGS. 1 and 2, unevenness in channel width caused by misalignment of semiconductor printing can be reduced. In FIG. 5, unevenness in channel width caused by unevenness in pattern width of semiconductor printing can be reduced. In addition, the above-mentioned mathematical formula is a case where the slope is linearly expanded, but even if the slope is not linear, it has similar effects. The present invention is not limited to the case of a linear slope.

In addition, as shown in FIGS. 4A to 4F and FIGS. 6A to 6C, the method for manufacturing a thin film transistor of this embodiment has at least the following The method of manufacturing a thin film transistor includes the steps of forming a gate electrode 2 on an insulating substrate 1; the step of forming a gate insulating film 3 thereon; and forming a region overlapping with the gate electrode 2 when viewed from above A step of a source electrode 4 and a drain electrode 5 having a gap; and a step of printing a semiconductor pattern 6 so that there is a region between the source electrode 4 and the drain electrode 5; the manufacturing method is characterized by: the source The gap between the electrode electrode 4 and the drain electrode 5 has a region with a constant interval and a region with a gradually increasing interval, and a semiconductor pattern 6 is printed so as to include the entire region with a fixed interval and a part of a region with a gradually increasing interval.

The insulating substrate 1 may be a rigid one such as a glass substrate, and may also be polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), or polyimide. Ethene imine (PEI), polyethersulfone (PES) and other soft ones.

A gate electrode 2 is formed thereon (FIG. 4A, FIG. 6A). Generally, the gate electrode 2 is connected to a gate wiring 2 '. The capacitor electrode 10 may be provided on the same layer, and the capacitor electrode 10 and the capacitor wiring 10 'may be connected. As the gate electrode 2, the gate wiring 2 ', the capacitor electrode 10, and the capacitor wiring 10', a metal such as Al, Ag, Cu, Cr, Ni, Mo, Au, Pt, or a conductive oxide such as ITO can be used. , Carbon, conductive polymer, etc. As a manufacturing method, the ink may be printed and fired, or formed by photo-etching or photoresist peeling after full film formation. Or formed by photoresist printing, etching, and photoresist stripping after full film formation.

Next, as shown in FIGS. 4A and 6A, a gate insulating film 3 is formed in a mesh pattern. As the gate insulating film 3, can be used SiO _2, SiON, SiN etc. inorganic, polyvinyl phenol (PVP), epoxy resin, etc. The organic matter. The manufacturing method can be obtained by vacuum deposition such as sputtering or CVD, or coating and firing of a solution.

Further, a source electrode 4 and a drain electrode 5 are formed (FIGS. 4B and 6B). Here, the source electrode 4 and the drain electrode 5 have a gap in a region overlapping the gate electrode 2 when viewed from above, and the gap has a region with a fixed interval and a region with an increasing interval. The source electrode 4 is generally connected to the source wiring 4 ', and the drain electrode 5 is generally connected to the pixel electrode 5'. As the source electrode 4 and the drain electrode 5, metals such as Ag, Cu, Cr, Ni, Mo, Au, Pt, and Al, or conductive oxides such as ITO, carbon, and a conductive polymer can be used. As a manufacturing method, it may be formed by photo-etching or photoresist peeling after full film formation, but it is preferably obtained by printing and firing the ink. As a printing method, screen printing, gravure printing, flexographic printing, and lithographic printing are suitable. In particular, patterns of 20 μm or less can be formed with high reproducibility by gravure, flexographic, and lithographic systems.

Then, a semiconductor pattern 6 is formed on the substrate in the state of FIG. 4B or 6B. At this time, a printed pattern 6 ′ of the semiconductor immediately after printing is formed so that the semiconductor pattern 6 includes the entire area of the fixed interval and a portion of the gradually increasing interval (FIGS. 4C and 6C). The semiconductor pattern 6 may be independent of each transistor, or may be a strip shape connected in a direction parallel to the source wiring 4 ′. As the semiconductor pattern 6, organic semiconductors such as polythiophene, acene, and allylamine, or In ₂ O ₃ , Ga ₂ O ₃ , ZnO, SnO ₂ , InGaZnO, InGaSnO, and InSnZnO can be used. Series of oxide semiconductors. As a manufacturing method, the method of printing and baking a solution with inkjet, a dispenser, flexographic printing, etc. is suitable.

It is preferable that the printed pattern 6 'of the semiconductor has a simple shape. This is because the simpler the shape, the easier it is to print. The most preferable is the shape of the semiconductor connection of the TFTs arranged in the stripe width parallel to the source wiring 4 'in the longitudinal direction. In this case, the misalignment in the longitudinal direction has no effect on the characteristics. The second best is a shape in which a rectangle is arranged in each TFT. In this case, if the misalignment in the longitudinal direction is small, it has no effect on the characteristics.

By applying appropriate waveforms to the gate wiring 2 'and the source wiring 4' of the TFT produced in this way, the potential of the pixel electrode 5 'can be controlled, and electronic paper and the like can be displayed.

Depending on the situation, a sealing layer 7 (FIG. 4D) covering the semiconductor pattern 6 or an interlayer insulating film 8 (shown as a pattern in FIG. 4E) having an opening A on the pixel electrode 5 'may be further provided, or via the opening A The upper pixel electrode 9 is connected to the pixel electrode 5 '(FIG. 4F). When the semiconductor pattern 6 is band-shaped, the sealing layer 7 is also preferably band-shaped. Moreover, the semiconductor pattern 6 may be independent, and the sealing layer 7 may be band-shaped. As the sealing layer 7, use of the organic fluorine resin, or SiO _2, SiN, SiON, etc. inorganic material, or a mixture of those, laminate and the like. As a manufacturing method, after the entire film formation, a method of photolithography etching and photoresist removal may be used, but a method of printing and firing the solution by screen printing or the like is more suitable. As the interlayer insulating film 8, an organic insulating film such as epoxy resin is suitable, and as the upper pixel electrode 9, Ag paste or the like is suitable. Both can be printed and fired by a method such as screen printing. When the interlayer insulating film 8 and the upper pixel electrode 9 are provided, by applying appropriate waveforms to the gate wiring 2 ′ and the source wiring 4 ′, the potential of the upper pixel electrode 9 can be controlled, and electronic paper and the like can be displayed. .

[Second Embodiment]

7, 8 and 11 are plan views showing examples of a thin film transistor according to a second embodiment of the present invention. As shown in FIG. 7, FIG. 8 and FIG. 11, the thin film transistor system of this embodiment has a gate electrode 2, a gate wiring 2 ′, a capacitor electrode 10 and a capacitor wiring 10 ′ on an insulating substrate 1 A gate insulating film 3 is provided thereon, and there are a source electrode 4 and a drain electrode 5, a source wiring 4 ', and a pixel electrode having gaps in an area overlapping with the gate electrode 2 when viewed from above. 5 ', and has a semiconductor pattern 6 having a region such as a gap between the source electrode 4 and the drain electrode 5. In the thin film transistor, the gap between the source electrode 4 and the drain electrode 5 has a region with a fixed interval and a region with a gradually increasing interval. The semiconductor pattern 6 is formed in a region with a fixed interval, and is not formed in a region with a gradually increasing interval. The spaced-apart region may be linear as shown in FIG. 11, or a polygonal shape with corners as shown in FIG. 7, or a curve with rounded corners as shown in FIG. 8. shape.

In addition, as shown in FIGS. 10A to 10G and 12A to 12D, the method for manufacturing a thin film transistor of this embodiment is a method for manufacturing a thin film transistor having at least the following steps. A step of forming a gate electrode 2; a step of forming a gate insulating film 3 thereon; a step of forming a source electrode 4 and a drain electrode 5 having a gap in an area overlapping the gate electrode 2 as viewed from above; and The step of printing the semiconductor pattern 6 in such a manner that the gap between the source electrode 4 and the drain electrode 5 has a region; the manufacturing method is characterized in that the gap between the source electrode 4 and the drain electrode 5 has a region with a fixed interval and Increasingly spaced areas The printed pattern 6 'of the semiconductor is printed in such a manner as to include the entire spaced-apart region and a portion of the gradually-increased region.

In the case of this embodiment, the source electrode 4 and the drain electrode Among the gaps between the electrodes 5, the semiconductor printed on the area where the interval is gradually increased as shown in FIG. 9A is absorbed by the area where the interval is fixed as shown in FIG. 9B. This is the effect of surface tension. In the region where the distance between the source electrode 4 and the drain electrode 5 gradually increases, the gap between the source electrode 4 and the drain electrode 5 and the overlapping portion of the semiconductor printed pattern 6 'have an acute angle, and can be smoothly absorbed. semiconductor.

The difference from the first embodiment is that the viscosity of the main semiconductor ink works. In the first embodiment, since the viscosity of the ink is large, the flow of the ink after printing hardly occurs, and the printed pattern 6 'becomes the semiconductor pattern 6 almost intact. On the other hand, in the second embodiment, since the viscosity of the ink is small, the flow of the ink after printing tends to occur. By the surface tension of the semiconductor ink, the semiconductor ink is more stable in the area with a fixed (narrow) interval than in the area with an increasing interval. In addition, since the semiconductor ink is relatively stable near the source electrode 4 and the drain electrode 5, the overlapping portion where the gap between the source electrode 4 and the drain electrode 5 and the semiconductor printed pattern 6 'overlaps has an acute angle, such as As shown in FIG. 9A, since the direction in which the semiconductor ink is attracted by the source electrode 4 or the drain electrode 5 is close to the direction in which the semiconductor ink is attracted by a region with a fixed interval, the effect of the region with a fixed interval can be enhanced.

The insulating substrate 1 may be a rigid one such as a glass substrate, and may also be polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), or polyimide. Etherimide (PEI), polyethersulfone (PES) and other soft people.

A gate electrode 2 is formed thereon (FIGS. 10A and 12A). Generally, the gate electrode 2 is connected to a gate wiring 2 '. The capacitor electrode 10 may be provided on the same layer, and the capacitor electrode 10 and the capacitor wiring 10 'may be connected. As the gate electrode 2, the gate wiring 2 ', the capacitor electrode 10, and the capacitor wiring 10', metals such as Al, Ag, Cu, Cr, Ni, Mo, Au, Pt, or conductive oxides such as ITO can be used. , Carbon, conductive polymer, etc. As a manufacturing method, the ink may be printed and fired, or formed by photo-etching or photoresist peeling after full film formation. Or formed by photoresist printing, etching, and photoresist stripping after full film formation.

Next, as shown in FIG. 10A and FIG. 12A, a gate insulating film 3 is formed in a mesh pattern. As the gate insulating film 3, an inorganic substance such as SiO ₂ , SiON, SiN, or the like, or an organic substance such as polyvinyl phenol (PVP), epoxy resin, or the like can be used. The manufacturing method can be obtained by vacuum deposition such as sputtering or CVD, or coating and firing of a solution.

Further, a source electrode 4 and a drain electrode 5 are formed (FIGS. 10B and 12B). Here, the source electrode 4 and the drain electrode 5 have a gap in a region overlapping the gate electrode 2 when viewed from above, and the gap has a region with a fixed interval and a region with an increasing interval. The source electrode 4 is generally connected to the source wiring 4 ', and the drain electrode 5 is generally connected to the pixel electrode 5'. As the source electrode 4 and the drain electrode 5, metals such as Ag, Cu, Cr, Ni, Mo, Au, Pt, and Al, or conductive oxides such as ITO, carbon, and a conductive polymer can be used. As a manufacturing method, it may be formed by photo-etching or photoresist peeling after full film formation, but it is preferably obtained by printing and firing the ink. As a printing method, screen printing, gravure Suitable for printing, flexographic printing, and lithographic printing. In particular, patterns of 20 μm or less can be formed with high reproducibility by gravure, flexographic, and lithographic systems.

Then, a printed pattern 6 ′ of the semiconductor is formed so as to include the entire area with the fixed interval and a part of the gradually increasing interval (FIGS. 10C and 12C). As shown above, the printed pattern 6 ′ is absorbed by the region where the distance between the source electrode 4 and the drain electrode 5 is fixed (FIGS. 10D and 12D). As the semiconductor pattern 6, organic semiconductors such as polythiophene, acene, and allylamine, or In ₂ O ₃ , Ga ₂ O ₃ , ZnO, SnO ₂ , InGaZnO, InGaSnO, and InSnZnO can be used. Series of oxide semiconductors. As a manufacturing method, the method of printing and baking a solution with inkjet, a dispenser, flexographic printing, etc. is suitable.

It is preferable that the printed pattern 6 'of the semiconductor has a simple shape. This is because the simpler the shape, the easier it is to print. The most preferable is the shape of the semiconductor connection of the TFTs arranged in the stripe width parallel to the source wiring 4 'in the longitudinal direction. In this case, the misalignment in the longitudinal direction has no effect on the characteristics. The second best is a shape in which a rectangle is arranged in each TFT. In this case, if the misalignment in the longitudinal direction is small, it has no effect on the characteristics.

By applying appropriate waveforms to the gate wiring 2 'and the source wiring 4' of the TFT produced in this way, the potential of the pixel electrode 5 'can be controlled, and electronic paper and the like can be displayed.

Depending on circumstances, a sealing layer 7 (FIG. 10E) covering the semiconductor pattern 6 or an interlayer insulating film 8 (FIG. 10F) having an opening A on the pixel electrode 5 'may be further provided, or the pixel electrode 5 may be connected through the opening A. 'Connect the upper pixel electrode 9 (Fig. 10G). When the semiconductor pattern 6 is band-shaped, the sealing layer 7 is also preferably band-shaped. Moreover, the semiconductor pattern 6 may be independent, and the sealing layer 7 may be band-shaped. As the sealing layer 7, use of the organic fluorine resin, or SiO _2, SiN, SiON, etc. inorganic material, or a mixture of those, laminate and the like. As the manufacturing method, after the entire film formation, a method of photolithography and photoresist removal may be used, but a method of printing and firing the solution by screen printing or the like is more suitable. As the interlayer insulating film 8, an organic insulating film such as epoxy resin is suitable, and as the upper pixel electrode 9, Ag paste or the like is suitable. Both can be printed and fired by a method such as screen printing. When the interlayer insulating film 8 and the upper pixel electrode 9 are provided, by applying appropriate waveforms to the gate wiring 2 ′ and the source wiring 4 ′, the potential of the upper pixel electrode 9 can be controlled, and electronic paper and the like can be displayed. .

[Example] (First Embodiment)

An embodiment of the present invention will be described with reference to FIGS. 4A to 4C. According to the steps of FIGS. 4A to 4C, the device shown in FIG. 2 is produced. First, on the PEN as the insulating substrate 1, Al was deposited to a thickness of 50 nm by vapor deposition, and then gate electrode 2 and capacitor electrode 10 were formed by photolithography and wet etching (FIG. 4A). Next, a polyvinyl phenol solution was spin-coated and fired at 150 ° C., thereby forming 1 μm of polyvinyl phenol as the gate insulating film 3 (FIG. 4A). Furthermore, as the source electrode 4, the source wiring 4 ', the drain electrode 5 and the pixel electrode 5', Ag ink was reverse-printed and fired at 180 ° C to form a pattern (Fig. 4B). Further, a polythiophene solution (viscosity 100 mPa · s) was flexographically printed and fired at 100 ° C., thereby forming a semiconductor layer 6 (FIG. 4C).

When the current unevenness of the thin film transistor manufactured in this way was examined, it was about half of the unevenness of the first comparative example described later.

(Second Embodiment)

An embodiment of the present invention will be described using FIGS. 6A to 6C. The device shown in FIG. 5 is manufactured according to the steps of FIGS. 6A to 6C. First, on the PEN as the insulating substrate 1, Al was deposited to a thickness of 50 nm by vapor deposition, and then the gate electrode 2 was formed by photolithography and wet etching (FIG. 6A). Next, a polyvinyl phenol solution was spin-coated and fired at 150 ° C., thereby forming 1 μm of polyvinyl phenol as the gate insulating film 3 (FIG. 6A). Furthermore, as the source electrode 4, source wiring 4 ', drain electrode 5 and pixel electrode 5', Ag ink was reverse-printed and fired at 180 ° C to form a pattern (Fig. 6B). Furthermore, a polythiophene solution (viscosity 100 mPa · s) was flexographically printed and fired at 100 ° C to form a semiconductor layer 6 (Fig. 6C).

When the current unevenness of the thin film transistor manufactured in this way was examined, it was about half of the unevenness of the second comparative example described later.

(3rd Embodiment)

Embodiments of the present invention will be described with reference to Figs. 10A to 10D. According to the steps of FIGS. 10A to 10D, the device shown in FIG. 8 is fabricated. First, on the PEN as the insulating substrate 1, Al is deposited to a thickness of 50 nm by vapor deposition, and then gate electrode 2 and capacitor electrode 10 are formed by photolithography and wet etching (FIG. 10A). Next, a polyvinyl phenol solution was spin-coated and fired at 150 ° C., thereby forming 1 μm of polyvinyl phenol as the gate insulating film 3 (FIG. 10A). Further, as the source electrode 4, source wiring 4 ', drain electrode 5 and pixel electrode 5', Ag ink was reverse-printed and fired at 180 ° C to form a pattern (Fig. 10B). Furthermore, a polythiophene solution (viscosity: 10 mPa · s) was flexographically printed and fired at 100 ° C., thereby forming a semiconductor layer 6 (FIGS. 10C to 10D).

When the current unevenness of the thin film transistor manufactured in this way was examined, it was about 1/3 of the unevenness of the first comparative example described later.

(Fourth embodiment)

Embodiments of the present invention will be described with reference to Figs. 12A to 12D. The device shown in FIG. 11 is manufactured according to the steps of FIGS. 12A to 12D. First, on the PEN as the insulating substrate 1, Al is deposited to a thickness of 50 nm by vapor deposition, and then the gate electrode 2 is formed by photolithography and wet etching (FIG. 12A). Next, a polyvinyl phenol solution was spin-coated and fired at 150 ° C., thereby forming 1 μm of polyvinyl phenol as the gate insulating film 3 (FIG. 12A). Furthermore, as the source electrode 4, source wiring 4 ', drain electrode 5 and pixel electrode 5', Ag ink was reverse-printed and fired at 180 ° C to form a pattern (Fig. 12B). Furthermore, a polythiophene solution (viscosity: 10 mPa · s) was flexographically printed and fired at 100 ° C., thereby forming a semiconductor layer 6 (FIGS. 12C to 12D).

When the current unevenness of the thin film transistor manufactured in this way was examined, it was about 1/3 of the unevenness of the second comparative example described later.

(First Comparative Example)

A comparative example is described using FIGS. 14A to 14C. The components shown in FIG. 14A are produced by steps similar to those in FIGS. 4A to 4C. First, on the PEN as the insulating substrate 1, Al is deposited to a thickness of 50 nm by vapor deposition, and then the gate electrode 2 and the capacitor electrode 10 are formed by photolithography and wet etching. Next, a polyvinyl phenol solution was spin-coated and fired at 150 ° C., thereby forming 1 μm of polyvinyl phenol as the gate insulating film 3. Further, Ag source ink 4, source wiring 4 ', drain electrode 5 and pixel electrode 5' were reverse-printed and fired at 180 ° C to form a pattern. Further, flexo A polythiophene solution (viscosity 100 mPa · s) was printed and fired at 100 ° C to form a semiconductor layer 6.

In the thin film transistor manufactured in this manner, current unevenness caused by the positional deviation of the semiconductor pattern (FIG. 14B and FIG. 14C) occurred.

(Second Comparative Example)

A comparative example is described using FIGS. 15A to 15C. The device shown in FIG. 15A is manufactured according to steps similar to those in FIGS. 6A to 6C. First, on the PEN as the insulating substrate 1, Al is deposited to a thickness of 50 nm by vapor deposition, and then the gate electrode 2 and the capacitor electrode 10 are formed by photolithography and wet etching. Next, a polyvinyl phenol solution was spin-coated and fired at 150 ° C., thereby forming 1 μm of polyvinyl phenol as the gate insulating film 3. Further, Ag source ink 4, source wiring 4 ', drain electrode 5 and pixel electrode 5' were reverse-printed and fired at 180 ° C to form a pattern. Furthermore, a polythiophene solution (viscosity: 10 mPa · s) was flexographically printed and fired at 100 ° C. to form a semiconductor layer 6.

In the thin-film transistor fabricated in this way, current unevenness caused by unevenness in semiconductor pattern widths (FIGS. 15B and 15C) occurred.

As can be understood from the above description, the present invention has the following effects. One effect is that the gap between the source electrode and the drain electrode has a first region with a fixed interval and a second region with an increasing interval. By forming a semiconductor pattern including the entirety of the first region and a part of the second region, The effect of misalignment on channel width is reduced. Another effect is printed in the gap between the source electrode and the drain electrode on the semiconductor in the second area. The body is absorbed by the first region, whereby the channel width is approximately determined by the first region, and the effect of misalignment or uneven channel width can be reduced. Since the gap between the source electrode and the drain electrode in the portion located in the second region and the overlapping portion of the semiconductor printed pattern have an acute angle, the movement of the semiconductor becomes smoother.

[Industrial availability]

The present invention is a thin film transistor that can be applied to liquid crystal display devices, electronic paper, organic electroluminescence display devices, and the like.

1‧‧‧ insulating substrate

2‧‧‧Gate electrode

2’‧‧‧Gate wiring

3‧‧‧Gate insulation film

4‧‧‧Source electrode

4’‧‧‧Source wiring

5‧‧‧ Drain electrode

5’‧‧‧pixel electrode

6‧‧‧ semiconductor pattern

10‧‧‧Capacitive electrode

10’‧‧‧ capacitor wiring

Claims (9)

A thin film transistor has a gate electrode, a gate insulating film, and a source electrode and a drain electrode having gaps with each other in a region overlapping with the gate electrode when viewed in plan on an insulating substrate. An electrode, and a thin film transistor having a semiconductor pattern having a region in the gap, characterized in that the gap has a first region with a fixed interval and a second region with an increasing interval, and the shape of the semiconductor pattern includes regions with a fixed interval The whole and part of the increasing space. For example, the thin film transistor of the first patent application range, wherein the thin film transistor system is an array of thin film transistors in which the gate electrode is connected to the gate wiring, the source electrode is connected to the source wiring, and the semiconductor pattern is along the A plurality of thin film transistors are connected to form a strip of equal width of the source wiring. A thin film transistor has a gate electrode, a gate insulating film, and a source electrode and a drain electrode having gaps with each other in a region overlapping with the gate electrode when viewed in plan on an insulating substrate. An electrode, and a thin film transistor having a semiconductor pattern having a region in the gap, wherein the gap has a first region with a fixed interval and a second region with an increasing interval; the semiconductor pattern is formed in the first region; The second region is not necessarily formed. For example, in the thin film transistor of the third scope of the patent application, the thin film transistor system is an array of thin film transistors in which the gate electrode is connected to the gate wiring, and the source electrode is connected to the source wiring. A plurality of thin-film transistor semiconductors are connected to form a strip of the source wiring. A method for manufacturing a thin film transistor is a method for manufacturing a thin film transistor having at least the following steps. The forming step includes a gate electrode, a gate insulating film, and a planar view on an insulating substrate. A source electrode and a drain electrode having a gap with each other in a region overlapping the gate electrode; and a printing step of printing a semiconductor pattern in the region with the gap; the manufacturing method is characterized in that the gap has a fixed interval The first region and the second region having an increasing interval are printed with the semiconductor pattern so as to include the entirety of the first region and a part of the second region. For example, the method for manufacturing a thin film transistor in the fifth item of the patent application, wherein the printed pattern of the semiconductor pattern is a stripe of equal width along the source wiring. For example, a method for manufacturing a thin film transistor of the scope of application for a patent No. 5 or 6, wherein the printed pattern of the semiconductor pattern printed in a manner including the entirety of the first region and a part of the second region is printed on the The semiconductor in the second region is absorbed by the first region. For example, the method for manufacturing a thin film transistor of claim 5 or 6, wherein an overlapping portion where the gap in the second region overlaps with the printed pattern of the semiconductor pattern has an acute angle. For example, the method of manufacturing a thin film transistor of claim 7 in which the overlapping portion where the gap in the second region overlaps with the printed pattern of the semiconductor pattern has an acute angle.