TWI614862B - Substrate structure and the manufacture thereof - Google Patents
Substrate structure and the manufacture thereof Download PDFInfo
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- TWI614862B TWI614862B TW106101182A TW106101182A TWI614862B TW I614862 B TWI614862 B TW I614862B TW 106101182 A TW106101182 A TW 106101182A TW 106101182 A TW106101182 A TW 106101182A TW I614862 B TWI614862 B TW I614862B
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- layer
- conductive
- insulating
- substrate
- substrate body
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- 239000000758 substrate Substances 0.000 title claims abstract description 109
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 238000002161 passivation Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 9
- 238000013461 design Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 116
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- 238000009413 insulation Methods 0.000 description 9
- 229910052732 germanium Inorganic materials 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920003192 poly(bis maleimide) Polymers 0.000 description 3
- 238000005728 strengthening Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- FYADHXFMURLYQI-UHFFFAOYSA-N 1,2,4-triazine Chemical compound C1=CN=NC=N1 FYADHXFMURLYQI-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一種基板結構，係包括：基板本體、設於該基板本體一側之絕緣部、設於該絕緣部中之導電層、形成於該基板本體中並電性連接該導電層之導電穿孔、以及形成於該基板本體另一側並電性連接該導電穿孔之金屬層，以藉由該基板本體之設計而強化該基板結構的強度。本發明復提供該基板結構之製法。 A substrate structure includes: a substrate body, an insulating portion disposed on a side of the substrate body, a conductive layer disposed in the insulating portion, a conductive via formed in the substrate body and electrically connected to the conductive layer, and forming The metal layer of the conductive via is electrically connected to the other side of the substrate body to strengthen the strength of the substrate structure by the design of the substrate body. The invention provides a method of fabricating the substrate structure.
Description
本發明係有關一種半導體結構，尤指一種基板結構及其製法。 The present invention relates to a semiconductor structure, and more particularly to a substrate structure and a method of fabricating the same.
隨著電子產業技術不斷創新，以及電子封裝產品趨向輕薄、高效能、高密度分佈等方向發展，使封裝型式已由平面演變成三維堆疊，進而使三維積體電路(3D integrated circuits,3D ICs)成為現今封裝技術的主要趨勢。 With the continuous innovation of the electronics industry technology and the trend of electronic packaging products tending to be thin, high-performance, high-density distribution, the package type has evolved from a plane to a three-dimensional stack, thereby enabling 3D integrated circuits (3D ICs). Become the main trend of today's packaging technology.
習知三維積體電路式半導體封裝件係將一半導體晶片藉由複數銲錫凸塊設於一矽中介板(Through Silicon interposer，簡稱TSI)上，其中，該矽中介板具有複數導電矽穿孔(Through-silicon via，簡稱TSV)及電性連接該些導電矽穿孔與該些銲錫凸塊之線路重佈層(Redistribution layer，簡稱RDL)，且該矽中介板藉由該些導電矽穿孔與複數導電元件結合至一封裝基板上，再以底膠包覆該些導電元件與該些銲錫凸塊，並以封裝膠體包覆該半導體晶片與該矽中介板。 The conventional three-dimensional integrated circuit type semiconductor package has a semiconductor wafer disposed on a through silicon interposer (TSI) by a plurality of solder bumps, wherein the germanium interposer has a plurality of conductive germanium vias (Through) a -silicon via (TSV for short) and electrically connecting the conductive vias and the redistribution layer (RDL) of the solder bumps, and the germanium interposer is perforated and electrically conductive by the conductive vias The component is bonded to a package substrate, and the conductive components and the solder bumps are coated with a primer, and the semiconductor wafer and the germanium interposer are coated with an encapsulant.
第1A至1C圖係為習知如晶圓狀(Wafer type)矽中介板 之基板結構1之半成品加工方法之剖視示意圖。 1A to 1C are conventional wafer-like (wafer type) interposers A schematic cross-sectional view of a semi-finished product processing method of the substrate structure 1.
如第1A圖所示，提供一矽板體11，其上形成有一線路層110及氧化層12，並透過黏著層100結合至一玻璃載板10上。 As shown in FIG. 1A, a slab body 11 is provided having a wiring layer 110 and an oxide layer 12 formed thereon and bonded to a glass carrier 10 through the adhesive layer 100.
如第1B圖所示，接著移除該矽板體11。 As shown in Fig. 1B, the slab body 11 is then removed.
如第1C圖所示，形成一絕緣層13於該氧化層12與該線路層110上，再形成一金屬層14於該絕緣層13上，以及形成導電穿孔140於該絕緣層13中，使該金屬層14藉由該導電穿孔140電性連接該線路層110，再形成銲錫凸塊15於該金屬層14上，使該基板結構1藉由該些銲錫凸塊15結合其它電子裝置(圖略)。 As shown in FIG. 1C, an insulating layer 13 is formed on the oxide layer 12 and the wiring layer 110, and a metal layer 14 is formed on the insulating layer 13, and conductive vias 140 are formed in the insulating layer 13. The metal layer 14 is electrically connected to the circuit layer 110 through the conductive vias 140, and the solder bumps 15 are formed on the metal layer 14, so that the substrate structure 1 is combined with other electronic devices by the solder bumps 15 (Fig. slightly).
惟，習知基板結構1中，因其結構強度不佳，而容易在生產過程中產生破裂的問題。 However, in the conventional substrate structure 1, the structural strength is not good, and it is easy to cause cracking during the production process.
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的問題。 Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明提供一種基板結構，係包括：基板本體，係具有相對之第一表面與第二表面；絕緣部，係設於該基板本體之第一表面上；導電層，係設於該絕緣部中；導電穿孔，係形成於該基板本體中並連通該第一表面與第二表面且延伸至該導電層，以令該導電穿孔電性連接該導電層；以及金屬層，係形成於該基板本體之第二表面上以電性連接該導電穿孔。 The present invention provides a substrate structure comprising: a substrate body having opposite first and second surfaces; and an insulating portion disposed on the first surface of the substrate body; a layer is disposed in the insulating portion; a conductive via is formed in the substrate body and communicates with the first surface and the second surface and extends to the conductive layer to electrically connect the conductive via to the conductive layer; A metal layer is formed on the second surface of the substrate body to electrically connect the conductive vias.
本發明復提供一種基板結構之製法，係包括：提供一 矽基板，該矽基板係包含一具有相對之第一表面與第二表面的基板本體、設於該第一表面上之絕緣部及設於該絕緣部中之導電層；於該基板本體之第二表面形成穿孔，其中，該穿孔連通該第一表面與第二表面並延伸至該導電層，以令該導電層外露於該穿孔；以及形成金屬層於該基板本體之第二表面上，且形成導電穿孔於該穿孔中，以令該金屬層藉由該導電穿孔電性連接該導電層。 The invention provides a method for fabricating a substrate structure, which comprises: providing a a substrate comprising a substrate body having a first surface and a second surface opposite to each other, an insulating portion disposed on the first surface, and a conductive layer disposed in the insulating portion; Forming a through hole, wherein the through hole communicates with the first surface and the second surface and extends to the conductive layer to expose the conductive layer to the through hole; and forms a metal layer on the second surface of the substrate body, and A conductive via is formed in the via hole to electrically connect the metal layer to the conductive layer through the conductive via.
前述之基板結構及其製法中，該絕緣部係包含結合於該第一表面上之第一絕緣層、設於該第一絕緣層上之第二絕緣層與設於該第二絕緣層上之第三絕緣層，其中，該導電層設於該第一絕緣層上而位於該第二絕緣層與第三絕緣層中，且該導電層係外露於該第三絕緣層。 In the above substrate structure and method of manufacturing the same, the insulating portion includes a first insulating layer bonded to the first surface, a second insulating layer disposed on the first insulating layer, and a second insulating layer disposed on the second insulating layer a third insulating layer, wherein the conductive layer is disposed on the first insulating layer and located in the second insulating layer and the third insulating layer, and the conductive layer is exposed to the third insulating layer.
前述之基板結構及其製法中，該基板本體之第二表面上復形成有開口，其中，該開口可連通該第一表面與第二表面，以令該絕緣部外露於該開口。 In the foregoing substrate structure and method of manufacturing the same, an opening is formed on the second surface of the substrate body, wherein the opening can communicate with the first surface and the second surface to expose the insulating portion to the opening.
前述之基板結構及其製法中，復包括於形成該穿孔之前，將該絕緣部結合至一承載件上。 In the foregoing substrate structure and method of manufacturing the same, the insulating portion is coupled to a carrier before forming the through hole.
前述之基板結構及其製法中，復包括形成導電元件於該金屬層上。 In the foregoing substrate structure and method of fabricating the same, the method further comprises forming a conductive element on the metal layer.
由上可知，本發明之基板結構及其製法中，主要藉由該矽基板包含該基板本體之設計，以強化該基板結構之整體結構強度，故相較於習知技術，本發明之基板結構可避免在生產過程中產生破裂的問題。 It can be seen from the above that in the substrate structure and the manufacturing method thereof, the substrate structure of the substrate is mainly included by the germanium substrate to strengthen the overall structural strength of the substrate structure, so the substrate structure of the present invention is compared with the prior art. The problem of cracking during the production process can be avoided.
1,2‧‧‧基板結構 1,2‧‧‧substrate structure
10‧‧‧玻璃載板 10‧‧‧glass carrier
100‧‧‧黏著層 100‧‧‧Adhesive layer
11‧‧‧矽板體 11‧‧‧矽板
110‧‧‧線路層 110‧‧‧Line layer
12‧‧‧氧化層 12‧‧‧Oxide layer
13‧‧‧絕緣層 13‧‧‧Insulation
14,24‧‧‧金屬層 14,24‧‧‧metal layer
140,240‧‧‧導電穿孔 140,240‧‧‧Electrical perforation
15‧‧‧銲錫凸塊 15‧‧‧ solder bumps
2a‧‧‧矽基板 2a‧‧‧矽 substrate
2b‧‧‧強化構造 2b‧‧‧Strengthening structure
20‧‧‧承載件 20‧‧‧Carrier
200‧‧‧結合層 200‧‧‧ bonding layer
21‧‧‧基板本體 21‧‧‧Substrate body
21a‧‧‧第一表面 21a‧‧‧ first surface
21b‧‧‧第二表面 21b‧‧‧ second surface
210‧‧‧導電層 210‧‧‧ Conductive layer
22‧‧‧絕緣部 22‧‧‧Insulation
22a‧‧‧第一絕緣層 22a‧‧‧First insulation
22b‧‧‧第二絕緣層 22b‧‧‧Second insulation
22c‧‧‧第三絕緣層 22c‧‧‧ third insulation
220‧‧‧穿孔 220‧‧‧Perforation
23‧‧‧鈍化層 23‧‧‧ Passivation layer
230‧‧‧連接部 230‧‧‧Connecting Department
241‧‧‧墊部 241‧‧‧Mats
25‧‧‧導電元件 25‧‧‧Conductive components
320‧‧‧開口 320‧‧‧ openings
9‧‧‧圖案化光阻 9‧‧‧patterned photoresist
t‧‧‧厚度 T‧‧‧thickness
第1A至1C圖係為習知基板結構之半成品加工方法之剖面示意圖；第2A至2E圖係為本發明之基板結構之製法之剖視示意圖；第3A圖係為本發明之基板結構之另一實施例的局部剖視示意圖；以及第3B圖係為第3A圖形成金屬層後之局部上視平面圖。 1A to 1C are schematic cross-sectional views showing a method of processing a semi-finished product of a conventional substrate structure; 2A to 2E are schematic cross-sectional views showing a method of fabricating the substrate structure of the present invention; and FIG. 3A is another embodiment of the substrate structure of the present invention; A partial cross-sectional view of an embodiment; and FIG. 3B is a partial top plan view of the third layer after forming a metal layer.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.
第2A至2E圖係為本發明之基板結構2之製法之剖視 示意圖。 2A to 2E are cross-sectional views showing the manufacturing method of the substrate structure 2 of the present invention. schematic diagram.
如第2A圖所示，提供一矽基板2a，其包含一具有相對之第一表面21a與第二表面21b的基板本體21、一設於該第一表面21a上之絕緣部22、及至少一設於該絕緣部22中之導電層210。接著，將該絕緣部22結合至一承載件20上。 As shown in FIG. 2A, a substrate 2a is provided, which includes a substrate body 21 having a first surface 21a and a second surface 21b opposite thereto, an insulating portion 22 disposed on the first surface 21a, and at least one A conductive layer 210 disposed in the insulating portion 22. Next, the insulating portion 22 is bonded to a carrier 20.
於本實施例中，該基板本體21係為矽晶圓、矽中介板(TSI)或玻璃基板，且該基板本體21係作為非線路區，而該絕緣部22與該導電層210係作為線路區。 In this embodiment, the substrate body 21 is a germanium wafer, a germanium interposer (TSI) or a glass substrate, and the substrate body 21 is used as a non-line region, and the insulating portion 22 and the conductive layer 210 are used as a line. Area.
再者，該絕緣部22係包含結合於該第一表面21a上之第一絕緣層22a、設於該第一絕緣層22a上之第二絕緣層22b與設於該第二絕緣層22b上之第三絕緣層22c，其中，該導電層210設於該第一絕緣層22a上並位於該第二與第三絕緣層22b,22c中。例如，形成該第一絕緣層22a之材質係為氧化矽(SiO2)、氮化矽(SixNy)或如聚苯並噁唑(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、苯基環丁烯(benzocyclobutane，簡稱BCB)、雙馬來醯亞胺三嗪(Bismaleimide Triazine，簡稱BT)等之有機絕緣材，且形成該第二與第三絕緣層22b,22c之材質係為如聚苯並噁唑(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、苯基環丁烯(benzocyclobutane，簡稱BCB)、雙馬來醯亞胺三嗪(Bismaleimide Triazine，簡稱BT)等之有機絕緣材。 In addition, the insulating portion 22 includes a first insulating layer 22a bonded to the first surface 21a, a second insulating layer 22b disposed on the first insulating layer 22a, and a second insulating layer 22b disposed on the second insulating layer 22b. The third insulating layer 22c is disposed on the first insulating layer 22a and located in the second and third insulating layers 22b, 22c. For example, the material forming the first insulating layer 22a is yttrium oxide (SiO 2 ), tantalum nitride (Si x N y ) or, for example, polybenzoxazole (PBO), polyimine (Polyimide, An organic insulating material such as PI), benzocyclobutane (BCB), Bismaleimide Triazine (BT), and the like, and the second and third insulating layers 22b, 22c are formed. The materials are, for example, polybenzoxazole (PBO), polyimide (PI), benzocyclobutane (BCB), Bismaleimide (Bismaleimide). Organic insulation materials such as Triazine (BT).
又，該絕緣部22係以結合層200結合至該承載件20 上，其中，該承載件20係玻璃板，且該結合層200係為離形膜、黏膠或其它易於分離該絕緣部22與該承載件20之材質。 Moreover, the insulating portion 22 is bonded to the carrier 20 by the bonding layer 200. The carrier 20 is a glass plate, and the bonding layer 200 is a release film, an adhesive or other material that is easy to separate the insulating portion 22 from the carrier 20.
另外，該導電層210之表面係外露於該第三絕緣層22c，使該導電層210接觸該結合層200。具體地，如第2A圖所示，該導電層210之表面係齊平該第三絕緣層22c之表面；或者，亦可於該第三絕緣層22c上形成外露該導電層210之開孔。 In addition, the surface of the conductive layer 210 is exposed to the third insulating layer 22c, so that the conductive layer 210 contacts the bonding layer 200. Specifically, as shown in FIG. 2A, the surface of the conductive layer 210 is flush with the surface of the third insulating layer 22c. Alternatively, the opening of the conductive layer 210 may be formed on the third insulating layer 22c.
如第2B圖所示，形成至少一穿孔220於該基板本體21之第二表面21b上，且該穿孔220連通該第一表面21a並延伸至該絕緣部22之第一絕緣層22a，以令該導電層210外露於該穿孔220。 As shown in FIG. 2B, at least one through hole 220 is formed on the second surface 21b of the substrate body 21, and the through hole 220 communicates with the first surface 21a and extends to the first insulating layer 22a of the insulating portion 22, so that The conductive layer 210 is exposed to the through hole 220.
於本實施例中，該穿孔220之製程係先於該基板本體21之第二表面21b上形成圖案化光阻9，再以蝕刻、機鑽、雷射或其它方式形成該穿孔220，之後移除該圖案化光阻9。 In this embodiment, the process of the via 220 is formed on the second surface 21b of the substrate body 21 to form a patterned photoresist 9, and then the via 220 is formed by etching, machine drilling, laser or other means, and then moved. In addition to the patterned photoresist 9.
如第2C圖所示，形成一鈍化層23於該穿孔220中(如該穿孔之側壁)及該基板本體21之第二表面21b上。 As shown in FIG. 2C, a passivation layer 23 is formed in the via 220 (such as the sidewall of the via) and the second surface 21b of the substrate body 21.
於本實施例中，形成該鈍化層23之材質可為氧化層或氮化層，如氧化矽(SiO2)或氮化矽(SixNy)，且可採用化學氣相沉積法(Chemical Vapor Deposition，簡稱CVD)方式形成該鈍化層23。 In this embodiment, the material of the passivation layer 23 may be an oxide layer or a nitride layer, such as yttrium oxide (SiO 2 ) or tantalum nitride (Si x N y ), and may be chemical vapor deposition (Chemical). The passivation layer 23 is formed by Vapor Deposition (referred to as CVD).
如第2D圖所示，形成一金屬層24於該基板本體21之第二表面21b之鈍化層23上，且形成導電穿孔240於該 穿孔220中，使該金屬層24藉由該導電穿孔240電性連接該導電層210。 As shown in FIG. 2D, a metal layer 24 is formed on the passivation layer 23 of the second surface 21b of the substrate body 21, and a conductive via 240 is formed thereon. In the through hole 220, the metal layer 24 is electrically connected to the conductive layer 210 by the conductive via 240.
於本實施例中，該金屬層24係具有墊部241以作為凸塊底下金屬層(Under Bump Metal，簡稱UBM)。 In the present embodiment, the metal layer 24 has a pad portion 241 as an under bump metal layer (UBM).
再者，可使用雙鑲嵌法一體成型製作該金屬層24(該墊部241與該導電穿孔240)，或者，可藉由濺鍍(sputter)或鍍覆(plating)配合曝光顯影之方式，進行圖案化製程，以形成該金屬層24與該導電穿孔240。然而，該金屬層24與該導電穿孔240之製作方式繁多，並不限於上述者。 Furthermore, the metal layer 24 (the pad portion 241 and the conductive via 240) may be integrally formed by using a dual damascene method, or may be formed by sputtering or plating combined with exposure and development. A patterning process is performed to form the metal layer 24 and the conductive vias 240. However, the metal layer 24 and the conductive via 240 are produced in a wide variety of ways, and are not limited to the above.
又，形成該金屬層24與該導電穿孔240之材質係例如鈦/銅/鎳或鈦/鎳釩/銅。然而，該金屬層24與該導電穿孔240之材質種類繁多，並不限於上述者。 Further, the material of the metal layer 24 and the conductive via 240 is formed, for example, titanium/copper/nickel or titanium/nickel vanadium/copper. However, the metal layer 24 and the conductive via 240 have a wide variety of materials, and are not limited to the above.
如第2E圖所示，形成導電元件25於該金屬層24之墊部241上，使該基板結構2藉由該些導電元件25結合其它電子裝置(圖略)，例如，半導體晶圓、晶片、封裝基板或線路板。 As shown in FIG. 2E, the conductive member 25 is formed on the pad portion 241 of the metal layer 24, so that the substrate structure 2 is combined with other electronic devices (not shown) by the conductive members 25, for example, a semiconductor wafer or a wafer. , package substrate or circuit board.
於本實施例中，該導電元件25係為銲錫凸塊、金屬凸塊或其它塊體等，並無特別限制。 In the embodiment, the conductive element 25 is a solder bump, a metal bump or other block, and the like, and is not particularly limited.
再者，於形成該導電元件25後，可依需求移除該承載件20與該結合層200。 Moreover, after the conductive element 25 is formed, the carrier 20 and the bonding layer 200 can be removed as needed.
本發明之製法中，係藉由該矽基板2a之非線路區的設計，亦即該基板本體21之設置，以強化該基板結構2的結構強度，故相較於習知技術，本發明之基板結構2可避免在生產過程中產生破裂的問題。進一步地，由該基板本體 21與該鈍化層23構成強化構造2b，可使該基板結構2製得更薄，且結構更強。 In the manufacturing method of the present invention, the design of the non-line region of the germanium substrate 2a, that is, the substrate body 21 is provided to strengthen the structural strength of the substrate structure 2, so that the present invention is compared with the prior art. The substrate structure 2 can avoid the problem of cracking during production. Further, the substrate body The passivation layer 23 and the passivation layer 23 constitute a reinforcing structure 2b, and the substrate structure 2 can be made thinner and more structurally strong.
再者，相較於一般厚度為100微米(um)之矽中介板，本發明之基板結構2係為薄型中介板設計，其線路區(該絕緣部22與該導電層210)與非線路區(該基板本體21)之厚度t分別為5至10微米(um)。 Furthermore, the substrate structure 2 of the present invention is a thin interposer design, the line region (the insulating portion 22 and the conductive layer 210) and the non-line region, compared to a general interposer having a thickness of 100 micrometers (um). The thickness t of the substrate body 21 is 5 to 10 micrometers (um), respectively.
又，該非線路區可進行圖案化設計，以達到減輕材質，但仍強化該基板結構2之目的。如第3A圖所示，該基板本體21之第二表面21b上復形成有至少一開口320，且該開口320連通該第一表面21b，以令該絕緣部22之第一絕緣層22a外露於該開口320，再使該鈍化層23沿該開口320之壁面延伸以形成於該開口320中。具體地，該開口320之製作方式可在形成該穿孔220時，依據該圖案化光阻9之設計一併蝕刻該開口320。 Moreover, the non-line area can be patterned to achieve material reduction, but the substrate structure 2 is still strengthened. As shown in FIG. 3A, the second surface 21b of the substrate body 21 is further formed with at least one opening 320, and the opening 320 communicates with the first surface 21b to expose the first insulating layer 22a of the insulating portion 22 to The opening 320 further extends the passivation layer 23 along the wall surface of the opening 320 to be formed in the opening 320. Specifically, the opening 320 can be formed by etching the opening 320 according to the design of the patterned photoresist 9 when the through hole 220 is formed.
於本實施例中，該開口320所形成之圖案可為矩形、六邊形或各種幾何圖形等，使該鈍化層23具有複數連接部230以連接於各該金屬層24之墊部241之間，如第3B圖所示。例如，由於三角形輪廓係為最穩定的應力分布狀態，其於受力時不易變形，故該開口320較佳的圖案係如第3B圖所示之類三角形輪廓(該連接部230或該強化構造2b係構成其邊緣)，以形成穩定的應力結構體，藉此強化該基板結構2之強度，且同時達到結構輕量化之功效。 In this embodiment, the pattern formed by the opening 320 may be a rectangle, a hexagon, or various geometric figures, etc., such that the passivation layer 23 has a plurality of connecting portions 230 for connecting between the pad portions 241 of the metal layers 24. As shown in Figure 3B. For example, since the triangular profile is the most stable stress distribution state, and it is not easily deformed under stress, the preferred pattern of the opening 320 is a triangular profile as shown in FIG. 3B (the connecting portion 230 or the reinforcing structure). 2b constitutes the edge thereof to form a stable stress structure, thereby strengthening the strength of the substrate structure 2 and at the same time achieving the effect of structural weight reduction.
應可理解地，單一墊部241可藉由至少一連接部230連接另一墊部241，並不限於第3B圖所示之態樣。 It should be understood that the single pad portion 241 can be connected to the other pad portion 241 by at least one connecting portion 230, and is not limited to the aspect shown in FIG. 3B.
本發明係提供一種基板結構2，其包括：一矽基板2a、至少一導電穿孔240以及一金屬層24。 The present invention provides a substrate structure 2 comprising: a germanium substrate 2a, at least one conductive via 240, and a metal layer 24.
所述之矽基板2a係包含一具有相對之第一表面21a與第二表面21b的基板本體21、設於該第一表面21a上之絕緣部22及設於該絕緣部22中之導電層210。 The substrate 2a includes a substrate body 21 having a first surface 21a and a second surface 21b opposite thereto, an insulating portion 22 disposed on the first surface 21a, and a conductive layer 210 disposed in the insulating portion 22. .
所述之導電穿孔240係形成於該基板本體21中且連通該第一與第二表面21a,21b並延伸至該導電層210，以令該導電穿孔240電性連接該導電層210。 The conductive vias 240 are formed in the substrate body 21 and communicate with the first and second surfaces 21a, 21b and extend to the conductive layer 210 to electrically connect the conductive vias 240 to the conductive layer 210.
所述之金屬層24係形成於該基板本體21之第二表面21b上以電性連接該導電穿孔240。 The metal layer 24 is formed on the second surface 21b of the substrate body 21 to electrically connect the conductive vias 240.
於一實施例中，該絕緣部22係包含結合於該第一表面21a上之第一絕緣層22a、設於該第一絕緣層22a上之第二絕緣層22b與設於該第二絕緣層22b上之第三絕緣層22c，且該導電層210設於該第一絕緣層22a上而位於該第二與第三絕緣層22b,22c中，其中，該導電層210之表面係外露於該第三絕緣層22c。 In one embodiment, the insulating portion 22 includes a first insulating layer 22a bonded to the first surface 21a, a second insulating layer 22b disposed on the first insulating layer 22a, and a second insulating layer disposed on the second insulating layer. a third insulating layer 22c on the second insulating layer 22a, and the conductive layer 210 is disposed on the first insulating layer 22a and located in the second and third insulating layers 22b, 22c, wherein the surface of the conductive layer 210 is exposed The third insulating layer 22c.
於一實施例中，該基板本體21之第二表面21b上復形成有開口320，且該開口320連通該第一表面21a，以令該絕緣部22之第一絕緣層22a外露於該開口320。 In an embodiment, the second surface 21b of the substrate body 21 is formed with an opening 320, and the opening 320 communicates with the first surface 21a to expose the first insulating layer 22a of the insulating portion 22 to the opening 320. .
於一實施例中，所述之基板結構2復包括一承載件20，係結合於該絕緣部22之第三絕緣層22c上。 In one embodiment, the substrate structure 2 further includes a carrier 20 bonded to the third insulating layer 22c of the insulating portion 22.
於一實施例中，基板結構2復包括導電元件25，係形成於該金屬層24上。 In one embodiment, the substrate structure 2 includes a conductive element 25 formed on the metal layer 24.
綜上所述，本發明之基板結構及其製法，係藉由該基 板本體之設置，以強化該基板結構的結構強度，故能避免該基板結構在生產過程中產生破裂的問題。 In summary, the substrate structure of the present invention and the method of manufacturing the same are based on the base The plate body is arranged to strengthen the structural strength of the substrate structure, so that the problem that the substrate structure is broken during the production process can be avoided.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2‧‧‧基板結構 2‧‧‧Substrate structure
2b‧‧‧強化構造 2b‧‧‧Strengthening structure
20‧‧‧承載件 20‧‧‧Carrier
200‧‧‧結合層 200‧‧‧ bonding layer
21‧‧‧基板本體 21‧‧‧Substrate body
21a‧‧‧第一表面 21a‧‧‧ first surface
21b‧‧‧第二表面 21b‧‧‧ second surface
210‧‧‧導電層 210‧‧‧ Conductive layer
22‧‧‧絕緣部 22‧‧‧Insulation
22a‧‧‧第一絕緣層 22a‧‧‧First insulation
22b‧‧‧第二絕緣層 22b‧‧‧Second insulation
22c‧‧‧第三絕緣層 22c‧‧‧ third insulation
23‧‧‧鈍化層 23‧‧‧ Passivation layer
24‧‧‧金屬層 24‧‧‧metal layer
240‧‧‧導電穿孔 240‧‧‧Electrical perforation
241‧‧‧墊部 241‧‧‧Mats
25‧‧‧導電元件 25‧‧‧Conductive components
t‧‧‧厚度 T‧‧‧thickness
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2017
- 2017-01-13 TW TW106101182A patent/TWI614862B/en active
- 2017-01-24 CN CN201710059612.1A patent/CN108305865B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201406243A (en) * | 2012-05-16 | 2014-02-01 | Ngk Spark Plug Co | Wiring substrate |
| TW201635449A (en) * | 2015-03-17 | 2016-10-01 | 矽品精密工業股份有限公司 | Electronic package and the manufacture thereof and substrate structure |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201826474A (en) | 2018-07-16 |
| CN108305865B (en) | 2020-06-09 |
| CN108305865A (en) | 2018-07-20 |
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