TWI608607B - Multi-gate high electron mobility transistor with aligned internal gate and negative capacitance ferroelectric dielectrics and manufacturing method thereof - Google Patents

Description

Multi-gate high electron mobility with aligned back gate and negative capacitance ferroelectric dielectric Rate field effect transistor and manufacturing method thereof

The present invention relates to a High Electron Mobility Transistor (HEMT), and more particularly to a multi-gate high electron mobility using an aligned back gate and a negative capacitance ferroelectric dielectric. Field effect transistor and its manufacturing method.

In general, since gallium nitride (GaN) high electron mobility field effect transistors (HEMTs) are normally-on components, their power consumption is greater than that of normally-off components.

In order to improve this drawback, today's technology is expected to be designed as an enhanced component. However, a typical gallium nitride high electron mobility field effect transistor usually has only a single metal gate, and its aluminum gallium nitride (AlGaN)/gallium nitride (GaN) hetero interface has a two-dimensional electron channel due to The control capability of a single metal gate is insufficient, and it is difficult to effectively control this heterogeneous interface, resulting in poor stability of its gate voltage.

In addition, the conventional gallium nitride high electron mobility field effect transistor often encounters the problem of poor heat dissipation of the power transistor, which leads to deterioration of reliability and stability.

Therefore, the present invention provides a multi-gate high electron mobility field effect transistor using an aligned back gate and a negative capacitance ferroelectric dielectric, and a method of fabricating the same, thereby solving the above problems encountered in the prior art.

A preferred embodiment of the invention is a multi-gate high electron mobility field effect transistor. In this embodiment, the multi-gate high electron mobility field effect transistor comprises a substrate, a channel layer, a barrier layer, a plurality of gates, a plurality of aligned back gates, and a negative capacitance ferroelectric dielectric. . The channel layer is disposed above the substrate. The barrier layer is disposed above the channel layer. A plurality of gates are respectively disposed above the barrier layer and extend downward into the barrier layer. A plurality of aligned back gates are respectively disposed under the substrate and extending toward the channel layer with respect to the plurality of gates. The negative capacitance ferroelectric dielectric is disposed between the plurality of gates and the barrier layer and between the plurality of aligned back gates and the substrate.

In one embodiment, the substrate comprises a semiconductor substrate.

In one embodiment, the substrate further includes a buffer layer disposed between the semiconductor substrate and the channel layer.

In one embodiment, the substrate further includes a seed layer disposed between the semiconductor substrate and the buffer layer.

In one embodiment, the plurality of aligned back gates extend beyond Pass through the substrate and into the channel layer.

In one embodiment, the multi-gate high electron mobility field effect transistor further includes a drain and a source. The drain and the source are respectively disposed on the barrier layer. The drain and the source are respectively located on opposite sides of the plurality of gates and are separated from each other by the plurality of gates.

In one embodiment, the channel layer comprises gallium nitride (GaN), zinc oxide (ZnO), silicon carbide (SiC), aluminum gallium indium nitride _{(Al x Ga y In 1-} xy N), aluminum gallium indium phosphide (Al _x Ga _y In _1-xy P) or aluminum gallium indium arsenide (Al _x Ga _y In _1-xy As), and 0 ≦ x + y ≦ 1.

In one embodiment, the negative capacitance ferroelectric dielectric is composed of a high dielectric constant (High-K) ferroelectric material having a negative capacitance characteristic, including hafnium niobium oxide (HfSiO), zinc antimony oxide (HfZrO), aluminum. HbAlO, HfYO, HfLaO, HfGdO or HfSrO.

In one embodiment, the negative capacitance ferroelectric dielectric comprises lead zirconate titanate (Pb(ZrTi)O ₃ , PZT), barium titanate (Ba(SrTi)O ₃ , BST) or bismuth ruthenate (Bi) ₂ (SrTa ₂ )O ₉ , SBT).

In one embodiment, the plurality of gates are made of a nitrided or carbonized metal material, including tantalum nitride (TaN), titanium nitride (TiN), titanium carbide (TiC), tantalum carbide (TaC), or nitride. Tungsten (WN).

In one embodiment, the plurality of aligned back gates are made of a metallic material and comprise aluminum (Al) or copper (Cu).

In one embodiment, the negative capacitance ferroelectric dielectric provides a ferroelectric negative capacitance effect, thereby reducing Sub-threshold Swing (SS) and off-state leakage of a multi-gate high electron mobility field effect transistor. Current.

In one embodiment, the plurality of aligned back gates and the plurality of gates are aligned with each other and respectively disposed on opposite sides of the multi-gate high electron mobility field effect transistor, thereby increasing the plurality of gates The heat dissipating area and the bondable area of the high electron mobility field effect transistor.

Another preferred embodiment of the present invention is a method of fabricating a multi-gate high electron mobility field effect transistor. In this embodiment, a multi-gate high electron mobility field effect transistor manufacturing method is used to fabricate a multi-gate high electron mobility field effect transistor.

The multi-gate high electron mobility field effect transistor manufacturing method comprises the following steps: (a) providing a substrate; (b) placing a channel layer over the substrate; (c) placing a barrier layer on the channel Above the layer; (d) forming a plurality of first recessed regions and a plurality of second recessed regions opposite to each other of the barrier layer and the substrate, wherein the plurality of first recessed regions extend into the barrier layer and the plurality of The second recessed region extends toward the channel layer; (e) respectively, a negative capacitance ferroelectric dielectric is disposed in the plurality of first recessed regions and the plurality of second recessed regions; (f) respectively setting a plurality of gates And covering the negative capacitance ferroelectric dielectric in the plurality of first recess regions, such that the plurality of gates extend into the barrier layer; and (g) respectively setting the plurality of aligned back gates In the plural The recessed region covers the negative capacitance ferroelectric dielectric such that the plurality of aligned back gates extend toward the channel layer.

Compared with the prior art, the multi-gate high electron mobility field effect transistor and the manufacturing method thereof according to the present invention can have the following advantages and effects: (1) using a multi-gate structure to strengthen the gate Controlling ability to achieve stable operating voltage and reduce power consumption; (2) Negative capacitance ferroelectric dielectric to provide negative capacitance effect, thereby reducing Sub-threshold Swing (SS) and off-state leakage Current, which in turn increases the drive current and current switching ratio; (3) Aligns the back gate to increase the heat dissipation area of the power transistor, thereby improving its heat dissipation efficiency and reliability, and also reducing wire bonding. The difficulty helps the realization of the three-dimensional integrated circuit; (4) The above structure also contributes to the improvement of the high voltage and high frequency output characteristics of the gallium nitride multi-gate high electron mobility field effect transistor.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

S10~S22‧‧‧Steps

1‧‧‧Multi-gate high electron mobility field effect transistor

10‧‧‧channel layer

12‧‧‧Barrier layer

14‧‧‧Semiconductor substrate

16‧‧‧Negative Capacitance Ferroelectric Dielectric

18‧‧‧ Buffer layer

SUB‧‧‧Substrate

D‧‧‧汲

S‧‧‧ source

G1‧‧‧ gate

G2‧‧‧ Aligned back gate

I _D ‧‧‧汲polar current

V _G ‧‧‧ gate voltage

P/E‧‧‧Standing/Erasing

V _D ‧‧‧汲polar voltage

V _backgate ‧‧‧back gate voltage

g _m ‧‧‧transduction value

1 is a schematic diagram of a multi-gate high electron mobility field effect transistor according to a preferred embodiment of the present invention.

2 is a flow chart showing a method of fabricating a multi-gate high electron mobility field effect transistor in accordance with another preferred embodiment of the present invention.

Figure 3 is a diagram showing that the ferroelectric material can have a subcritical pendulum of less than 60 mv/dec Subthreshold swing to reduce the operating voltage of the transistor component and improve its reliability.

FIG. 4 is a schematic diagram showing the flat-band voltage value of the negative-capacitance ferroelectric dielectric variable-capacitance device equivalent to the threshold voltage value of the modulated transistor component.

Figure 5 is a schematic diagram showing the behavior of a crystalline phase of a material from a metastable monoclinic phase to a more stable orthorhombic phase representing a negative capacitance.

FIG. 6 is a schematic diagram showing that a ferroelectric dielectric having a negative capacitance characteristic can be switched at a high speed between an on state and a off state.

FIG. 7 is a graph showing the peak current variation of a multi-gate high electron mobility field effect transistor having a ferroelectric dielectric and no ferroelectric dielectric at different gate voltages.

FIG. 8 is a graph showing the change of transduction values at different gate voltages of a multi-gate high electron mobility field effect transistor having a ferroelectric dielectric and no ferroelectric dielectric, respectively.

A preferred embodiment of the present invention is a multi-gate high electron mobility field effect transistor (HEMT) having a multi-gate, negative capacitance ferroelectric dielectric and alignment The structural features such as the back gate can not only effectively reduce the sub-threshold swing and gate leakage current, but also improve the heat dissipation effect and high-voltage and high-frequency output characteristics.

In this embodiment, the multi-gate high electron mobility field effect transistor includes at least a substrate, a channel layer, a barrier layer, a plurality of gates, and a plurality of aligned backs. Ferroelectric dielectric to the gate and negative capacitance. Wherein the channel layer is disposed above the substrate. The barrier layer is disposed above the channel layer. A plurality of gates are respectively disposed above the barrier layer and extend downward into the barrier layer. A plurality of aligned back gates are respectively disposed under the substrate and extending toward the channel layer with respect to the plurality of gates. The negative capacitance ferroelectric dielectric is disposed between the plurality of gates and the barrier layer and between the plurality of aligned back gates and the substrate.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a multi-gate high electron mobility field effect transistor according to a preferred embodiment of the present invention.

As shown in FIG. 1, the multi-gate high electron mobility field effect transistor 1 includes a substrate SUB, a channel layer 10, a barrier layer 12, a negative capacitance ferroelectric dielectric 16, a drain D, and a source S. A plurality of gates G1 and a plurality of aligned back gates G2.

It should be noted that the substrate SUB in this embodiment includes the semiconductor substrate 14 and the buffer layer 18, but is not limited thereto. In fact, the substrate SUB may also include only the semiconductor substrate 14 , or the substrate SUB may further include a seed layer disposed between the semiconductor substrate 14 and the buffer layer 18 in addition to the semiconductor substrate 14 and the buffer layer 18 ( The figure is not shown). The buffer layer 18 can be used to reduce the lattice mismatch between the semiconductor substrate 14 (or the seed layer) and the subsequently formed channel layer 10, and to solve the semiconductor substrate due to the difference in thermal expansion coefficient during epitaxial growth. The problem of uniformity of the epitaxial layer on 14; the seed layer can be used to compensate for the lattice misalignment between the semiconductor substrate 14 and the buffer layer 18.

In practical applications, the semiconductor substrate 14 may be made of bismuth (Si), tantalum carbide (SiC), sapphire, gallium nitride (GaN), aluminum gallium nitride (AlGaN), nitride. It is composed of aluminum (AlN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs) or other compounds of group III-V elements, but is not limited thereto. The buffer layer 18 may comprise gallium nitride (GaN) or doped gallium nitride (GaN), which may be produced using an epitaxial process or other suitable method, but is not limited thereto.

It should be noted that the energy gap of the channel layer 10 needs to be smaller than the energy gap of the barrier layer 12, and the combination and thickness of the channel layer 10 and the barrier layer 12 are required to generate two-dimensional electron gas.

In fact, the channel layer 10 may be a compound of a group III-V element or a compound of a doped group III-V element, a compound of a group II-VI element or a compound of a doped group II-VI element or IV- a compound of a group IV element or a compound of a group of doped group IV-IV elements, such as gallium nitride (GaN), zinc oxide (ZnO), tantalum carbide (SiC), aluminum gallium indium nitride (Al _x Ga _y In _1-xy N), aluminum gallium indium phosphide (Al _x Ga _y In _1-xy P) or aluminum gallium indium arsenide (Al _x Ga _y In _1-xy As), and 0 ≦ x + y ≦ 1, But not limited to this. The barrier layer 12 may be composed of a compound of a group III-V element, such as aluminum nitride (AlN), aluminum indium nitride (AlInN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride. (InGaN), aluminum indium gallium nitride (AlInGaN), etc., but not limited thereto.

In a preferred embodiment, the multi-gate high electron mobility field effect transistor 1 can employ a bismuth (Si) substrate as the semiconductor substrate 14, gallium nitride (GaN) as the channel layer 10, and aluminum gallium nitride. (AlGaN) is used as the barrier layer 12, but is not limited thereto.

As for the negative capacitance ferroelectric dielectric 16, it may be a conventional lead zirconate titanate (Pb(ZrTi)O ₃ , PZT), barium titanate (Ba(SrTi)O ₃ , BST) or bismuth ruthenate (Bi _{2 ).} (SrTa ₂ )O ₉ ,SBT), or consisting of high dielectric constant (High-K) ferroelectric materials with negative capacitance characteristics, such as hafnium oxide (HfSiO), zinc antimony oxide (HfZrO), aluminum antimony oxide (HfAlO), HfYO, HfLaO, HfGdO or HfSrO, but not limited thereto.

In addition, the plurality of gates G1 may be composed of a nitrided or carbonized metal material such as tantalum nitride (TaN), titanium nitride (TiN), titanium carbide (TiC), tantalum carbide (TaC) or tungsten nitride (WN). ), etc., but not limited to this. The plurality of aligned back gates G2 may be made of a metal material, such as aluminum (Al) or copper (Cu), but not limited thereto.

In this embodiment, the channel layer 10 is disposed above the semiconductor substrate 14 and the barrier layer 12 is disposed above the channel layer 10. The barrier layer 12 and the semiconductor substrate 14 are respectively formed with a plurality of first recess regions and a plurality of second recess regions facing each other, wherein the plurality of first recess regions extend into the barrier layer 12 and the plurality of The second recessed area will extend toward the channel layer 10. In this embodiment, the plurality of second recessed regions may extend beyond the semiconductor substrate 14 and the buffer layer 18 into the channel layer 10, but are not limited thereto.

The negative capacitance ferroelectric dielectric 16 is disposed in the plurality of first recess regions and the plurality of second recess regions, respectively. The plurality of gates G1 electrically connected to each other fill the plurality of first recessed regions and over the negative capacitance ferroelectric dielectric 16, so that the plurality of gates G1 are extended into the barrier layer 12. The plurality of aligned back gates G2 electrically connected to each other fill the plurality of second recess regions and overlying the negative capacitance ferroelectric dielectric 16, causing the plurality of aligned back gates G2 extends toward the channel layer 10. In this embodiment, due to the plurality of second recessed regions The semiconductor substrate 14 and the buffer layer 18 are extended into the channel layer 10. Therefore, the plurality of aligned back gates G2 also extend beyond the semiconductor substrate 14 and the buffer layer 18 into the channel layer 10, but This is limited to this. Thereby, the plurality of aligned back gates G2 can be aligned with the plurality of gates G1 such that the multi-gate high electron mobility field effect transistor 1 has a double recess gate (Double recess gate) )Structure.

The drain D and the source S are respectively disposed on the barrier layer 12. The drain D and the source S are respectively located on both sides of the plurality of gates G1 and are separated from each other by the plurality of gates G1.

Another preferred embodiment of the present invention is a method of fabricating a multi-gate high electron mobility field effect transistor. In this embodiment, the multi-gate high electron mobility field effect transistor manufacturing method can be used to manufacture the multi-gate high electron mobility field effect transistor 1 as shown in FIG. 1 , but not limited thereto.

Please refer to FIG. 2. FIG. 2 is a flow chart showing a method for fabricating a multi-gate high electron mobility field effect transistor according to another preferred embodiment of the present invention.

As shown in FIG. 2, the method for fabricating a multi-gate high electron mobility field effect transistor includes the following steps: Step S10: providing a substrate SUB including a semiconductor substrate 14 and a buffer layer 18, wherein the buffer layer 18 is located above the semiconductor substrate 14. Step S12: disposing the channel layer 10 over the substrate SUB; step S14: disposing the barrier layer 12 over the channel layer 10; step S16: forming a plurality of layers opposite to each other of the barrier layer 12 and the semiconductor substrate 14 a recessed region and a plurality of second recessed regions, wherein the plurality of first recessed regions extend into the barrier layer 12 and the plurality of second recessed regions pass through The gate layer 10 is extended; step S18: respectively, a negative capacitance ferroelectric dielectric 16 is disposed in the plurality of first recess regions and the plurality of second recess regions; step S20: respectively setting a plurality of gates G1 a plurality of first recessed regions covering the negative capacitance ferroelectric dielectric 16 such that the plurality of gates G1 extend into the barrier layer 12; and step S22: respectively aligning the plurality of aligned back gates G2 is disposed in the plurality of second recessed regions and covers the negative capacitance ferroelectric dielectric 16, such that the plurality of aligned back gates G2 extend toward the channel layer 10.

Thereby, the plurality of aligned back gates G2 can be aligned with the plurality of gates G1 such that the multi-gate high electron mobility field effect transistor 1 has a double recess gate (Double recess gate) )Structure.

In this embodiment, since the plurality of second recessed regions extend beyond the semiconductor substrate 14 and the buffer layer 18 into the channel layer 10, the plurality of alignments respectively filled into the plurality of second recessed regions are respectively filled. The back gate G2 also extends beyond the semiconductor substrate 14 and the buffer layer 18 into the channel layer 10, but is not limited thereto.

It should be noted that although the substrate SUB in this embodiment includes the semiconductor substrate 14 and the buffer layer 18, in other embodiments, the substrate may also include only the semiconductor substrate 14, or the substrate SUB includes the semiconductor substrate 14 and In addition to the buffer layer 18, a seed layer (not shown) disposed between the semiconductor substrate 14 and the buffer layer 18 may be further included.

Multi-gate high electron mobility field obtained according to the above manufacturing method The effect transistor 1 has multi-gate, negative-capacitance ferroelectric dielectric and aligned back gate and other structural features, which not only enhances the gate control ability to stabilize the operating voltage and reduce power consumption, but also reduces sub-criticality. Swing and off-state leakage current to improve the drive current and current switching ratio, which can effectively improve the heat dissipation performance, reliability, high voltage and high frequency output characteristics.

It should be noted that the basic transistor physics phenomenon (minimum sub-threshold swing is 60mV/dec) limits the conventional MOS half-effect transistor, and cannot further reduce its operating voltage and switching energy consumption. Since the steep sub-threshold swing can not only reduce the switching energy consumption, but also reduce the DC off-state leakage current, the next generation of green-energy crystal components must have low operating voltage and high switching speed to effectively save switching. Energy consumption.

Please refer to FIG. 3 , the left side of FIG. 3 is a graph showing the gate current ID of the multi-gate high electron mobility field effect transistor on the gate voltage VG, and the right side of FIG. 3 shows the high gate mobility of the multi-gate. A plot of the sub-threshold swing of the field effect transistor versus the number of write/erase times. It can be seen from FIG. 3 that since the ferroelectric material used for the negative-capacitance ferroelectric dielectric can have a sub-threshold swing of less than 60 mV/dec, the operating voltage of the multi-gate high electron mobility field-effect transistor can be reduced and Improve the specific effectiveness of its reliability.

Please refer to FIG. 4. FIG. 4 is a graph showing gate-substrate capacitance versus gate voltage VG of a multi-gate high electron mobility field effect transistor. It can be seen from Fig. 4 that the negative-capacitance ferroelectric dielectric can change the surface potential of the channel and the flat-band voltage value of the capacitive component, that is, the negative-capacitance ferroelectric dielectric can be changed into multiple gates and high electron mobility field-effect electricity. The critical voltage value of the crystal, so it can improve more under the premise that the threshold voltage is pulled to a positive value. The closing current and sub-threshold swing characteristics of the gate high electron mobility field effect transistor.

Referring to FIG. 5, as shown in FIG. 5, when the crystal phase of the ferroelectric material is converted into a lower energy and more stable rhombic by a higher energy metastable state monoclinic phase. The Orthorhombic phase represents the behavior of a negative capacitance.

Referring to FIG. 6, as shown in FIG. 6, a multi-gate high electron mobility field effect transistor made of a ferroelectric dielectric having a negative capacitance characteristic can quickly perform an on state and a closed state ( The switching between Off state) can achieve a high switching speed of the nanosecond (ns) level, so that the multi-gate high electron mobility field effect transistor of the present invention can be applied to a high frequency component.

Please refer to FIG. 7 and FIG. 8. FIG. 7 is a diagram showing the gate currents of the multi-gate high electron mobility field effect transistor having ferroelectric dielectric and no ferroelectric dielectric at different gate voltages. FIG. 8 is a graph showing transduction values of a multi-gate high electron mobility field effect transistor having a ferroelectric dielectric and no ferroelectric dielectric at different gate voltages, respectively.

It can be seen from FIG. 7 and FIG. 8 that the subcritical swing amplitude and the transduction value (g _m ) of the multi-gate high electron mobility field effect transistor are obvious when the aligned back gate voltage V _backgate is a fixed value. Get improved. Comparing the two curves of ferroelectric dielectric and ferroelectric dielectric in FIGS. 7 and 8 also shows that when the multi-gate high electron mobility field effect transistor is in addition to the aligned back gate When combined with a negative-capacitance ferroelectric dielectric, the component characteristics of a multi-gate high electron mobility field-effect transistor can be significantly improved.

Multi-gate high electron mobility according to the present invention compared to prior art The rate field effect transistor and the manufacturing method thereof can have the following advantages and effects: (1) using a multi-gate structure to strengthen the gate control capability, thereby achieving the effect of stabilizing the operating voltage and reducing power consumption; (2) using a negative capacitance The ferroelectric dielectric provides a negative capacitance effect, thereby reducing the sub-threshold swing and the off-state leakage current, thereby improving the effect of driving current and current switching ratio; (3) using an aligned back gate to increase power consumption. The heat dissipation area of the crystal can improve the heat dissipation performance and reliability, and can also reduce the difficulty of wire bonding, and contribute to the realization of the three-dimensional integrated circuit; (4) the above structure also contributes to the improvement of the gallium nitride multi-gate high High-voltage and high-frequency output characteristics of electron mobility field-effect transistors.

The features and spirits of the present invention are intended to be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.

S10~S22‧‧‧Steps

Claims (26)

A multi-gate high electron mobility field effect transistor comprises: a substrate; a channel layer disposed above the substrate; a barrier layer disposed above the channel layer; and a plurality of gates (Top Gate) And respectively disposed above the barrier layer and extending downward into the barrier layer; a plurality of aligned directional internal gates respectively disposed under the substrate with respect to the plurality of gates And extending to the channel layer; and a negative capacitance ferroelectric dielectric disposed between the plurality of gates and the barrier layer and between the plurality of aligned back gates and the substrate. The multi-gate high electron mobility field effect transistor according to claim 1, wherein the substrate comprises a semiconductor substrate. The multi-gate high electron mobility field effect transistor according to claim 2, wherein the substrate further comprises: a buffer layer disposed between the semiconductor substrate and the channel layer. The multi-gate high electron mobility field effect transistor according to claim 3, wherein the substrate further comprises: a seed layer disposed between the semiconductor substrate and the buffer layer. The multi-gate high electron mobility field effect transistor of claim 1, wherein the plurality of aligned back gates extend beyond the substrate into the channel layer. The multi-gate high electron mobility field effect transistor described in claim 1 further comprises: A drain and a source are respectively disposed on the barrier layer, and the drain and the source are respectively located on opposite sides of the plurality of gates and are separated from each other by the plurality of gates. The multi-gate high electron mobility field effect transistor according to claim 1, wherein the channel layer comprises gallium nitride (GaN), zinc oxide (ZnO), tantalum carbide (SiC), aluminum gallium nitride. Indium (Al _x Ga _y In _1-xy N), aluminum gallium indium phosphide (Al _x Ga _y In _1-xy P) or aluminum gallium indium arsenide (Al _x Ga _y In _1-xy As), and 0≦ x+y≦1. The multi-gate high electron mobility field effect transistor according to claim 1, wherein the negative capacitance ferroelectric dielectric material is a high dielectric constant (High-K) ferroelectric material having a negative capacitance characteristic. The composition comprises HfSiO, HfZrO, HfAlO, HfYO, HfLaO, HfGdO or HfSrO ). The multi-gate high electron mobility field effect transistor according to claim 1, wherein the negative capacitance ferroelectric dielectric comprises lead zirconate titanate (Pb(ZrTi)O ₃ , PZT), barium titanate Barium (Ba(SrTi)O ₃ , BST) or barium strontium bismuth (Bi ₂ (SrTa ₂ )O ₉ , SBT). The multi-gate high electron mobility field effect transistor according to claim 1, wherein the plurality of gates are made of a nitrided or carbonized metal material, including tantalum nitride (TaN), titanium nitride ( TiN), titanium carbide (TiC), tantalum carbide (TaC) or tungsten nitride (WN). The multi-gate high electron mobility field effect transistor according to claim 1, wherein the plurality of aligned back gates are made of a metal material and comprise aluminum (Al) or copper (Cu). The multi-gate high electron mobility field effect transistor according to claim 1, wherein the negative capacitance ferroelectric dielectric provides a ferroelectric negative capacitance effect, thereby reducing Sub-threshold Swing (SS) and off-state leakage current (Ioff) of the multi-gate high electron mobility field effect transistor. The multi-gate high electron mobility field effect transistor according to claim 1, wherein the plurality of aligned back gates and the plurality of gates are aligned with each other and respectively disposed on the plurality of gates The opposite sides of the high electron mobility field effect transistor are used to increase the heat dissipating area and the bondable area of the multi-gate high electron mobility field effect transistor. A multi-gate high electron mobility field effect transistor manufacturing method for fabricating a multi-gate high electron mobility field effect transistor, comprising the steps of: (a) providing a substrate; (b) providing a channel layer Provided above the substrate; (c) disposing a barrier layer over the channel layer; (d) forming a plurality of first recessed regions and a plurality of second portions opposite to each other of the barrier layer and the substrate a recessed region, wherein the plurality of first recessed regions extend into the barrier layer and the plurality of second recessed regions extend toward the via layer; (e) respectively setting a negative capacitance ferroelectric dielectric to the plurality of a first recessed region and the plurality of second recessed regions; (f) respectively arranging a plurality of top gates in the plurality of first recessed regions and covering the negative capacitance ferroelectric dielectric Causing the plurality of gates to extend into the barrier layer; and (g) respectively arranging a plurality of aligned directional internal gates in the plurality of second recess regions and covering the negative capacitance Ferroelectric dielectric, causing the plurality of aligned back gates to be extended to the channel . Multi-gate high electron mobility field effect electro-crystal as described in claim 14 The method of manufacturing a body, wherein the substrate comprises a semiconductor substrate. The method for manufacturing a multi-gate high electron mobility field effect transistor according to claim 15, wherein the substrate further comprises: a buffer layer disposed between the semiconductor substrate and the channel layer. The method for manufacturing a multi-gate high electron mobility field effect transistor according to claim 16, wherein the substrate further comprises: a seed layer disposed between the semiconductor substrate and the buffer layer. The method of fabricating a multi-gate high electron mobility field effect transistor according to claim 14, wherein the plurality of aligned back gates extend beyond the substrate into the channel layer. The method for manufacturing a multi-gate high electron mobility field effect transistor according to claim 14, further comprising: respectively disposing a drain and a source on the barrier layer, thereby causing the drain and the Sources are respectively located on opposite sides of the plurality of gates and are separated from each other by the plurality of gates. The method for manufacturing a multi-gate high electron mobility field effect transistor according to claim 14, wherein the channel layer comprises gallium nitride (GaN), zinc oxide (ZnO), tantalum carbide (SiC), and nitridation. Al ₊ Ga _y In _1-xy N, Al _x Ga _y In _1-xy P or Al _x Ga _y In _1-xy As, and 0≦x+y≦1. The method for manufacturing a multi-gate high electron mobility field effect transistor according to claim 14, wherein the negative capacitance ferroelectric dielectric system has a high dielectric constant (High-K) iron having a negative capacitance characteristic. Electrical material composition, including hafnium oxide (HfSiO), zinc lanthanum oxide (HfZrO), aluminum lanthanum oxide (HfAlO), niobium oxide (HfYO), niobium oxide (HfLaO), niobium oxide (HfGdO) or niobium oxide (HfSrO). The method for manufacturing a multi-gate high electron mobility field effect transistor according to claim 14, wherein the negative capacitance ferroelectric dielectric comprises lead zirconate titanate (Pb(ZrTi)O ₃ , PZT), titanium Barium strontium (Ba(SrTi)O ₃ , BST) or bismuth ruthenate (Bi ₂ (SrTa ₂ )O ₉ , SBT). The method for manufacturing a multi-gate high electron mobility field effect transistor according to claim 14, wherein the plurality of gates are made of a nitrided or carbonized metal material, including tantalum nitride (TaN), and nitrided. Titanium (TiN), titanium carbide (TiC), tantalum carbide (TaC) or tungsten nitride (WN). The method for manufacturing a multi-gate high electron mobility field effect transistor according to claim 14, wherein the plurality of aligned back gates are made of a metal material, including aluminum (Al) or copper (Cu). ). The method for manufacturing a multi-gate high electron mobility field effect transistor according to claim 14, wherein the negative capacitance ferroelectric dielectric provides a ferroelectric negative capacitance effect, thereby reducing the multi-gate high electron mobility. The sub-critical swing of the field effect transistor and the off-state leakage current. The method for manufacturing a multi-gate high electron mobility field effect transistor according to claim 14, wherein the plurality of aligned back gates and the plurality of gates are aligned with each other and are respectively disposed at the plurality of gates The opposite sides of the gate high electron mobility field effect transistor, thereby increasing the heat dissipating area and the bondable area of the multi-gate high electron mobility field effect transistor.