TWI607595B - Electronic device package - Google Patents

Description

Electronic component package

The present invention relates to a package, and more particularly to an electronic component package.

As electronic components in electronic products are becoming more sophisticated, some electronic components are more sensitive to moisture. Taking an organic thin film transistor array as an example, the infiltration of moisture can easily cause the aging of the organic thin film transistor to fail to operate normally. Generally, an organic thin film transistor array is composed of a plurality of film layers stacked in sequence. A portion of these layers may extend continuously from the center of the array to the edges. Water vapor and oxygen may penetrate into the interior through the side of the film that extends to the edge, thereby accelerating the aging of the organic thin film transistor, which will result in a shortened life of the electronic product, which may not meet the market demand.

The present invention provides an electronic component package which can reduce the probability that an electronic component will be damaged by moisture from a side surface.

An electronic component package provided by the present invention includes a carrier board, an electronic component, a first insulating layer and a barrier layer. The carrier plate includes a central zone, an inner edge zone and an outer edge zone, wherein the inner edge zone is located between the central zone and the outer edge zone. The electronic component is disposed on the carrier board and located in the central area. The first insulating layer is disposed on the carrier board and overlaps the electronic component, and the first insulating layer extends from the central region to the inner edge region. The barrier layer is disposed on the carrier plate, and the barrier layer is exposed to the central region, wherein the barrier layer includes a sidewall contact portion and an extension portion. The sidewall contact surrounds a side surface of the first insulating layer, and the extension extends from the sidewall contact to the outer edge region in a direction away from the first insulating layer.

In an embodiment of the invention, the barrier layer further includes a cover portion that extends from the sidewall contact portion in a direction away from the extension portion over the first insulation layer, and the cover portion exposes the central region.

In an embodiment of the invention, the electronic component includes an organic thin film transistor, wherein the organic thin film transistor includes a gate, a source, a drain, and an organic semiconductor channel layer. The area of the gate overlaps the area of the organic semiconductor channel layer. The first insulating layer is between the gate and the organic semiconductor channel layer. The source and the drain are connected to the organic semiconductor channel layer.

In an embodiment of the invention, the sidewall contact portion covers a side surface of the first insulating layer.

In an embodiment of the invention, the electronic component package further includes a second insulating layer disposed between the second insulating layer and the carrier.

In an embodiment of the invention, the second insulating layer has an area exceeding a side surface of the first insulating layer and has a sidewall portion, and the sidewall portion is located between the side surface of the first insulating layer and the sidewall contact portion.

In an embodiment of the invention, the electronic component package further includes a sidewall blocking structure disposed in the inner edge region and extending through the first insulating layer to form a barrier wall.

In an embodiment of the invention, the sidewall blocking structure includes a plurality of sub-barrier structures stacked in a direction perpendicular to the carrier. The material of the sub-blocking structure includes metal.

In an embodiment of the invention, the extension of the barrier layer has an uneven surface on an upper side away from the carrier. The uneven surface is a zigzag shape, a micro cup shape, a step shape or a combination of at least one of the above.

In an embodiment of the invention, the material of the barrier layer is tantalum nitride (SiNx), yttrium oxide (SiOx) or a multilayer tantalum nitride/yttria (SiNx/SiOx) film.

In an embodiment of the invention, the electronic component package further includes an organic buffer layer, a bottom barrier layer, a display dielectric layer, and a protective layer. The organic buffer layer is disposed between the electronic component and the carrier board. The bottom barrier layer is disposed between the organic buffer layer and the carrier plate. The display medium layer is disposed on the electronic component, wherein the display medium layer is electrically connected to the electronic component and used to display an image. The protective layer is disposed on the display medium layer.

In an embodiment of the invention, the extension of the barrier layer contacts the bottom barrier layer.

In an embodiment of the invention, the sidewall contact portion of the barrier layer covers a side surface of the organic buffer layer.

Another electronic component package provided by the present invention includes a carrier board, an electronic component, a plurality of insulating layers, and a sidewall blocking structure. The carrier board includes a central area and an edge area. The electronic component is disposed on the carrier board and located in the central area. A plurality of insulating layers are disposed on the carrier board and overlapped with the electronic component, wherein the plurality of insulating layers extend from the central region to the edge regions, respectively. The sidewall blocking structure is disposed in the edge region, wherein the sidewall blocking structure penetrates the plurality of insulating layers and constitutes a barrier wall shape.

In an embodiment of the invention, the sidewall blocking structure comprises a plurality of sub-barrier structures stacked in a direction of a vertical carrier.

In an embodiment of the invention, one of the plurality of sub-blocking structures is electrically connected to the electronic component. The material of each sub-blocking structure includes metal.

In an embodiment of the invention, the sidewall blocking structure is electrically floating.

In an embodiment of the invention, the electronic component includes an organic thin film transistor. The plurality of insulating layers include a first insulating layer and a second insulating layer. The organic thin film transistor includes a gate, a source, a drain, and an organic semiconductor channel layer. The area of the gate overlaps the area of the organic semiconductor channel layer. The first insulating layer is between the gate and the organic semiconductor channel layer. The source and the drain are connected to the organic semiconductor channel layer, and the first insulating layer is disposed between the second insulating layer and the carrier.

In an embodiment of the invention, the electronic component package further includes an organic buffer layer, a bottom barrier layer, a display dielectric layer, and a protective layer. The organic buffer layer is disposed between the electronic component and the carrier board. The bottom barrier layer is disposed between the organic buffer layer and the carrier plate. The display medium layer is disposed on the electronic component, wherein the display medium layer is electrically connected to the electronic component and used to display an image. The protective layer is disposed on the display medium layer.

Based on the above, in the electronic component package of the present invention, the barrier structure has a certain height on a plane perpendicular to the carrier plate, and a general structure of the barrier wall can be formed around the electronic component package. As a result, the probability that the electronic component in the electronic component package is damaged by the moisture from the side can be reduced.

The above described features and advantages of the invention will be apparent from the following description.

1 is a schematic cross-sectional view showing an electronic component package of the first embodiment of the present invention. Referring to FIG. 1 , the electronic component package 10 a includes a carrier board 100 , an electronic component 110 , a first insulating layer 122 , and a barrier layer 130 . The carrier board 100 includes a center area AA and an edge area around the center area AA. The edge region can be divided into an inner edge region IB and an outer edge region OB. The inner edge region IB is located between the central area AA and the outer edge area OB. In this embodiment, the carrier board 100 can be a rigid substrate, such as a glass substrate or other substrate having good mechanical strength, but is not limited thereto. The carrier board 100 is used to provide suitable support for the electronic component package 10a.

The electronic component 110 is disposed on the carrier board 100 and located in the central area AA of the carrier board 100. The first insulating layer 122 is disposed on the carrier board 100 and overlaps the electronic component 110, and the first insulating layer 122 extends from the central area AA of the carrier board 100 to the inner edge area IB. The barrier layer 130 is disposed on the carrier 100, and the barrier layer 130 includes a sidewall contact portion 132 and an extension portion 134. The sidewall contact portion 132 surrounds one side surface S1 of the first insulating layer 122, and the extension portion 134 extends from the sidewall contact portion 132 in a direction away from the first insulating layer 122 to the outer edge region OB.

In addition, the electronic component package 10a may further include one or more traces M1 on the carrier board 100, wherein the trace M1 may be disposed in the inner edge region IB and electrically connected to the electronic component 110 as The electrical transmission path of the electronic component 110 and the driving circuit is provided, but the invention is not limited thereto. Specifically, in the trace M1 In the case of electrical connection to the electronic component 110, the trace M1 can be used to transmit a signal. However, in the case where the trace M1 is not electrically connected to the electronic component 110, the trace M1 can function as an electrostatic protection circuit or provide an electrical shield. In addition, in other embodiments, the routing M1 may be selectively omitted in the inner edge region IB of the electronic component package 10a, and the invention is not limited thereto.

For the sake of clarity, "outside" in this specification means the side of the carrier sheet 100 in which the central area AA faces the outer edge area OB. Conversely, "inside" refers to the side of the carrier sheet 100 in which the outer edge region OB faces the center region AA.

Referring to Fig. 1, in order to facilitate the electronic component package 10a, it can be stably supported during the manufacturing process and can be provided with flexibility after fabrication. In this embodiment, the carrier board 100 of the electronic component package 10a may include a flexible substrate 102A and a support substrate 102B. The flexible substrate 102A is disposed between the electronic component 110 and the support substrate 102B. Specifically, the material of the flexible substrate 102A may be, for example, polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyacrylate (PA), poly. Polynorbornene (PNB), polyethylene terephthalate (PET), polyetheretherketone (PEEK), polyethylene naphthalate (PEN) or poly A flexible material such as polyetherimide (PEI). After the electronic component package 10a is completed, the flexible substrate 102A and the support substrate 102B can be selectively separated. At this time, the carrier board 100 may be constituted only by the flexible substrate 102A.

In order to enhance the water vapor barrier property of the flexible substrate 102A. In this embodiment, the electronic component package 10a further includes a bottom barrier layer 104 disposed between the electronic component 110 and the flexible substrate 102A and between the first insulating layer 122 and the flexible substrate 102A. The bottom barrier layer 104 may be a single layer film or a laminate composed of a plurality of layers. This embodiment does not limit the number of layers and the constituent materials of the bottom barrier layer 104. In the above, when the bottom barrier layer 104 is a laminate composed of a plurality of films, the bottom barrier layer 104 is, for example, a laminate in which an organic film and an inorganic film are alternately stacked, or the bottom barrier layer 104 may be a plurality of layers. A laminate of inorganic thin film stacks. When the bottom barrier layer 104 is a laminate composed of a plurality of layers of inorganic thin films, the bottom barrier layer 104 may be a stack of alternating stacks of tantalum nitride and tantalum oxide. The vapor barrier transmission rate (VWTR) of the bottom barrier layer 104 is not higher than 10 ^-2 g/m ² ‧ days, preferably not higher than 10 ^-6 g/m ² ‧ days

In order to release the stress between the electronic component 110 and the bottom barrier layer 104 and improve the adhesion of the electronic component 110, the embodiment may selectively provide an organic buffer layer 106 between the electronic component 110 and the bottom barrier layer 104 to enhance the electrons. The reliability of component 110. In the present embodiment, the organic buffer layer 106 is disposed between the electronic component 110 and the carrier board 100 and the bottom barrier layer 104 is located between the organic buffer layer 106 and the carrier board 100.

The electronic component 110 may include a Thin Film Transistor (TFT). In detail, the thin film transistor may include an amorphous germanium thin film transistor (a-Si TFT), a microcrystalline silicon transistor (micro-Si TFT), a polycrystalline germanium thin film transistor (p-Si TFT), or an organic thin film transistor. (OTFT) and other transistors. In the present embodiment, the electronic component 110 includes an organic thin film transistor 112, but not limited thereto. In other embodiments, the electronic component 110 may further include a capacitor structure, a diode or other components. The organic thin film transistor 112 is composed of a plurality of patterned films and these films can be formed by inkjet (jet-jet), spin coating, flexographic printing, deposition, etc. by lithography. The etching method is patterned into a desired pattern. Specifically, the organic thin film transistor 112 includes a gate G, a source S, a drain D, and an organic semiconductor channel layer CH. The area of the gate G overlaps the area of the organic semiconductor channel layer CH. The first insulating layer 122 is located between the gate G and the organic semiconductor channel layer CH. The source S and the drain D are connected to the organic semiconductor channel layer CH. In operation, the gate G can control the opening (turning on) and closing (opening) of the organic thin film transistor 112. When the organic thin film transistor 112 is turned on (on), the organic thin film transistor 112 can allow the source S to be electrically conducted to the drain D through the organic semiconductor channel layer CH.

In this embodiment, the electronic component package 10a further includes a second insulating layer 124. The first insulating layer 122 is disposed between the second insulating layer 124 and the carrier 100. In addition, in the embodiment, the electronic component package 10a may further include a conductive layer M2 disposed on the second insulating layer 124, and the conductive layer M2 may be electrically connected to the drain D. When the electronic component 110 is turned on, the electronic component 110 is electrically connected to other components through the conductive layer M2. In the present embodiment, the electronic component package 10a is actually constituted by a plurality of film layers stacked on the carrier board 100. First, the bottom barrier layer 104 and the organic buffer layer 106 are sequentially disposed on the carrier 100. At this time, the source S and the drain D of the organic thin film transistor 112 may be the same as the trace M1 as the first conductive layer, and may be simultaneously formed on the organic buffer layer 106. In other words, the source S, the drain D, and the trace M1 can be incorporated into the same process. Next, the organic semiconductor channel layer CH, the first insulating layer 122, the gate G, the second insulating layer 124, and the trace M2 may be sequentially formed. Before the gate G and the trace M2 are formed, the first insulating layer 122 and the second insulating layer 124 may be appropriately patterned to form an opening on the drain D. In this way, the trace M2 can be electrically connected to the drain D through the opening.

In other embodiments, the electronic component package 10a may further include other insulating layers, and the present invention does not limit the number of insulating layers. For example, the electronic component package 10a may further include a third insulating layer, a fourth insulating layer, and the like. In addition, the first insulating layer 122 and the second insulating layer 124 may be an organic insulating material such as parylene, hexamethyl decane (HMDSO) or other organic materials having insulating properties. The above-mentioned organic insulating material has a water vapor permeability of about 10 ^-2 g/m ² ‧Day. However, in the process, whether the first insulating layer 122 and the second insulating layer 124 are formed by chemical vapor deposition, physical vapor deposition, or film formation by wet film heating, the first insulating layer 122 or the second insulation Defects in layer 124 inevitably coalesce to create pin-hloes. As shown in FIG. 1 , if the side surface S1 of the first insulating layer 122 and the side surface S2 of the second insulating layer 124 are exposed, the moisture may be from the side surface S1 of the first insulating layer 122 and the second insulating layer 124. The side surface S2 enters, further contacting the electronic component 110 by rapid diffusion of pinholes in the first insulating layer 122 or the second insulating layer 124, which may cause damage to the electronic component 110.

In the present embodiment, the exposure of one side surface S3 of the organic buffer layer 106 may also cause moisture to enter from the side surface S3 to damage the electronic component 110. Therefore, the sidewall contact portion 132 of the barrier layer 130 surrounds and covers the above-described side surface S1, the side surface S2, and the side surface S3, and the extension portion 134 of the barrier layer 130 is extended by the sidewall contact portion 132 in a direction away from the first insulating layer 122. To the outer edge layer OB, and contact the bottom barrier layer 104. At this time, the side wall contact portion 132 and the extension portion 134 have an L-shaped structure and the outer edge region OB of the carrier plate 100 is disposed. The material of the barrier layer 130 may be selected from inorganic materials such as tantalum nitride (SiNx), yttrium oxide (SiOx), and the like. In addition, the barrier layer 130 may alternatively be formed by stacking a plurality of layers of tantalum nitride/yttria (SiNx/SiOx) films. The water vapor permeability of the above materials is less than 10 ^-4 g/m ² ‧Day. The smaller the water vapor permeability of the barrier layer 130, the more the moisture can be prevented from entering the barrier layer 130 from the outside of the electronic component package 10a, thereby ensuring that the electronic component 110 is not affected by moisture. However, the material of the barrier layer 130 in the present invention is not limited thereto, and the material can be adjusted according to the required water vapor permeability.

In addition, in the present embodiment, the sidewall contact portion 132 of the barrier layer 130 covers the side surface S3 of the organic buffer layer 106 and the side surface S1 of the first insulating layer 122, and the sidewall contact portion 132 contacts the side surface S1, the side surface S2, and An interface 140 is formed at the side surface S3. The interface 140 helps to block the diffusion of moisture from the sidewall contact portion 132 to the inner first insulating layer 122, the second insulating layer 124, and the organic buffer layer 106 to contact the electronic component 110, thereby ensuring the quality of the electronic component 110. In detail, the interface 140 may make the pin-hloes in the first insulating layer 122, the second insulating layer 124, and the organic buffer layer 106 not continuous with the pinholes in the sidewall contact portion 132. As a result, the moisture cannot be quickly diffused from the outside of the electronic component package 10a into the inner side by the pinhole to affect the electronic component 110, so that the electronic component 110 can be protected from moisture.

In this embodiment, the barrier layer 130 further includes a cover portion 136. The cover portion 136 extends from the sidewall contact portion 132 in a direction away from the extension portion 134 to cover the first insulation layer 122, and the cover portion 136 exposes the central region AA. . In other words, in the present embodiment, the cover portion 136 of the barrier layer 130 is not disposed on the central area AA, or the barrier layer 130 does not extend to the central area AA or does not completely cover the central area AA. In general, inorganic materials have more brittle characteristics than organic materials. Therefore, the barrier layer 130 is harder than the first insulating layer 122 and the second insulating layer 124. In the electronic component package 10a, when the electronic component package 10a performs the ball drop test, if the barrier layer 130 is filled with the central area AA, it is relatively easy to be broken, which affects other components, and even causes the electronic component package 10a to be abnormal. Operation. Therefore, the barrier layer 130 of the present embodiment is exposed to the central area AA, and the probability of the barrier layer 130 being broken can be reduced, so that the ability of the electronic component package 10a to withstand an external force can be ensured.

In this embodiment, the electronic component package 10a may further include a display medium layer EPL and a protective layer PV. The display medium layer EPL is coated between the protective layer PV and the carrier plate 100. The display medium layer EPL is disposed on the electronic component 110, wherein the display medium layer EPL and the electronic component 110 are electrically connected by the conductive layer M2 and used to display an image. The display medium in the display medium layer EPL may be a display medium composed of a liquid crystal, a dielectric solvent and a plurality of charged particles doped in a dielectric solvent, or other suitable display medium, and the present invention does not Define the type and material of the display media layer. In other words, the electronic component package 10a can be used to display a screen as a display, but in another embodiment, the electronic component 110 may not be provided with a display medium layer EPL but may be provided with an inductive material (for example, converting light energy into electrical energy) The photoelectric conversion material) is used to make the electronic component package 10a function as a sensor.

2 is a cross-sectional view showing an electronic component package in accordance with a second embodiment of the present invention. Referring to FIG. 2, the electronic component package 10b includes the carrier board 100, the bottom barrier layer 104, the organic buffer layer 106, the electronic component 110, the first insulating layer 122, the second insulating layer 124, the barrier layer 130, and the display of FIG. The dielectric layer EPL, a protective layer PV, a conductive layer M2, and a trace M1. The electronic component package 10b is similar to the embodiment of FIG. 1. The characteristics of the above-mentioned component members and the connection relationship between the component members can be referred to the related description of the electronic component package 10a, and details are not described herein again. In the present embodiment, the electronic component package 10b is different from the electronic component package 10a in that the second insulating layer 124 has a side wall portion 126 beyond the side surface S1 of the first insulating layer 122. The sidewall portion 126 is located between the side surface S1 of the first insulating layer 122 and the sidewall contact portion 132, and the second insulating layer 124 may cover the first insulating layer 122. Further, the side wall contact portion 132 surrounds the side surface S1, the side wall portion 126 away from the side surface S2 of the side surface S1, and the side surface S3 of the organic buffer layer 106, and covers the above-described side surface S2 and side surface S3.

In the present embodiment, the sidewall portion 126 can increase the number of layers of the electronic component package 10b stacked from the inside toward the outside, and an interface is formed between the two layers stacked on each other. Specifically, the film layers stacked on the sidewalls of the electronic component package 10b from the inside to the outside are sequentially the first insulating layer 122, the sidewall portion 126 of the second insulating layer 124, and the sidewall contact portion 132. The side surface S2 of the side wall portion 126 and the side surface S3 of the organic buffer layer 106 and the side wall contact portion 132 form an interface 142. In addition, the side wall portion 126 and the side surface S1 of the first insulating layer 122 form another interface 144. In this way, similar to the interface 140 in FIG. 1 , the above two interfaces 142 and 144 help to block the rapid diffusion of moisture from the outside of the electronic component package 10 b into the inner side to prevent the electronic component 110 from being affected by moisture. The quality of the electronic component 110 can be ensured.

It should be noted that the present invention does not limit the number of insulation layer stacks, and the number thereof can be adjusted as needed. In another embodiment, the area of the organic buffer layer 106 of the electronic component package 10b may be smaller than the second insulating layer 124 such that the sidewall portion 126 covers the side surface S3 of the organic buffer layer 106. In addition, the electronic component package 10b may further include a third insulating layer (not shown) having a larger area than the side surface S2 of the second insulating layer 124 and another sidewall portion. The film layers stacked from the inside to the outside on the side walls of the electronic component package 10b are sequentially the first insulating layer 122, the second insulating layer 124, the third insulating layer and the sidewall contact portion 132, and a total of three different interfaces are formed. In this way, the three different interfaces can effectively block the moisture from diffusing from the outside to the inside of the electronic component package 10b, thereby ensuring the quality of the electronic component 110.

3 is a cross-sectional view showing an electronic component package in accordance with a third embodiment of the present invention. Fig. 4 is a top plan view showing the electronic component package 10c of the embodiment of Fig. 3. Referring first to FIG. 3, the electronic component package 10c includes the carrier board 100, the bottom barrier layer 104, the organic buffer layer 106, the electronic component 110, the first insulating layer 122, the second insulating layer 124, and the barrier layer 130 in FIG. A dielectric layer EPL, a protective layer PV, a conductive layer M2, and a trace M1 are displayed. In the electronic component package 10c, similar to FIG. 2, the characteristics of the above-described constituent members and the connection relationship between the constituent members can be referred to the related descriptions of the electronic component package 10a and the electronic component package 10b, and details are not described herein again.

In this embodiment, the electronic component package 10c is different from the electronic component package 10b. The electronic component package 10c further includes one or more sidewall blocking structures 150a disposed in the inner edge region IB and extending through the first insulation. The layer 122 and the second insulating layer 124 form a wall shape. The sidewall blocking structure 150a is disposed on the organic buffer layer 106 and covered by the covering portion 136 of the barrier layer 130. Specifically, the sidewall blocking structure 150a may include a plurality of traces M1, a plurality of sub-barrier structures 152a, and a plurality of sub-barrier structures 152b, wherein one of the sub-blocking structures 152a and one of the sub-barrier structures 152b are sequentially oriented in the vertical carrier board 100. One of the side wall blocking structures 150a is formed by being stacked on one of the traces M1. That is to say, the trace M1 can also substantially serve as one of the sub-block structures constituting the sidewall blocking structure 150a.

In this embodiment, the trace M1 of at least one of the plurality of sidewall blocking structures 150a can be electrically connected to the electronic component 110. In other words, the sidewall blocking structure 150a can be used to transmit signals of the electronic component 110. In another embodiment, the traces M1 of the plurality of sidewall blocking structures 150a may not electrically connect the electronic components 110. As such, the sidewall blocking structure 150a may be in an electrically floating state or may be a structure for electrostatic protection.

Referring to FIG. 3 and FIG. 4 simultaneously, it can be seen from FIG. 3 and FIG. 4 that the sidewall stack structure 150a of the multilayer stack is substantially in the shape of a sheet and surrounds the electronic component 110 at the periphery of the electronic component package 10c. In other words, the sidewall blocking structure 150a can cause the electronic component package 10c to have a plurality of wall-like structures perpendicular to the plane of the carrier board 100, which can block the diffusion of moisture from the outside of the electronic component package 10c to the central area AA and affect the electrons. The operation of component 110. In more detail, the plurality of barrier-like sidewall blocking structures 150a may have the electronic component package 10c having a plurality of interfaces perpendicular to the plane of the carrier 100 from the inside to the outside. As such, similar to the interface 140 of FIG. 1, the plurality of interfaces prevent moisture from diffusing from the outside into the inside through the pinholes in the film. In addition, although three sidewall blocking structures 150a are illustrated in FIG. 3, the number of sidewall blocking structures 150a is not limited thereto. For example, the electronic component package 10c may include 1, 2, 4, etc. sidewall blocking structures 150a. Further, in some embodiments, since the sidewall blocking structure 150a is provided to block moisture, the electronic component package provided with the sidewall blocking structure 150a may optionally not be provided with the barrier layer 130, or the barrier layer 130 may be Optionally there are no sidewall contacts 132 and extensions 134.

Fig. 5 is a cross-sectional view showing an electronic component package in accordance with a fourth embodiment of the present invention. Referring to FIG. 5 , similar to FIG. 4 , in the embodiment, the electronic component package 10 d includes the carrier 100 of the electronic component package 10 c , the bottom barrier layer 104 , the organic buffer layer 106 , the electronic component 110 , and the first insulating layer 122 . a second insulating layer 124, a barrier layer 130, a display dielectric layer EPL, a protective layer PV, a conductive layer M2, and a trace M1. In the electronic component package 10d, similar to FIG. 3, the characteristics of the above-described constituent members and the connection relationship between the constituent members can be referred to the related description of the electronic component package 10c, and details are not described herein again.

In this embodiment, similar to FIG. 3, the electronic component package 10d further includes a sidewall blocking structure 150b disposed in the inner edge region IB and extending through the first insulating layer 122 and the second insulating layer 124 to form a wall shape. . The sidewall blocking structure 150 is disposed on the organic buffer layer 106 and covered by the covering portion 136 of the barrier layer 130. In the embodiment of FIG. 5, the sidewall blocking structure 150b includes a sub-barrier structure 152a, a sub-barrier structure 152b, and a sub-barrier structure 152c, wherein the sub-barrier structure 152a and the sub-blocking structure 152b are sequentially stacked in the direction of the vertical carrier plate 100. Sub-blocking structure 152c. The sub-barrier structure 152a may be composed of the same film layer as the trace M1.

However, unlike the embodiment of FIG. 3, in the present embodiment, the sidewall blocking structure 150b of the multilayer structure is disposed independently of the trace M1 of the single-layer structure, such that the sidewall blocking structure 150b of the multilayer structure is located on the single-layer trace M1. Outside. However, similar to the sidewall blocking structure 150a of FIG. 3, the sidewall blocking structure 150b allows the electronic component package 10d to have a plurality of interfaces perpendicular to the plane of the carrier board 100 from the outside to the inside, so that the sidewall blocking structure 150b can block moisture from the electrons. The diffusion of the component package 10d, in turn, affects the operation of the electronic component 110. In addition, in the present embodiment, the sidewall blocking structure 150b is also similar to the sidewall blocking structure 150a, which may be electrically connected to the electronic component 110 or electrically floating or as a member of electrostatic protection. In addition, although the sidewall blocking structure 150b is disposed on the outer side of the trace M1 in this embodiment, the invention is not limited thereto. For example, the sidewall blocking structure 150b may also be disposed on a side closer to the electronic component 110 than the trace M1. Further, in some embodiments, since the sidewall blocking structure 150b has the function of blocking moisture, the electronic component package provided with the sidewall blocking structure 150b may optionally not need to be provided with the barrier layer 130, or the barrier layer 130 may be Optionally there are no sidewall contacts 132 and extensions 134.

In the embodiment of FIGS. 3 and 5, the electronic component package 10c and the electronic component package 10d are substantially constituted by a plurality of film layers stacked on the carrier 100. First, the source S, the drain D, the trace M1, and the sub-block structure 152c may be the same first conductive layer, and may be simultaneously formed on the organic buffer layer 106. Next, the organic semiconductor channel layer CH and the first insulating layer 122 are sequentially formed. At this time, the gate G and the sub-barrier structure 152a may be the same second conductive layer, and the first insulating layer 122 may be simultaneously formed and the sub-barrier structure 152a penetrates the first insulating layer 122 to contact the trace M1/sub-barrier structure 152c. Next, a second insulating layer 124 is formed on the first insulating layer 122. The conductive layer M2 and the sub-barrier structure 152b may be the same third conductive layer, which may be simultaneously formed on the second insulating layer 124 and the sub-blocking structure 152b penetrates the second insulating layer 124 to contact the sub-blocking structure 152a. In other words, in the embodiment of FIGS. 3 and 5, the fabrication of the sidewall blocking structure 150a and the sidewall blocking structure 150b can be integrated into the original process, so that no additional process is added to increase the cost.

In this embodiment, the material of the first conductive layer, the second conductive layer, and the third conductive layer may be a metal, a metal alloy, a conductive oxide, an organic conductive material, or a combination thereof, and the first conductive layer, Each of the two conductive layers and the third conductive layer may be a laminate of a plurality of layers of conductive material. In general, metal materials have a lower water vapor transmission rate than organic materials. If the material of the sidewall blocking structure 150a and the sidewall blocking structure 150b includes metal, the moisture can be further prevented from entering from the outside, and the sealing effect of preventing the moisture from damaging the electronic component 110 is enhanced. However, the above materials are for illustrative purposes only and are not intended to limit the invention.

6 is an enlarged view of a partial component of an electronic component package according to a fifth embodiment of the present invention, wherein FIG. 6 only shows a carrier board, a bottom barrier layer, a first insulating layer, a display dielectric layer, a protective layer, and the electronic component package; Barrier layer. Referring to FIG. 6, the electronic component package 10e includes a carrier board 100, a bottom barrier layer 104, an insulating layer IN, a display dielectric layer EPL, a barrier layer 130a, a package board CG, and a sealant SE, wherein the barrier layer 130a includes a sidewall contact portion 132a. And an extension 134a. For the characteristics and arrangement relationship of the respective components in the electronic component package 10e, reference may be made to any of the above embodiments, and details are not described herein again. The insulating layer IN may include the first insulating layer 122, the second insulating layer 124, or a combination thereof as described in the foregoing embodiments. Although the electronic component is not shown in FIG. 6, the arrangement relationship between the electronic component, the insulating layer IN, and the barrier layer 130a can be understood by referring to the foregoing embodiment.

In the present embodiment, the barrier layer 130a is different from the barrier layer 130 in that the barrier layer 130a does not cover the insulating layer IN, and the extension portion 134a is composed of a plurality of bumps PT and is away from the carrier plate 100 at the barrier layer 130a. One side constitutes a concave-convex surface 138a in which the projections PT are spaced apart from each other and the uneven surface 138a is serrated. Specifically, after the barrier layer 130a is formed, the extending portion 134a of the barrier layer 130a may be further patterned, and the extending portion 134a may be patterned into the bump PT to form a zigzag uneven surface 138a. Next, the display medium layer EPL is packaged between the carrier board 100 and the package board CG. In an embodiment, the carrier sheet 100 and the package board CG may be assembled by using the sealant SE around the display medium layer EPL. The interface formed by the concave-convex surface 138a and the sealant SE can effectively block the moisture from diffusing from the outside of the sealant SE into the first insulating layer 122 in the insulating layer IN and contacting the electronic component 110 (not shown, refer to the figure 1~3 and FIG. 5), in addition, can maintain the normal operation of the electronic component 110 (not shown, can refer to FIGS. 1-3 and FIG. 5).

7 is an enlarged view of a partial member of an electronic component package according to a sixth embodiment of the present invention, wherein FIG. 7 only shows a carrier board, a bottom barrier layer, a first insulating layer, a display dielectric layer, a protective layer, and the electronic component package; Barrier layer. Referring to FIG. 7, the electronic component package 10f includes a carrier board 100, a bottom barrier layer 104, an insulating layer IN, a display dielectric layer EPL, a barrier layer 130b, a package board CG, and a sealant SE. The barrier layer 130b includes a sidewall contact portion 132b. And an extension 134b. For the characteristics and arrangement relationship of the respective components in the electronic component package 10f, reference may be made to the related description of the embodiment of FIG. 6, and details are not described herein again. In the present embodiment, similar to the electronic component package 10e of FIG. 6, the extending portion 134b of the barrier layer 130b forms a concave-convex surface 138b on an upper side of the barrier layer 130b away from the carrier sheet 100. The extending portion 134b in this embodiment continuously extends outward, and the formed uneven surface 138b is in the shape of a microcup. That is, the uneven surface 138b is constituted by a plurality of thicker sections and a plurality of thinner sections and the thicker sections and the thinner sections are alternately distributed in the extending portion 134b. In addition, the display medium layer EPL is packaged between the carrier board 100 and the package board CG. In an embodiment, the carrier sheet 100 and the package board CG may be assembled by using the sealant SE around the display medium layer EPL. The interface formed by the concave-convex surface 138b and the sealant SE can effectively block the moisture from diffusing from the outside of the sealant SE into the first insulating layer 122 in the insulating layer IN and contacting the electronic component 110 (not shown, refer to the figure 1~3 and FIG. 5), in addition, can maintain the normal operation of the electronic component 110 (not shown, can refer to FIGS. 1-3 and FIG. 5).

8 is an enlarged view of a partial member of an electronic component package according to a seventh embodiment of the present invention, wherein FIG. 8 only shows a carrier board, a bottom barrier layer, a first insulating layer, a display dielectric layer, a protective layer, and the electronic component package; Barrier layer. 8, the electronic component package 10g includes a carrier 100, a bottom barrier layer 104, an insulating layer IN, a display dielectric layer EPL, a barrier layer 130c, a package board CG, and a sealant SE. The barrier layer 130c includes a sidewall contact portion 132. And an extension 134c. The display medium layer EPL is packaged between the carrier board 100 and the package board CG. The sealant SE surrounds the carrier sheet 100 and the package board CG around the display medium layer EPL. For the characteristics and arrangement relationship of the respective components in the electronic component package 10g, reference may be made to the above embodiments, and details are not described herein again. In the present embodiment, similar to the electronic component package 10e of FIG. 6, the extending portion 134c of the barrier layer 130 has a concave-convex surface 138c on an upper side away from the carrier sheet 100. For the specific formation of the uneven surface 138c, reference may be made to the related description of the embodiment of FIG. 6, and details are not described herein again. Unlike the uneven surface 138a of the electronic component package 10e, the uneven surface 138c has a stepped shape. The uneven surface 138c can also prevent moisture from diffusing from the outside of the sealant SE into the first insulating layer 122 in the insulating layer IN and contacting the electronic component 110, thereby maintaining the normal operation of the electronic component 110.

It is to be noted that the uneven surface 138a, the uneven surface 138b, and the uneven surface 138c of the extending portions 134a to 134c in FIGS. 6, 7, and 8 can be applied to the electronic component packages of FIGS. 1, 2, 3, and 5. In the body, the probability of the electronic components in the electronic component package being damaged by moisture is further reduced. Further, the present invention does not limit the specific uneven shape of the uneven surface, and the shapes of the uneven surface 138a, the uneven surface 138b, and the uneven surface 138c are merely exemplary but not limited thereto. For example, the shape of the concave-convex surface may be in a shape of a love, a triangle, or a combination of any one or more of the above, in addition to a zigzag shape, a micro cup shape, or a step shape.

Fig. 9 is an enlarged view of a partial member of an electronic component package in accordance with an eighth embodiment of the present invention. Referring to FIG. 9, the electronic component package 10h includes a carrier board 100, a bottom barrier layer 104, an insulating layer IN, a display dielectric layer EPL, and a barrier layer 130d. For the characteristics and arrangement relationship of the carrier board 100, the bottom barrier layer 104, the insulating layer IN, and the display medium layer EPL in the electronic component package 10g, reference may be made to the above embodiments, and details are not described herein again. In addition, the barrier layer 130d can be implemented by the barrier layer 130 in the foregoing embodiment. In addition, the electronic component package 10h may include the electronic component 110 and/or the sidewall blocking structure 150a or 150b described in the foregoing embodiments, but is not limited thereto. Specifically, in the embodiment, the display medium layer EPL is encapsulated between the carrier board 100 and the package board CG, and the sealant SE surrounds the display medium layer EPL for assembling the carrier board 100 and the package board CG. The manner in which the package board CG and the sealant SE of the present embodiment are disposed may be used in place of the protective layer PV in any of the foregoing embodiments. In other words, the embodiment of the present invention does not limit the packaging of the display medium layer EPL by the film-shaped protective layer PV, and the display medium layer EPL may be packaged by using the package board CG with the sealant SE.

In summary, in the electronic component package of the present invention, the arrangement of the barrier layer and the sidewall blocking structure can increase the number of interfaces in the electronic component package perpendicular to the plane of the carrier, wherein the interface is located around the electronic component package and Around the electronic components. In this way, the moisture can be effectively prevented from diffusing from the outside into the inside, and the probability that the electronic components in the electronic component package are damaged by the moisture from the side is reduced. In addition, the sidewall blocking structure can be integrated into the original process without additional cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h‧‧‧ electronic component package

100‧‧‧ carrying board

102A‧‧‧Soft substrate

102B‧‧‧Support substrate

104‧‧‧ bottom barrier

106‧‧‧Organic buffer layer

110‧‧‧Electronic components

112‧‧‧Organic film transistor

122‧‧‧First insulation

124‧‧‧Second insulation

126‧‧‧ sidewall section

130, 130a~130d‧‧‧ barrier layer

132, 132a~132c‧‧‧ sidewall contact

134, 134a~134c‧‧‧ extension

136‧‧‧ Coverage

138, 138a, 138b, 138c‧‧‧ concave surface

140, 142, 144‧‧ interface

150a, 150b‧‧‧ sidewall blocking structure

152a, 152b, 152c‧‧‧sub-blocking structure

AA‧‧‧ Central District

CG‧‧‧Package board

CH‧‧‧Organic semiconductor channel layer

D‧‧‧汲

EPL‧‧‧ display media layer

G‧‧‧ gate

IB‧‧ Inner Marginal Area

IN‧‧‧Insulation

M1‧‧‧Wiring

M2‧‧‧ conductive layer

OB‧‧‧ outer edge zone

PT‧‧‧Bumps

PV‧‧‧ protective layer

S‧‧‧ source

S1, S2, S3‧‧‧ side surface

SE‧‧‧ frame glue

1 is a schematic cross-sectional view showing an electronic component package in accordance with a first embodiment of the present invention. 2 is a cross-sectional view showing an electronic component package in accordance with a second embodiment of the present invention. 3 is a cross-sectional view showing an electronic component package in accordance with a third embodiment of the present invention. Fig. 4 is a top plan view showing the electronic component package 10c of the third embodiment. Fig. 5 is a cross-sectional view showing an electronic component package in accordance with a fourth embodiment of the present invention. Fig. 6 is an enlarged view of a partial member of an electronic component package in accordance with a fifth embodiment of the present invention. Fig. 7 is an enlarged view of a partial member of an electronic component package in accordance with a sixth embodiment of the present invention. Fig. 8 is an enlarged view of a partial member of an electronic component package in accordance with a seventh embodiment of the present invention. Fig. 9 is an enlarged view of a partial member of an electronic component package in accordance with an eighth embodiment of the present invention.

10c‧‧‧Electronic component package

100‧‧‧ carrying board

102A‧‧‧Soft substrate

102B‧‧‧Support substrate

104‧‧‧ bottom barrier

106‧‧‧Organic buffer layer

110‧‧‧Electronic components

112‧‧‧Organic film transistor

122‧‧‧First insulation

124‧‧‧Second insulation

126‧‧‧ sidewall section

130‧‧‧Barrier

132‧‧‧ sidewall contact

134‧‧‧Extension

136‧‧‧ Coverage

142, 144‧‧ interface

150a‧‧‧ sidewall blocking structure

152a, 152b‧‧‧sub-blocking structure

AA‧‧‧ Central District

CH‧‧‧Organic semiconductor channel layer

D‧‧‧汲

EPL‧‧‧ display media layer

G‧‧‧ gate

IB‧‧ Inner Marginal Area

M1‧‧‧Wiring

M2‧‧‧ conductive layer

OB‧‧‧ outer edge zone

PV‧‧‧ protective layer

S‧‧‧ source

S1, S2, S3‧‧‧ side surface

Claims (22)

An electronic component package includes: a carrier board including a central area, an inner edge area, and an outer edge area, the inner edge area being located between the central area and the outer edge area; an electronic component disposed on the a first insulating layer disposed on the carrier board, overlapping the electronic component and extending from the central region to the inner edge region; a barrier layer disposed on the carrier layer The barrier layer includes the cover portion, a sidewall contact portion, and an extension portion, the cover portion is disposed on the inner edge region over the first insulation layer The sidewall contact portion surrounds a side surface of the first insulating layer, and the extension portion extends from the sidewall contact portion to the outer edge region in a direction away from the first insulating layer; and a display dielectric layer disposed on the electron The component and the covering portion of the barrier layer are electrically connected to the electronic component and used to display an image. The electronic component package of claim 1, wherein the covering portion exposes the central region. The electronic component package of claim 1, wherein the electronic component comprises an organic thin film transistor, wherein the organic thin film transistor comprises a gate, a source, a drain, and an organic semiconductor channel layer. The area of the gate overlaps the area of the organic semiconductor channel layer. The first insulating layer is between the gate and the organic semiconductor channel layer, and the source and the drain are connected to the organic semiconductor channel layer. The electronic component package of claim 1, wherein the sidewall contact portion covers the side surface of the first insulating layer. The electronic component package of claim 1, further comprising a second insulating layer disposed between the second insulating layer and the carrier. The electronic component package of claim 5, wherein the second insulating layer has an area exceeding a side surface of the first insulating layer and has a sidewall portion, the sidewall portion being located at the first insulating layer The side surface is in contact with the side wall contact portion. The electronic component package of claim 1, further comprising a sidewall blocking structure disposed in the inner edge region and extending through the first insulating layer to form a barrier wall. The electronic component package of claim 7, wherein the sidewall blocking structure comprises a plurality of sub-barrier structures stacked in a direction perpendicular to the carrier. The electronic component package of claim 8, wherein the material of each of the sub-blocking structures comprises a metal. The electronic component package of claim 1, wherein the extension of the barrier layer forms an uneven surface on an upper side away from the carrier. The electronic component package according to claim 10, wherein the uneven surface is in a zigzag shape, a micro cup shape, a step shape or a combination of at least one of the above. The electronic component package according to claim 1, wherein the material of the barrier layer is SiNx, SiOx or a multilayer SiNx/SiOx film. The electronic component package of claim 1, further comprising: an organic buffer layer disposed between the electronic component and the carrier; a bottom barrier layer disposed on the organic buffer layer and the carrier And a protective layer disposed on the display medium layer. The electronic component package of claim 13, wherein the extension of the barrier layer contacts the bottom barrier layer. The electronic component package of claim 13, wherein the sidewall contact portion of the barrier layer covers a side surface of the organic buffer layer. An electronic component package includes: a carrier board, the carrier board includes a central area and an edge area; an electronic component disposed on the carrier board and located in the central area; and a plurality of insulating layers disposed on the carrier board And overlying the electronic component, the insulating layers respectively extending from the central region into the edge region; a sidewall blocking structure disposed in the edge region, wherein the sidewall blocking structure penetrates the insulating layers and constitutes a retaining wall And a display medium layer disposed on the electronic component and the sidewall blocking structure, wherein the display dielectric layer is electrically connected to the electronic component and used to display an image. The electronic component package of claim 16, wherein the sidewall blocking structure comprises a plurality of sub-barrier structures stacked in a direction perpendicular to the carrier. The electronic component package of claim 17, wherein one of the sub-blocking structures is electrically connected to the electronic component. The electronic component package of claim 17, wherein the material of each of the sub-blocking structures comprises a metal. The electronic component package of claim 19, wherein the sidewall blocking structure is electrically floating. The electronic component package of claim 16, wherein the electronic component comprises an organic thin film transistor, the insulating layer comprises a first insulating layer and a second insulating layer, wherein the organic thin film transistor comprises a gate, a source, a drain, and an organic semiconductor channel layer, the gate having an area overlapping the area of the organic semiconductor channel layer, the first insulating layer being located between the gate and the organic semiconductor channel layer The source and the drain are connected to the organic semiconductor channel layer, and the first insulating layer is disposed between the second insulating layer and the carrier. The electronic component package of claim 16, further comprising: an organic buffer layer disposed between the electronic component and the carrier plate; a bottom barrier layer disposed on the organic buffer layer and the carrier plate And a protective layer disposed on the display medium layer.