TWI693874B - Circuit carrier board structure and manufacturing method thereof - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
Description
本發明是有關於一種載板結構及其製作方法,且特別是有關於一種線路載板結構及其製作方法。The invention relates to a carrier board structure and a manufacturing method thereof, and particularly relates to a circuit carrier board structure and a manufacturing method thereof.
一般而言,線路板的多層線路結構大多採用增層(build up)方式或是壓合(laminated)方式來製作,因此具有高線路密度與縮小線路間距的特性。舉例來說,多層線路結構的製作方式是將銅箔(copper foil)與膠片(PrePreg)組成增層結構,並將增層結構反覆壓合而堆疊於核心層(core)上,來形成多層線路結構,以增加多層線路結構的內部佈線空間,其中增層結構上的導電材料可依據所需的線路佈局形成導電線路,而增層結構的盲孔或通孔中可另外填充導電材料來導通各層。如此,多層線路結構可依據需求調整線路結構的數量,並以上述方法製作而成。Generally speaking, the multi-layer circuit structure of the circuit board is mostly produced by a build-up method or a laminated method, so it has the characteristics of high circuit density and reduced circuit spacing. For example, the manufacturing method of the multilayer circuit structure is that copper foil (Copper foil) and film (PrePreg) are formed into a layered structure, and the layered structure is repeatedly laminated and stacked on the core layer to form a multilayer circuit In order to increase the internal wiring space of the multilayer circuit structure, the conductive material on the build-up structure can form a conductive circuit according to the required circuit layout, and the blind hole or the through hole of the build-up structure can be additionally filled with conductive material to conduct the layers . In this way, the multi-layer circuit structure can be adjusted according to the number of circuit structures required and manufactured by the above method.
隨著科技的進步,各類電子產品皆朝向高速、高效能、且輕薄短小的趨勢發展。在此趨勢下,多層線路結構的層數也隨之增加,以符合更複雜的電子產品設計。然而,隨著多層線路結構的層數增加,多層線路結構的翹曲(warpage issue)問題將變得更加嚴重。此外,多層線路結構的製程複雜,提升超微細線路的製作工藝難度,進而無法降低成本,更有生產良率不佳的問題。With the advancement of technology, all types of electronic products are developing towards high speed, high efficiency, and thin, light, and short. Under this trend, the number of layers of the multilayer circuit structure has also increased to meet the design of more complex electronic products. However, as the number of layers of the multilayer circuit structure increases, the warpage issue of the multilayer circuit structure will become more serious. In addition, the manufacturing process of the multi-layer circuit structure is complicated, which increases the difficulty of the manufacturing process of the ultra-fine circuit, which can not reduce the cost, and has the problem of poor production yield.
本發明提供一種線路載板結構及其製作方法,其可改善線路載板結構的翹曲問題、降低製作難度、製作成本、並提升生產良率,且具有良好品質。The invention provides a circuit carrier board structure and a manufacturing method thereof, which can improve the warpage problem of the circuit carrier board structure, reduce manufacturing difficulty, manufacturing cost, and increase production yield, and have good quality.
本發明的線路載板結構的製作方法包括以下步驟。提供臨時載板。形成第一基板於臨時載板上,第一基板具有第一表面以及相對第一表面的第二表面。提供第二基板,具有第三表面以及相對第三表面的第四表面。設置黏著層於第一基板與第二基板的其中之一者上,且黏著層位於第一基板與第二基板之間。組合第一基板的第二表面至第二基板的第三表面。以及,移除臨時載板,其中第一基板電性連接第二基板。The manufacturing method of the circuit board structure of the present invention includes the following steps. Provide temporary carrier board. A first substrate is formed on the temporary carrier. The first substrate has a first surface and a second surface opposite to the first surface. A second substrate is provided, having a third surface and a fourth surface opposite to the third surface. An adhesive layer is provided on one of the first substrate and the second substrate, and the adhesive layer is located between the first substrate and the second substrate. The second surface of the first substrate is combined with the third surface of the second substrate. And, the temporary carrier board is removed, wherein the first substrate is electrically connected to the second substrate.
在本發明的一實施例中,上述的形成第一基板的步驟包括形成離形層於臨時載板上。以及,形成多個第一增層依序堆疊於離形層上。各第一增層包括第一介電層以及第一線路層。各第一增層彼此電性連接。In an embodiment of the invention, the above step of forming the first substrate includes forming a release layer on the temporary carrier. And, a plurality of first build-up layers are sequentially stacked on the release layer. Each first build-up layer includes a first dielectric layer and a first circuit layer. The first build-up layers are electrically connected to each other.
在本發明的一實施例中,上述的提供第二基板的步驟包括提供第二基底。形成多個第二增層依序堆疊於第二基底上,其中各第二增層包括第二介電層以及第二線路層。以及,形成多個導電接墊於第三表面上,且導電接墊電性連接第二線路層。各第二增層彼此電性連接。In an embodiment of the invention, the step of providing the second substrate includes providing a second base. A plurality of second build-up layers are sequentially stacked on the second substrate, wherein each second build-up layer includes a second dielectric layer and a second circuit layer. And, a plurality of conductive pads are formed on the third surface, and the conductive pads are electrically connected to the second circuit layer. The second build-up layers are electrically connected to each other.
在本發明的一實施例中,上述的製作方法更包括以下步驟。形成多個貫孔貫穿第一基板並暴露導電接墊。形成種子層(seed layer)於第一表面上,並填入貫孔接觸導電接墊。形成覆蓋部分種子層的光阻圖案,以暴露出部分種子層。自暴露出的部分種子層形成多個導電結構,各導電結構電性連接各導電接墊以及第一線路層。移除光阻圖案以及光阻圖案所覆蓋的種子層。In an embodiment of the invention, the above manufacturing method further includes the following steps. A plurality of through holes are formed to penetrate the first substrate and expose the conductive pads. A seed layer is formed on the first surface, and a through hole is filled to contact the conductive pad. A photoresist pattern covering part of the seed layer is formed to expose part of the seed layer. A plurality of conductive structures are formed from the partially exposed seed layer, and each conductive structure is electrically connected to each conductive pad and the first circuit layer. The photoresist pattern and the seed layer covered by the photoresist pattern are removed.
在本發明的一實施例中,上述的形成第一基板的步驟更包括形成多個導電柱於第二表面上,並電性連接第一線路層。In an embodiment of the invention, the step of forming the first substrate further includes forming a plurality of conductive pillars on the second surface and electrically connecting the first circuit layer.
在本發明的一實施例中,上述的提供第二基板的步驟包括提供第二基底。形成多個第二增層依序堆疊於第二基底上,其中各第二增層包括第二介電層以及第二線路層。以及,形成多個導電盲孔於第三表面上,且導電盲孔電性連接第二線路層。各第二增層彼此電性連接。In an embodiment of the invention, the step of providing the second substrate includes providing a second base. A plurality of second build-up layers are sequentially stacked on the second substrate, wherein each second build-up layer includes a second dielectric layer and a second circuit layer. And, a plurality of conductive blind holes are formed on the third surface, and the conductive blind holes are electrically connected to the second circuit layer. The second build-up layers are electrically connected to each other.
在本發明的一實施例中,上述的組合第一基板至第二基板的步驟更包括組合導電柱至導電盲孔,以使導電柱電性連接並填入導電盲孔以形成導電結構。導電結構電性連接第二線路層以及第一線路層。In an embodiment of the present invention, the above-mentioned step of combining the first substrate to the second substrate further includes combining the conductive pillar to the conductive blind hole to electrically connect the conductive pillar and fill the conductive blind hole to form a conductive structure. The conductive structure is electrically connected to the second circuit layer and the first circuit layer.
在本發明的一實施例中,上述的製作方法更包括形成多個連接墊於第一表面上,連接墊電性連接第一線路層,其中第一線路層的線寬小於各連接墊的線寬。形成防焊層覆蓋第一表面以及第四表面,且防焊層暴露部分連接墊、第一線路層以及第二線路層。以及,進行表面處理程序。In an embodiment of the invention, the above manufacturing method further includes forming a plurality of connection pads on the first surface, the connection pads are electrically connected to the first circuit layer, wherein the line width of the first circuit layer is smaller than the lines of the connection pads width. A solder resist layer is formed to cover the first surface and the fourth surface, and the solder resist layer exposes a portion of the connection pad, the first circuit layer, and the second circuit layer. And, perform surface treatment procedures.
在本發明的一實施例中,上述的製作方法更包括設置多個電子元件於第一基板的第一表面上,且電子元件電性連接至連接墊及第一線路層。以及,設置多個焊球電性連接第二線路層。In an embodiment of the invention, the above-mentioned manufacturing method further includes placing a plurality of electronic components on the first surface of the first substrate, and the electronic components are electrically connected to the connection pad and the first circuit layer. And, a plurality of solder balls are provided to electrically connect the second circuit layer.
本發明的線路載板結構包括第一基板、第二基板、黏著層以及多個連接墊。第一基板具有第一表面以及相對第一表面的第二表面,包括多個第一增層依序堆疊,各第一增層包括第一介電層以及第一線路層,且各第一增層彼此電性連接。第二基板具有第三表面以及相對第三表面的第四表面,包括多個第二增層依序堆疊,各第二增層包括第二介電層以及第二線路層,且各第二增層彼此電性連接。黏著層位於第一基板與第二基板之間。第二表面組合至第三表面。連接墊位於第一表面上電性連接第一線路層。第一基板電性連接第二基板,第一線路層的線寬小於各連接墊的線寬,且第一線路層的線寬小於或等於10微米。The circuit board structure of the present invention includes a first substrate, a second substrate, an adhesive layer, and a plurality of connection pads. The first substrate has a first surface and a second surface opposite to the first surface, including a plurality of first build-up layers stacked sequentially, each first build-up layer includes a first dielectric layer and a first circuit layer, and each of the first build-up layers The layers are electrically connected to each other. The second substrate has a third surface and a fourth surface opposite to the third surface, including a plurality of second build-up layers stacked sequentially, each second build-up layer includes a second dielectric layer and a second circuit layer, and each second build-up layer The layers are electrically connected to each other. The adhesive layer is located between the first substrate and the second substrate. The second surface is combined to the third surface. The connection pad is located on the first surface and is electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate, the line width of the first circuit layer is less than the line width of each connection pad, and the line width of the first circuit layer is less than or equal to 10 microns.
在本發明的一實施例中,上述的第一基板更包括多個貫孔貫穿第一基板。第二基板更包括第二基底且第二增層設置於第二基底上,以及多個導電接墊位於第三表面上電性連接第二線路層。貫孔暴露導電接墊,且導電接墊填入貫孔中電性連接連接墊、導電接墊、第一線路層以及第二線路層。In an embodiment of the invention, the above-mentioned first substrate further includes a plurality of through holes penetrating the first substrate. The second substrate further includes a second substrate and the second build-up layer is disposed on the second substrate, and a plurality of conductive pads are located on the third surface and are electrically connected to the second circuit layer. The through hole exposes the conductive pad, and the conductive pad fills in the through hole to electrically connect the connection pad, the conductive pad, the first circuit layer and the second circuit layer.
在本發明的一實施例中,上述的各導電結構的頂面靠近第一表面,導電結構的底面靠近第二表面,且導電結構的頂面的直徑大於底面的直徑。第一線路層的頂面靠近第二表面,第一線路層的底面靠近第一表面,且第一線路層的頂面的直徑大於底面的直徑。In an embodiment of the invention, the top surface of each conductive structure is close to the first surface, the bottom surface of the conductive structure is close to the second surface, and the diameter of the top surface of the conductive structure is larger than the diameter of the bottom surface. The top surface of the first circuit layer is close to the second surface, the bottom surface of the first circuit layer is close to the first surface, and the diameter of the top surface of the first circuit layer is larger than the diameter of the bottom surface.
在本發明的一實施例中,上述的第一基板更包括多個導電柱位於第二表面上電性連接第一線路層。第二基板更包括第二基底且第二增層設置於第二基底上,以及多個導電盲孔位於第三表面上電性連接第二線路層。導電柱填入導電盲孔以形成多個導電結構,且導電結構電性連接第一線路層以及第二線路層。In an embodiment of the invention, the above-mentioned first substrate further includes a plurality of conductive posts on the second surface to electrically connect the first circuit layer. The second substrate further includes a second substrate and the second build-up layer is disposed on the second substrate, and a plurality of conductive blind holes are located on the third surface and are electrically connected to the second circuit layer. The conductive posts are filled with conductive blind holes to form a plurality of conductive structures, and the conductive structures are electrically connected to the first circuit layer and the second circuit layer.
在本發明的一實施例中,上述的線路載板結構更包括防焊層覆蓋第一表面以及第四表面。防焊層暴露部分連接墊、第一線路層以及第二線路層。In an embodiment of the invention, the circuit board structure described above further includes a solder mask covering the first surface and the fourth surface. The solder resist layer exposes part of the connection pad, the first circuit layer and the second circuit layer.
在本發明的一實施例中,上述的線路載板結構更包括多個電子元件位於第一基板的第一表面上、以及多個焊球電性連接第二線路層。電子元件電性連接至連接墊及第一線路層。In an embodiment of the invention, the circuit board structure described above further includes a plurality of electronic components located on the first surface of the first substrate, and a plurality of solder balls electrically connected to the second circuit layer. The electronic component is electrically connected to the connection pad and the first circuit layer.
基於上述,本發明的線路載板結構及其製作方法,可透過分別將多層第一增層以及第二增層設置於第一基板及第二基板中。如此,可減少在同一基板上形成增層的層數,改善製作多層增層產生的翹曲問題,並可降低製作難度、製作成本、並提升生產良率。此外,本發明的線路載板結構更可透過導電結構以及連接墊,以電性連接第一基板與第二基板。如此,線路載板結構不需額外的互連板結構即可達成與電子元件上精細接點接合的需求,更可透過全面性地設置於第二基板上的第一基板及設置於第一基板中的導電結構,電性連接第二基板。因此線路載板結構的佈線裕度可以大幅提升,更可提升多個電子元件之間訊號傳遞的訊號完整性,使線路載板結構具有良好的品質。Based on the above, the circuit carrier structure and the manufacturing method of the present invention can be provided by placing multiple first build-up layers and second build-up layers in the first substrate and the second substrate, respectively. In this way, the number of layers formed on the same substrate can be reduced, the warpage problem caused by the production of multiple layers can be improved, and the production difficulty, production cost, and production yield can be reduced. In addition, the circuit board structure of the present invention can further electrically connect the first substrate and the second substrate through the conductive structure and the connection pad. In this way, the circuit board structure can achieve the requirement of fine contact bonding with electronic components without an additional interconnection board structure, and can be more comprehensively provided through the first substrate on the second substrate and the first substrate The conductive structure in is electrically connected to the second substrate. Therefore, the wiring margin of the circuit board structure can be greatly improved, and the signal integrity of the signal transmission between multiple electronic components can also be improved, so that the circuit board structure has good quality.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.
下文列舉一些實施例並配合所附圖式來進行詳細地說明,但所提供的實施例並非用以限制本發明所涵蓋的範圍。此外,圖式僅以說明為目的,並未依照原尺寸作圖。為了方便理解,下述說明中相同的元件將以相同之符號標示來說明。The following lists some embodiments and details in conjunction with the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only, and are not drawn according to the original dimensions. For ease of understanding, the same elements in the following description will be described with the same symbols.
另外,關於文中所使用之「第一」、「第二」...等用語,並非表示順序或順位的意思,應知其是為了區別以相同技術用語描述的元件或操作。In addition, the terms "first", "second", etc. used in the text do not mean order or order, and it should be understood that they are used to distinguish elements or operations described in the same technical terms.
其次,在本文中所使用的用詞「包含」、「包括」、「具有」等等,均為開放性的用語;也就是指包含但不限於。Secondly, the terms "include", "include", "have", etc. used in this article are all open terms; that is, they include but are not limited to.
再者,在本文中所使用的用詞「接觸」、「相接」、「接合」等等,如無特別說明,則可代表直接接觸或者透過其他膜層間接地接觸。Furthermore, the terms "contact", "joint", "joint", etc. used in this article, unless otherwise specified, can represent direct contact or indirect contact through other membrane layers.
圖1是本發明一實施例的一種線路載板結構的剖面示意圖。請參考圖1,在本實施例中,線路載板結構1包括第一基板100具有第一表面102以及相對第一表面102的第二表面104、第二基板200具有第三表面202及相對第三表面202的第四表面204、黏著層170位於第一基板100的第一表面102與第二基板200的第三表面202之間、以及多個連接墊142位於第一表面102上。第一基板100包括多個第一增層120依序堆疊,且各第一增層120包括第一介電層122以及第一線路層124。各第一增層120彼此電性連接。第二基板200包括多個第二增層220依序堆疊,且各第二增層220包括第二介電層222以及第二線路層224,且各第二增層220彼此電性連接。舉例而言,第二基板200更包括第二基底210,且第二增層220設置於第二基底210上。多個連接墊142電性連接第一線路層124。第一基板100電性連接第二基板200。FIG. 1 is a schematic cross-sectional view of a circuit carrier structure according to an embodiment of the invention. Please refer to FIG. 1. In this embodiment, the
在本實施例中,線路載板結構1還包括防焊層180覆蓋第一表面102以及第四表面204,且防焊層180暴露部分連接墊142、第一線路層124以及第二線路層224。線路載板結構1更包括多個電子元件500位於第一基板100的第一表面102上以及多個焊球SB電性連接第二線路層224。電子元件500電性連接連接墊142及第一線路層124。以下將以一實施例說明線路載板結構1的製作方法。In this embodiment, the
圖2A至圖2D是本發明一實施例的第一基板的製造流程剖面示意圖。請參考圖2A至圖2D,線路載板結構1的製作方法包括以下步驟,首先提供臨時載板110,接著形成第一基板100於臨時載板110上。在本實施例中,第一基板100具有第一表面102及相對第一表面102的第二表面104(繪示於圖1D)。2A to 2D are schematic cross-sectional views of a manufacturing process of a first substrate according to an embodiment of the invention. Please refer to FIGS. 2A to 2D. The manufacturing method of the
在本實施例中,形成第一基板100的方法包括以下步驟。請再次參考圖2A,形成離形層130於臨時載板110上。在本實施例中,臨時載板110可以是玻璃基板(glass substrate)、矽基板(Si substrate)、陶瓷基板(ceramic substrate)或其組合,本發明不以此為限。離形層130可以是光固化離形膜(photo-curable release film)或熱固化離形膜(thermal curable release film),但本發明不以此為限。所述光固化離形膜的黏度(viscosity)會通過光固化(photo-curing)製程減小;而所述熱固化離形膜的黏度會通過熱固化(thermal-curing)製程減小。在其他實施例中,離形層130也可以是雷射離形膜(laser debond release film)。In this embodiment, the method of forming the
接著,請參考圖2B、圖2C以及圖2D,進行鍍覆製程,以形成多個第一增層120依序堆疊於離形層130上。在本實施例中,第一增層120包括第一介電層122以及第一線路層124。舉例而言,第一線路層124內嵌於第一介電層122,但本發明不以此為限。在本實施例中,如圖2B所示,先設置一層第一增層120於離形層130上。接著,請參考圖2C及圖2D,再依序組合多層第一增層120堆疊於前述之第一增層120上。如圖2D所示,本實施例的第一基板100是以三層第一增層120的堆疊舉例說明,但本發明不以此為限。在其他實施例中,第一增層120的數量可以為單層或多層,視使用者需求而設計。Next, please refer to FIGS. 2B, 2C, and 2D to perform a plating process to form a plurality of first build-up
在形成第一基板100的步驟後,接著設置黏著層170於第一基板100上。在本實施例中,黏著層170例如是作為第一增層120中的第一介電層122設置。換句話說,黏著層與介電層例如是相同的材質,因此在後續組合的製程中,不需額外透過設置黏著材料的步驟,即可直接組合第一基板100與第二基板200,以簡化製程。在本實施例中,黏著層170(例如最外層的第一介電層122)的第二表面104組合至第二基板200的第三表面202。黏著層170的材料包括介電材料,所述介電材料包括選自膠片、耐燃玻璃纖維(FR4)、背膠銅箔、ABF膜、黏膠、防焊材料或感光型介電材料的其中一者,但本發明不以此為限。After the step of forming the
在本實施例中,第一基板100例如為重佈置線路層(redistribution layer, RDL),且每一層的第一增層120的第一線路層124可應用為重佈置線路,但本發明不以此為限。在本實施例中,第一線路層124是以超微細線路的工藝設置,其線寬小於或等於10微米,但本發明不以此為限。各第一增層120彼此電性連接。在本實施例中,第一線路層124的材料包括金屬材料,其可例如是銅或類似材料。第一介電層122的材料包括介電材料。所述介電材料例如為膠片(PrePreg)、感光型介電材料(photoimageable dielectric, PID)、感光性聚合體(例如苯並環丁烯,Benzocyclobutene)、ABF膜(Ajinomoto build-up film)、背膠銅箔(resin coated cooper foil, RCC)、玻璃纖維樹脂複合材料或其組合,本發明不以此為限。In this embodiment, the
圖3A至圖3E是本發明一實施例的第二基板的製造流程剖面示意圖。接著,請參考圖3A至圖3E,提供第二基板200。第二基板200具有第三表面202以及相對第三表面202的第四表面204(繪示於圖3E)。本實施例的第二基板200是以高密度連接板(High Density Interconnect, HDI)為例進行說明,然而本發明不以此為限。在其他實施例中,第二基板200也可以是無核心基板(coreless)、印刷電路板(printed circuit board, PCB)或任意層印刷電路板(any-layer printed circuit board)。3A to 3E are schematic cross-sectional views of a manufacturing process of a second substrate according to an embodiment of the invention. Next, please refer to FIGS. 3A to 3E to provide a
在本實施例中,提供第二基板200的方法包括以下步驟。請再次參考圖3A,首先提供第二基底210。第二基底210包括有核基板(core)或無核心基板(coreless)。在本實施例中,第二基底210可以是絕緣基板、玻璃基板或其組合,本發明不以此為限。在其他實施例中,第二基底也可以是膠片(PrePreg)或是其他合適的介電材料。In this embodiment, the method of providing the
在本實施例中,可選擇性地在第二基底210上設置光阻圖案(未標示),以在第二基底210中形成多個貫穿第二基底210的開孔(未標示),但本發明不以此為限。在其他實施例中,開孔的形成方式也可以是機械鑽孔、雷射鑽孔或是其他合適的方法。In this embodiment, a photoresist pattern (not labeled) may be selectively provided on the
接著,進行鍍覆製程,以分別形成多個第二增層220依序堆疊於第二基底210的相對的兩個表面上。在本實施例中,第二增層220包括第二介電層222以及第二線路層224。舉例而言,第二線路層224內嵌於第二介電層222,但本發明不以此為限。在本實施例中,如圖3C所示,先設置一層第二增層220於第二基底210上。接著,請參考圖3C及圖3D,再依序組合多層第二增層220堆疊於前述之第二增層220上。如圖3E所示,本實施例的第二基板200包括三層第二增層220的堆疊分別設置在第二基底210的相對兩個表面上舉例說明,但本發明不以此為限。在其他實施例中,第二增層220的數量可以為單層或多層,視使用者需求而設計。在其他實施例中,第二增層220也可以僅設置在第二基底210的其中一個表面上,本發明不以此為限。Next, a plating process is performed to form a plurality of second build-up
請參考圖3E,形成多個導電接墊240於第二基板200的第三表面202上。在本實施例中,導電接墊240電性連接第二線路層224。在本實施例中,第三表面202舉例是第二基板200最上層的表面,且第三表面202面對第一基板100(繪示於圖4A)。在本實施例中導電接墊240的材料包括金屬材料,其可例如是銅或類似材料。Referring to FIG. 3E, a plurality of
在本實施例中,各第二增層220彼此電性連接。在本實施例中,第二線路層224的材料包括金屬材料,其可例如是銅或類似材料。第二介電層222的材料包括介電材料。所述介電材料例如為膠片(PrePreg)、感光型介電材料(photoimageable dielectric, PID)、感光性聚合體(例如苯並環丁烯,Benzocyclobutene)、ABF膜(Ajinomoto build-up film)、背膠銅箔(resin coated cooper foil, RCC)、玻璃纖維樹脂複合材料或其組合,本發明不以此為限。In this embodiment, the second build-up
圖4A至圖4G是本發明一實施例的線路載板的製造流程的剖面示意圖。請參考圖4A,在形成第一基板100以及提供第二基板200的步驟後,接著組合第一基板100的第二表面104至第二基板200的第三表面202。在上述組合的步驟之前,本實施例是以先將黏著層170作為第一介電層122而設置在第一基板100,但本發明不以此為限。在一些實施例中,可設置黏著層170於第一基板100與第二基板200的其中之一者上。舉例而言,黏著層也可作為最外層的第二介電層222以設置在第二基板200,但本發明不以此為限。4A to 4G are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to an embodiment of the invention. Referring to FIG. 4A, after the steps of forming the
接著,請參考圖4A以及圖4B,在組合第一基板100的第二表面104至第二基板200的第三表面202後,接著,移除臨時載板110以及形成於臨時載板110上的離形層130。在本實施例中,最靠近第一表面102的第一線路層124可視為凸塊結構,但本發明不以此為限。在其他實施例中,上述第一線路層124亦可以是凸塊下金屬(UBM)層。在本實施例中,第二線路層224的線寬大於第一線路層124的線寬,且第二線路層的線寬為10微米至數百微米,但本發明不以此為限。4A and 4B, after combining the
值得注意的是,本發明可以分別形成第一基板100以及第二基板200,再透過組合第一基板100至第二基板200。如此,可以分別將多層增層設置形成在不同基板中,再組合成一體。進而可以減少在同一基板上形成增層的層數,改善製作多層增層產生的翹曲問題,並可降低製作難度、製作成本、並提升生產良率。It is worth noting that the present invention can form the
請參考圖4C,在本實施例中,線路載板結構1的製作方法更包括以下步驟。於移除臨時載板110之後,形成多個貫孔150貫穿第一基板100並暴露導電接墊240。舉例而言,貫孔150形成於多個第一增層120中並貫穿前述的多個第一增層120的堆疊。在本實施例中,貫孔150的形成方法可以是機械鑽孔、雷射鑽孔或是其他合適的方法,本發明不以此為限。貫孔150的剖面例如是錐形,但本發明不以此為限。Please refer to FIG. 4C. In this embodiment, the manufacturing method of the
接著,請參考圖4D,形成種子層140’(seed layer)於第一基板100的第一表面102上,並填入貫孔150接觸導電接墊240。舉例而言,種子層140’共形地覆蓋第一表面102以及貫孔150的表面。在本實施例中,種子層140’的材料包括金屬材料,其可以是銅或鈦/銅。種子層140’的形成方法包括化學鍍、濺鍍或其組合,本發明不以此為限。Next, referring to FIG. 4D, a seed layer 140' (seed layer) is formed on the
然後,請參考圖4E,形成覆蓋部分種子層140的光阻圖案160,以暴露出部分種子層140’。舉例而言,光阻圖案160暴露填入貫孔150的部分種子層140’,以及暴露出部分覆蓋第一線路層124的種子層140’。在本實施例中,光阻圖案160可用以定義後續形成的導電結構140(繪示於圖4F)的位置。光阻圖案160的材料包括感光型介電材料、聚醯亞胺、或是聚苯噁唑(Polybenzoxazole, PBO)、矽利康(Silicone)、環氧樹脂(Epoxy)、苯並環丁烯(BCB)或其他合適的材料,但本發明不以此為限。Then, referring to FIG. 4E, a
接著,請參考圖4E以及圖4F,進行鍍覆製程,以自暴露出的部分種子層140’形成多個導電結構140。舉例而言,可透過電鍍或化學鍍,在貫孔150中形成導電結構140。換句話說,導電結構140填入貫孔150中,並電性連接導電接墊240。接著,移除光阻圖案160以及光阻圖案160所覆蓋的種子層140’。Next, referring to FIGS. 4E and 4F, a plating process is performed to form a plurality of
在本實施例中,在移除光阻圖案160之前,更包括形成多個連接墊142於第一表面102上,且連接墊142電性連接第一線路層124。在本實施例中,連接墊142與導電結構140係同時完成的,但本發明不以此為限。舉例而言,形成多個導電結構140的同時,部分暴露出的種子層140’也可以同時形成連接墊142於第一線路層124上,且連接墊142電性連接導電結構140。如此,導電結構140與連接墊142可同時在一次鍍覆製程中形成而被視為一體的結構。在本實施例中,導電結構140電性連接導電接墊240以及第一線路層124。由於第一線路層124可透過連接墊142以及導電結構140,以電性連接至導電接墊240以及第二線路層224,因此完成第一基板100電性連接第二基板200。In this embodiment, before removing the
在本實施例中,導電結構140的頂面141與第一線路層124的頂面123所靠近的表面不同。舉例而言,導電結構140的頂面141靠近第一表面102,導電結構140的底面143靠近第四表面204,且導電結構140的頂面141的直徑大於底面143的直徑。第一線路層124的頂面123靠近第四表面204,第一線路層124的底面121靠近第一表面102,且第一線路層124的頂面123的直徑大於底面121的直徑。導電結構140的剖面呈錐形,但本發明不以此為限。In this embodiment, the
值得注意的是,本發明可以在第一基板100組合至第二基板200後,再於第一基板100上形成貫孔150以設置導電結構140以及形成連接墊142。在上述的設置下,本發明可先製作超微細線路的第一線路層124,再進行一般線寬之導電結構140以及連接墊142的製作。如此,本發明可以簡單的製程方法,在第一基板100上製作線寬不同的第一線路層124、導電結構140以及連接墊142。舉例而言,第一線路層124的線寬小於連接墊142的線寬。由於,第一基板100可同時具有超微細線寬的第一線路層124以及一般線寬的連接墊142,因此不需額外的互連板結構即可達成與晶片上精細接點接合的精細走線需求(例如UBM),以及導通第一基板100與第二基板200的一般走線需求,進而提升線路佈局的裕度,使線路載板結構1具有良好的品質。It is worth noting that in the present invention, after the
接著,請繼續參考圖4G,形成防焊層180覆蓋第一表面102以及第四表面204。在本實施例中,防焊層180暴露部分連接墊142、第一線路層124以及第二線路層224。防焊層180的材料包括綠漆、感光型介電材料、ABF膜、以及高分子樹脂材料,本發明不以此為限。Next, please continue to refer to FIG. 4G to form a
接著,在本實施例中,選擇性地進行表面處理程序。表面處理程序包括無電鍍鎳無電鍍鈀浸金(electroless nickel/electroless palladium/ immersion gold, ENEPIG)、無電鍍鎳自催化金(electroless nickel autocatalytic gold, ENAG)、浸鍍錫(immersion tin, IT)、微錫球植球(Micro-ball)、以及305錫銀銅合金錫膏(SAC 305)。至此,本發明的線路載板10便製作完成。Next, in this embodiment, the surface treatment process is selectively performed. Surface treatment procedures include electroless nickel/electroless palladium/immersion gold (ENEPIG), electroless nickel autocatalytic gold (ENAG), immersion tin (IT), Micro-ball and Micro-ball, and 305 tin-silver-copper alloy solder paste (SAC 305). At this point, the
然後,請參考圖1及圖4G,設置多個電子元件500於第一基板100的第一表面102上。電子元件500電性連接至連接墊142及第一線路層124。最後,設置多個焊球SB電性連接第二線路層224。至此,已完成線路載板結構1的製作。在本實施例中,電子元件500舉例為晶片,且具有精細線寬的接點以及一般線寬的接點(未標示),分別與第一線路層124以及連接墊142電性連接。在上述的設置下,本發明的線路載板10可不需透過額外的互連結構即可達成與晶片上精細接點接合。多個電子元件500可透過第一基板100彼此電性連結,並且可透過導電結構140電性連接第二基板200,進而提升線路載板結構1的佈線裕度,更可提升多個電子元件500之間訊號傳遞的訊號完整性。Then, referring to FIGS. 1 and 4G, a plurality of
簡言之,本發明的線路載板結構1可透過分別將多層第一增層120以及第二增層220設置於第一基板100及第二基板200中。如此,可減少在同一基板上形成增層的層數,改善製作多層增層產生的翹曲問題,並可降低製作難度、製作成本、並提升生產良率。此外,本發明的線路載板結構1還可以在第一基板100組合至第二基板200後,於第一基板100上設置導電結構140以及連接墊142,以電性連接第一基板100與第二基板200。如此,線路載板結構1不需額外的互連板結構即可透過第一基板100的超細微的第一線路層124及連接墊142電性連接電子元件500(例如晶片)。藉此,線路載板結構1除了達成與電子元件500上精細接點接合的需求,更可透過全面性地設置於第二基板200上的第一基板100及設置於第一基板100中的導電結構140,電性連接第二基板200。因此線路載板結構1的佈線裕度可以大幅提升,更可提升多個電子元件500之間訊號傳遞的訊號完整性,使線路載板結構1具有良好的品質。In short, the
在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,關於省略了相同技術內容的部分說明可參考前述實施例,下述實施例中不再重複贅述。It must be noted here that the following embodiments follow the element numbers and partial contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements. For the description of the parts that omit the same technical contents, refer to the foregoing embodiments. Details are not repeated in the following embodiments.
圖5A至圖5D是本發明另一實施例的線路載板的製造流程的剖面示意圖。請先參考圖4G及圖5D,本實施例的線路載板10A與圖4G的線路載板10相似,主要的差異在於:線路載板10A的第一基板100A更包括多個導電柱300、第二基板200A更包括多個導電盲孔260。導電柱300填入導電盲孔260以形成導電結構320,且導電結構320電性連接第一線路層124以及第二線路層224。以下將以一實施例說明線路載板10A的製作方法。5A to 5D are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to another embodiment of the invention. Please refer to FIGS. 4G and 5D first. The
請參考圖5A,形成多個導電柱300於第二表面104上,並電性連接第一線路層124。形成導電柱300的方法例如透過鍍覆製程,在第一線路層124上形成導電柱300。導電柱300與第一線路層124的材料包括金屬材料,其可例如是銅或類似材料。在本實施例中,多個導電柱300彼此分離且剖面呈柱形。在本實施例中,於形成最靠近臨時載板110的第一增層120時,可同時形成第一線路層124以及連接墊142A。舉例而言,第一線路層124與連接墊142A可實際上一體成形,但本發明不以此為限。在其他實施例中,連接墊142A也可以在移除臨時載板110後形成。Referring to FIG. 5A, a plurality of
接著,請參考圖5B,形成多個導電盲孔260於第三表面202上,並電性連接第二線路層224。導電盲孔260的材料包括金屬材料,其可以是銅或鈦/銅。導電盲孔260的形成方法包括化學鍍、濺鍍或其組合,本發明不以此為限。Next, referring to FIG. 5B, a plurality of conductive
接著,請參考圖5B以及圖5C,組合第一基板100A至第二基板200A。然後,移除臨時載板110以及形成於臨時載板110上的離形層130。然後,請參考圖5D,形成防焊層180覆蓋第一表面102及第四表面204,並暴露連接墊142A、第一線路層124以及第二線路層224。如此,於後續設置電子元件以及焊球(繪示於圖1)的製程中,可以直接將電子元件電性連接第一線路層124,焊球電性連接第二線路層224,以降低製作難度、製作成本、並提升生產良率。Next, please refer to FIGS. 5B and 5C to combine the
值得注意的是,組合第一基板100A至第二基板200A的步驟包括藉由一定的溫度與壓力,將導電柱300組合至導電盲孔260,以使導電柱300電性連接並填入導電盲孔260以形成導電結構320。在本實施例中,所述組合步驟的溫度與壓力可依材料或製程需求來進行調整。在本實施例中,導電柱300與導電盲孔260的材料相同。舉例來說,導電柱300的材料與導電盲孔260的材料皆為金屬銅。因此,本實施例可透過銅對銅接合而將第一基板100A與第二基板200A接合在一起,以形成線路載板10A。It is worth noting that the step of combining the
在本實施例中,導電結構320的剖面呈錐形或柱形,但本發明不以此為限。舉例而言,導電結構320靠近第一表面102的頂面(未標示)的直徑可以大於或等於靠近第四表面204的底面(未標示)的直徑。如此,導電結構320可依設計需求而形成底面的直徑較頂面的直徑來得小的錐狀,或底面與頂面的直徑相同的柱狀。藉此,導電結構320可以電性連接第二線路層224以及第一線路層,更提供良好的接合可靠度及品質,降低製作難度、製作成本、並提升生產良率。此外,藉由上述的設計,本實施例的線路載板10A還可獲致與上述實施例相同的效果,於此不再贅述。In this embodiment, the cross-section of the
圖6A至圖6H是本發明又一實施例的線路載板的製造流程的剖面示意圖。請先參考圖4G及6H,本實施例的線路載板10B與圖4G的線路載板10相似,主要的差異在於:本實施例的第二基板200B不包括第二基底。具體而言,本實施例的第二基板200B是以無核心基板舉例進行說明。6A to 6H are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention. Please refer to FIGS. 4G and 6H first. The
請參考圖4A及圖6A,本實施例的第一基板100與圖4A的第一基板100相同,於此不再贅述。第二基板200B包括多個第二增層22依序堆疊,且設置於第二基底210A的相對兩個表面上。舉例來說上下的兩個第二基板200B的第四表面204設置於第二基底210A的相對兩個表面上。第二基底210A的材料可包括玻璃、陶瓷、高分子材料或具可撓性的介電材料或其他適用材質,本發明不以此為限。在其他實施例中,第二基底210A的材料也可以包括膠片(PrePreg)。Please refer to FIG. 4A and FIG. 6A. The
接著,如圖6A所示,上下的兩個第一基板100的第二表面104分別組合至上下的兩個第二基板200B的第三表面202。然後,請參考圖6B,移除臨時載板110。詳細的接合及移除步驟已於上述段落說明過,於此便不再贅述。Next, as shown in FIG. 6A, the
接著,請參考圖6C,將第二基底210A移除,以得到兩個無核心的第二基板200B。如此,可以提升製作效率、降低成本並提升生產良率。Next, referring to FIG. 6C, the
接著,請參考圖6D、圖6E、圖6F、圖6G及圖6H,形成多個導電結構140填入貫孔150中電性連接連接墊142、導電接墊240、第一線路層120以及第二線路層224。詳細的形成步驟已於上述段落說明過,於此便不再贅述。如此,線路載板10B的第一基板100可以電性連接第二基板200B,並獲致與上述實施例相同的效果。Next, please refer to FIG. 6D, FIG. 6E, FIG. 6F, FIG. 6G and FIG. 6H, forming a plurality of
圖7是本發明又一實施例的線路載板的剖面示意圖。請參考圖6H及圖7,本實施例的線路載板10C與圖6H的線路載板10B相似,主要的差異在於:本實施例的第一基板100A組合至第二基板200C,使導電柱填入導電盲孔(繪示於圖5B中)以形成導電結構320,且導電結構320電性連接第一線路層124以及第二線路層224。詳細的組合步驟已於上述段落說明過,於此便不再贅述。如此,線路載板10C的第一基板100A可以電性連接第二基板200C,並獲致與上述實施例相同的效果。7 is a schematic cross-sectional view of a circuit carrier board according to another embodiment of the invention. Please refer to FIG. 6H and FIG. 7, the
圖8A是本發明又一實施例的線路載板的製造流程的剖面示意圖。請參考圖4G及圖8A,本實施例的線路載板10D與圖4G的線路載板10相似,主要的差異在於:本實施例的第二基板400是印刷電路板。具體而言,第二基板400包括第二基底410以及多個第二增層420依序堆疊於第二基底410上。第二增層420包括第二介電層422以及第二線路層424,且各第二增層420彼此電性連接。第一基板100設置於第二基板400上且第一基板100電性連接第二基板400。詳細的形成步驟已於上述段落說明過,於此便不再贅述。如此,線路載板10D的第一基板100可以電性連接第二基板400,並獲致與上述實施例相同的效果。在本實施例中,第二基板400是以印刷電路板舉例進行說明,然而本發明不以此為限。在其他實施例中,第二基板也可以是任意層印刷電路板。8A is a schematic cross-sectional view of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention. 4G and FIG. 8A, the
圖8B是本發明再一實施例的線路載板的製造流程的剖面示意圖。請參考圖8A及圖8B,本實施例的線路載板10E與圖8A的線路載板10D相似,主要的差異在於:本實施例的第一基板100A組合至第二基板400A,使導電柱填入導電盲孔(繪示於圖5B中)以形成導電結構320,且導電結構320電性連接第一線路層124以及第二線路層424。詳細的組合步驟已於上述段落說明過,於此便不再贅述。如此,線路載板10E的第一基板100A可以電性連接第二基板400A,並獲致與上述實施例相同的效果。在本實施例中,第二基板400A是以印刷電路板舉例進行說明,然而本發明不以此為限。在其他實施例中,第二基板也可以是任意層印刷電路板。8B is a schematic cross-sectional view of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention. Please refer to FIGS. 8A and 8B. The
綜上所述,本發明的線路載板結構及其製作方法可透過分別將多層第一增層以及第二增層設置於第一基板及第二基板中。如此,可減少在同一基板上形成增層的層數,改善製作多層增層產生的翹曲問題,並可降低製作難度、製作成本、並提升生產良率。此外,本發明的線路載板結構更可透過導電結構以及連接墊,以電性連接第一基板與第二基板。如此,線路載板結構不需額外的互連板結構即可透過第一基板的超細微的第一線路層及連接墊電性連接電子元件(例如晶片)。藉此,線路載板結構除了達成與電子元件上精細接點接合的需求,更可透過全面性地設置於第二基板上的第一基板及設置於第一基板中的導電結構,電性連接第二基板。因此線路載板結構的佈線裕度可以大幅提升,更可提升多個電子元件之間訊號傳遞的訊號完整性,使線路載板結構具有良好的品質。此外,線路載板結構更可包括導電柱與導電盲孔以銅對銅接合方式形成的導電結構,可進一步提供良好的接合可靠度及品質,降低製作難度、製作成本、並提升生產良率。此外,本發明的線路載板結構的製作方法可以應用於高密度連接板、無核心基板、印刷電路板或任意層印刷電路板,具有優良的適用性。In summary, the circuit board structure and the manufacturing method of the present invention can be implemented by arranging multiple first build-up layers and second build-up layers in the first substrate and the second substrate, respectively. In this way, the number of layers formed on the same substrate can be reduced, the warpage problem caused by the production of multiple layers can be improved, and the production difficulty, production cost, and production yield can be reduced. In addition, the circuit board structure of the present invention can further electrically connect the first substrate and the second substrate through the conductive structure and the connection pad. In this way, the circuit carrier structure can be electrically connected to the electronic component (such as a chip) through the ultra-fine first circuit layer of the first substrate and the connection pad without additional interconnection structure. In this way, in addition to meeting the demand for fine contact bonding on electronic components, the circuit carrier structure can be electrically connected through the first substrate provided on the second substrate and the conductive structure provided in the first substrate Second substrate. Therefore, the wiring margin of the circuit board structure can be greatly improved, and the signal integrity of the signal transmission between multiple electronic components can also be improved, so that the circuit board structure has good quality. In addition, the circuit board structure may further include a conductive structure formed by a conductive pillar and a conductive blind hole formed by copper-to-copper bonding, which can further provide good bonding reliability and quality, reduce manufacturing difficulty, manufacturing cost, and increase production yield. In addition, the manufacturing method of the circuit carrier structure of the present invention can be applied to high-density connection boards, coreless substrates, printed circuit boards, or printed circuit boards of arbitrary layers, and has excellent applicability.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.
1‧‧‧線路載板結構10、10A、10B、10C、10D、10E‧‧‧線路載板100、100A‧‧‧第一基板102‧‧‧第一表面104‧‧‧第二表面110‧‧‧臨時載板120‧‧‧第一增層121、143‧‧‧底面122‧‧‧第一介電層123、141‧‧‧頂面124‧‧‧第一線路層130‧‧‧離形層140、320‧‧‧導電結構140’‧‧‧種子層142、142A‧‧‧連接墊150‧‧‧貫孔160‧‧‧光阻圖案170‧‧‧黏著層180‧‧‧防焊層200、200A、200B、200C、400、400A‧‧‧第二基板202‧‧‧第三表面204‧‧‧第四表面210、210A‧‧‧第二基底220、420‧‧‧第二增層222、422‧‧‧第二介電層224、424‧‧‧第二線路層240‧‧‧導電接墊260‧‧‧導電盲孔300‧‧‧導電柱500‧‧‧電子元件SB‧‧‧焊球1‧‧‧
圖1是本發明一實施例的一種線路載板結構的剖面示意圖。 圖2A至圖2D是本發明一實施例的第一基板的製造流程剖面示意圖。 圖3A至圖3E是本發明一實施例的第二基板的製造流程剖面示意圖。 圖4A至圖4G是本發明一實施例的線路載板的製造流程的剖面示意圖。 圖5A至5D是本發明另一實施例的線路載板的製造流程的剖面示意圖。 圖6A至圖6H是本發明又一實施例的線路載板的製造流程的剖面示意圖。 圖7是本發明又一實施例的線路載板的剖面示意圖。 圖8A是本發明又一實施例的線路載板的製造流程的剖面示意圖。 圖8B是本發明再一實施例的線路載板的製造流程的剖面示意圖。FIG. 1 is a schematic cross-sectional view of a circuit carrier structure according to an embodiment of the invention. 2A to 2D are schematic cross-sectional views of a manufacturing process of a first substrate according to an embodiment of the invention. 3A to 3E are schematic cross-sectional views of a manufacturing process of a second substrate according to an embodiment of the invention. 4A to 4G are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to an embodiment of the invention. 5A to 5D are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to another embodiment of the invention. 6A to 6H are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention. 7 is a schematic cross-sectional view of a circuit carrier board according to another embodiment of the invention. 8A is a schematic cross-sectional view of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention. 8B is a schematic cross-sectional view of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention.
1‧‧‧線路載板結構 1‧‧‧ Line carrier board structure
100‧‧‧第一基板 100‧‧‧The first substrate
102‧‧‧第一表面 102‧‧‧First surface
104‧‧‧第二表面 104‧‧‧Second surface
120‧‧‧第一增層 120‧‧‧The first layer
122‧‧‧第一介電層 122‧‧‧First dielectric layer
124‧‧‧第一線路層 124‧‧‧ First circuit layer
140‧‧‧導電結構 140‧‧‧conductive structure
142‧‧‧連接墊 142‧‧‧ connection pad
180‧‧‧防焊層 180‧‧‧Soldering layer
200‧‧‧第二基板 200‧‧‧Second substrate
202‧‧‧第三表面 202‧‧‧The third surface
204‧‧‧第四表面 204‧‧‧Fourth surface
210‧‧‧第二基底 210‧‧‧Second base
220‧‧‧第二增層 220‧‧‧The second layer
222‧‧‧第二介電層 222‧‧‧Second dielectric layer
224‧‧‧第二線路層 224‧‧‧ Second circuit layer
240‧‧‧導電接墊 240‧‧‧Conductive pad
500‧‧‧電子元件 500‧‧‧Electronic components
SB‧‧‧焊球 SB‧‧‧Solder ball
Claims (20)
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US16/244,113 US10888001B2 (en) | 2018-06-08 | 2019-01-10 | Circuit carrier board structure and manufacturing method thereof |
US16/503,500 US11032917B2 (en) | 2018-06-08 | 2019-07-04 | Circuit carrier board and manufacturing method thereof |
US16/535,102 US10999939B2 (en) | 2018-06-08 | 2019-08-08 | Circuit carrier board and manufacturing method thereof |
US16/950,910 US11678441B2 (en) | 2018-06-08 | 2020-11-18 | Manufacturing method of circuit carrier board structure |
US17/219,898 US20210219435A1 (en) | 2018-06-08 | 2021-04-01 | Manufacturing method of circuit carrier board |
US17/315,357 US20210282277A1 (en) | 2018-06-08 | 2021-05-10 | Manufacturing method of circuit carrier board |
US18/089,465 US20230137841A1 (en) | 2018-06-08 | 2022-12-27 | Circuit carrier and manufacturing method thereof and package structure |
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