TWI690056B - Static random-access memory (sram）cell array and forming method thereof - Google Patents

Abstract

A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (passing-gate) FinFET shares at least one active fin with a PD (pull-down) FinFET, at least one dummy fin is disposed between two adjacent active fins of PU (pull-up) FinFETs in a memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Description

Static random access memory cell array and forming method thereof

The invention relates to a static random access memory cell array and a method for forming the same, and particularly relates to a static random access memory cell array using a sacrificial fin structure and a method for forming the same.

Random access memory (RAM: Random Access Memory) can be used to read data or write data, the data disappears immediately after the power is turned off. Since the data of the random access memory is easy to change, it is generally used in a personal computer as a memory for temporarily storing data. Random access memory can be subdivided into "Dynamic" and "Static".

"Dynamic Random Access Memory (DRAM: Dynamic RAM)" is a transistor plus a capacitor to store 1 bit (1bit) of data, and when using it must periodically replenish power to maintain memory The content is called "Dynamic". The structure of dynamic random access memory is relatively simple (1 transistor plus 1 capacitor to store 1 bit of data), which makes the access speed slower (capacitor charging and discharging takes longer time), but the cost is also lower Therefore, it is generally made into a memory with a high capacity requirement but a low speed requirement, such as a main memory (main memory) commonly used on a motherboard of a personal computer.

"Static Random Access Memory (SRAM: Static RAM)" is stored with 6 transistors One bit (1bit) of data, and when using it does not need to periodically supplement the power to maintain the contents of the memory, so it is called "Static". The structure of static random access memory is more complicated (6 transistors store 1 bit of data), which makes the access speed faster, but the cost is also higher, so it is generally made to have lower capacity requirements but speed requirements Higher memory, for example, the central processing unit (CPU) of the personal computer has a built-in 256KB or 512KB cache memory. Because the speed of the central processor determines how fast the computer can calculate data and process information, the capacity of the main memory determines how much information the computer can store, so the cache memory is used to store some frequently used information. Frequently used information is placed in the faster cache memory to enable the central processor to quickly obtain this information, without having to go to the slower main memory to find, so that the central The processing speed of the processor is accelerated.

The invention provides a static random access memory cell array and a method for forming the same, which can promote the reliability of the manufacturing process and improve the performance of the static random access memory.

The invention provides a method for forming a static random-access memory (SRAM) cell array, which includes the following steps. First, patterning to form a plurality of fin structures on a substrate, wherein the fin structures include a plurality of active fin structures and a plurality of sacrificial fin structures, each channel transistor (PG FinFET) and a corresponding drop The piezoelectric crystal (PD FinFET) at least shares an active fin structure, and at least one sacrificial fin structure is disposed between two active fin structures spanned by two adjacent boost transistors (PU FinFET) in a memory cell structure. Next, at least a portion of these sacrificial fin structures are removed.

The invention provides a static random-access memory (static random-access memory, SRAM) cell array, including a plurality of fin-like structures on a substrate. These fin-shaped structures include a plurality of active fin-shaped structures and a plurality of remaining sacrificial fin-shaped structures shorter than these active fin-shaped structures, wherein each channel transistor (PG FinFET) and the corresponding one of the reduced piezoelectric crystals ( PD FinFET) at least share an active fin structure, at least one remaining sacrificial fin structure is arranged between two active fin structures spanned by two adjacent boost transistors (PU FinFET) in a memory cell .

Based on the above, the present invention proposes a static random access memory cell array and a method of forming the same, which is first patterned to form a plurality of fin-like structures on a substrate, wherein the fin-like structures may include a plurality of active fin-like structures And a plurality of sacrificial fin structures, and then at least part of the sacrificial fin structures are removed, so that by adding sacrificial fin structures to the desired active fin structure layout, between the fin structures The spacing is the same, or nearly the same, so that the contours of the fin-like structures can be similar. Therefore, the fin-like structures formed in the present invention having similar shapes can promote the process stability and the reliability of the device. Furthermore, the invention is provided with at least one sacrificial fin structure between two active fin structures straddling two adjacent boost transistors in a static random access memory cell, so that (usually with a larger pitch) The spacing between the two active fin structures may be similar to the spacing between other active fin structures (including the spacing between fin structures in other regions such as logic regions).

10: Hard mask layer

12: oxide layer

14: Nitride layer

20, 30: mask

22, 32: Organic dielectric layer

24, 34: Anti-reflective layer with silicon-containing hard mask bottom

26, 36: photoresist

40: Insulation structure

110: base

110’: massive substrate

112, 112a, 112b, 112c, 112d: fin structure

112e, 112f, 112g, 112h, 112h1, 112h2, 112i, 112i1, 112i2, 112j, 112j1, 112j2: active fin structure

112k, 112k’, 112l, 112l’, 112m, 112m’, 112n, 112n’, 112o, 112o’: sacrificial fin structure

112a’, 112b’, 112c’, 112d’: the rest

120: Polysilicon gate

130: interconnection metal

140: contact plug

A: Static random access memory unit area

C1: Cutting the first fin structure

C2: Cutting the second fin structure

E: tail

P, P1, P2, P3, P4: pitch

P1: Etching process

PD1, PD2: step-down piezoelectric crystal

PG1, PG2: channel transistor

PU1, PU2: boost transistor

U1: (1,1,1) type static random access memory unit

U2: (1,2,2) type static random access memory unit

w: width

θ: angle

1-7 are schematic top and cross-sectional views of a method for forming a static random access memory cell array according to an embodiment of the invention.

FIG. 8 is a schematic top and cross-sectional view of a method for forming a static random access memory cell array according to another embodiment of the invention.

1-7 are schematic top and cross-sectional views of a method for forming a static random access memory cell array according to an embodiment of the invention. As shown in FIGS. 1-2, a plurality of fin-shaped structures 112 are formed on a substrate 110 by patterning. As shown in FIG. 1, a block substrate 110' is provided, a hard mask layer 10 is formed thereon, and it is patterned to define the corresponding fin shape to be formed in the block substrate 110' below it Location of structure 112. In this embodiment, the hard mask layer 10 may be a stacked structure of an oxide layer 12 and a nitride layer 14 from bottom to top, but the invention is not limited thereto. Next, as shown in FIG. 2, an etching process P1 is performed to form a fin structure 112 in the bulk substrate 110'. In this way, the fabrication of the fin structure 112 on the substrate 110 is completed. In one embodiment, the hard mask layer 10 can be removed after the fin structure 112 is formed, and a tri-gate MOSFET is formed in the subsequent process. In this way, since there are three direct contact surfaces (including two contact side surfaces and a contact top surface) between the fin structure 112 and the subsequently formed dielectric layer, it is called a tri-gate field effect transistor (tri-gate MOSFET). Compared with the planar field effect transistor, the three-gate field effect transistor can have a wider carrier channel width under the same gate length by using the three direct contact surfaces as a channel for carrier circulation, so that So that the same driving voltage can be doubled to drive current. In another embodiment, the hard mask layer 10 can also be retained, and another multi-gate MOSFET-fin field effect transistor with a fin structure can be formed in the subsequent process ( fin field effect transistor, Fin FET). In the fin field effect transistor, since the hard mask layer 10 is retained, there are only two contact sides between the fin structure 112 and the dielectric layer to be formed later.

In addition, as mentioned above, the present invention can also be applied to other types of semiconductor substrates. For example, in another embodiment, a silicon-clad insulating substrate (not shown) is provided, and the silicon is etched by etching and lithography. The single crystal silicon layer on the insulating substrate (not shown) stops at the oxide layer, and the fabrication of the fin structure on the silicon coating insulating substrate can be completed. In addition, in order to simplify and clearly disclose the present invention, there are 15 fin structures 112 in this embodiment, but the fin structures 112 that can be used in the present invention can also be a plurality of other fin structures 112 that can form static The number of random access memory cell arrays.

As shown in FIGS. 3-6, these fin structures 112 are trimmed to form the required layout of the static random access memory cell array. The method of trimming the fin structure 112 and the layout of the static random access memory cell array depend on the required process requirements and device requirements. In this embodiment, the method of cutting these fin structures 112 includes a first fin structure cut C1 and a second fin structure cut C2, wherein FIGS. 3-4 illustrate the first A fin-shaped structure is cut C1, and FIGS. 5-6 illustrate the second fin-shaped structure cut C2 in this embodiment. The method for forming the fin-shaped structure 112 of the present invention may include forming using the side wall image transfer (SIT) technology, and the first fin-shaped structure cut C1 or/and the second fin-shaped structure cut C2 may be combined with the sidewall image Transfer (Sidewall Image Transfer, SIT) technology. That is to say, the first fin-shaped structure trimming C1 or/and the second fin-shaped structure trimming C2 may be a step in the side wall image transfer (SIT) technology, so the first fin-shaped structure trimming C1 or/ And the second fin-shaped structure cut C2 may include cutting together to define and transfer its image to the substrate 110 to form a side wall of the fin-shaped structure 112.

In detail, as shown in FIG. 3, a mask 20 is sequentially covered and patterned in order to cover the part of the fin structure 112 that does not need to be removed, and exposes a part of the fin structure 112 to be removed . In this embodiment, the covered mask 20 is an organic dielectric layer (ODL) 22 stacked from bottom to top, and a silicon-containing hardmask bottom anti-reflection layer (Silicon-containing Hardmask Bottom anti-reflection coating, SHB) 24 and a photoresist 26. The mask 20 completely exposes a fin-like structure 112a and a fin-like structure 112b at both ends, and only exposes the trailing end E of the fin-like structure 112 between the fin-like structure 112a and the fin-like structure 112b, so it can be solved, for example The side wall image transfer (Sidewall Image Transfer, SIT) technology in the connection of the fin structure and line-end shortening (line-end shortening) and other issues. Next, the first fin-shaped structure is cut C1 to completely remove the exposed fin-shaped structure 112a and fin-shaped structure 112b, and the fin-shaped junction As shown in FIG. 4, the trailing end E of the fin structure 112 between the structure 112a and the fin structure 112b, the dotted line is the cutting range of the first fin structure cutting C1. After trimming, the fin-shaped structure 112a and the fin-shaped structure 112b may still retain the remaining portion 112a'/112b', and the trailing end E of the fin-shaped structure 112 between the fin-shaped structure 112a and the fin-shaped structure 112b also remains the remaining portion (Not shown), wherein the remaining portion 112a'/112b' protrudes from the base 110 between the fin structures 112. The first fin-shaped structure cutting C1 can be multi-directional cutting, or only cutting in a first direction. In this embodiment, the first fin structure cut C1 is roughly cut in the y direction, and the x direction cut is selectively added to remove the fin structure 112a and the fin structure 112b, but the invention is not limited to this . In other embodiments, the first fin-shaped structure cut C1 can only be cut along the y direction, while retaining the fin-shaped structure 112a and the fin-shaped structure 112b. After the first fin-shaped structure is cut C1, the photoresist 26, the silicon-containing hard mask bottom anti-reflection layer 24, and the organic dielectric layer 22 are then removed.

Next, the second fin-shaped structure is cut C2. As shown in FIG. 5, a mask 30 is sequentially covered and patterned in order to cover the part of the fin structure 112 that does not need to be removed, and exposes a part of the fin structure 112 to be removed. In this embodiment, the covered mask 30 is an organic dielectric layer (ODL) 32 stacked from bottom to top, and a silicon-based hard mask (SHB) 34与一个光刻36。 And a photoresist 36. The mask 30 completely exposes a fin structure 112c and a fin structure 112d at the edge. Next, the second fin-shaped structure is cut C2, and the exposed fin-shaped structure 112c and the fin-shaped structure 112d are removed. As shown in FIG. 6, the dotted line is the cutting range of the second fin-shaped structure C2. After cutting, the fin-shaped structure 112c and the fin-shaped structure 112d may still retain the remaining portion 112c'/112d', wherein the remaining portion 112c'/112d' will also protrude from the base 110 between the fin-shaped structures 112. In this embodiment, the second fin-shaped structure cut C2 is cut along a second direction, that is, the x-direction cut, and the first fin-shaped structure cut C1 is cut perpendicular to the second fin-shaped structure in the first direction C2 is cut in the second direction, but the invention is not limited to this. After the second fin-shaped structure is cut C2, the photoresist 36, the silicon-containing hard mask bottom anti-reflection layer 34, and the organic dielectric layer 32 can be removed immediately. In this embodiment, the hard mask layer 10 is removed immediately.

Two embodiments are proposed below to form two static random access memory cell arrays, respectively. Figure 7 is a (1,1,1) type static random access memory cell array, that is, each channel transistor (PG FinFET) in the static random access memory cell array and the corresponding one buck piezoelectric crystal ( PD FinFET) share a single active fin structure. Figure 8 is another (1,2,2) type static random access memory cell array, that is, each channel transistor (PG FinFET) in the static random access memory cell array and the corresponding one piezoelectric crystal (PD FinFET) shares two active fin structures. In addition, the present invention can also be applied to other types of static random access memory cell arrays, or other devices with fin structures.

Next, after completing the second fin structure trimming step C2 of FIG. 6, part of the fin structure 112 is removed to form a fin structure for straddling the transistor group of the static random access memory cell array The layout is shown in Figure 7. Furthermore, as shown in FIG. 6, the fin structure 112 may include a plurality of active fin structures 112e/112f/112g/112h/112i/112j and a plurality of sacrificial fin structures 112k'/112l'/112m '/112n'/112o', the present invention removes at least a part of the sacrificial fin structure 112k'/112l'/112m'/112n'/112o' to obtain the desired fin structure layout and form the same shape Fin structure. In detail, in this embodiment, after removing part of the sacrificial fin structure 112k'/112l'/112m'/112n'/112o', five sacrificial fin structures 112k/112l/112m/112n/112o are formed, wherein The sacrificial fin structure 112k/112l/112m/112n/112o will protrude from the base 110 between the fin structures 112, as shown in the left figure of FIG. 7, but the invention is not limited thereto. In this way, the distribution of the active fin structures 112e/112f/112g/112h can form one (1,1,1) type static random access memory unit U1 shown in the right figure of FIG. 7. Furthermore, the active fin structures 112i/112j are located on both sides of the static random access memory unit U1 of (1,1,1) type respectively. The two active fin structures 112i/112j can be used as other static random storage, for example Take the active fin structure in the memory unit. Five sacrificial fin structures 112k/112l/112m/112n/112o are located in each active fin structure 112e/112f/112g/112h/112i/112j. In this embodiment, according to the distance between the active fins 112e/112f/112g/112h/112i/112j, the sacrificial fins are respectively arranged between the active fins 112e/112f/112g/112h/112i/112j The structures 112k/112l/112m/112n/112o, so that the distance between the fin structures 112 is the same as each other and the distance between the fin structures in other regions is the same, but the invention is not limited thereto. For example, in general, the distance between the active fin structures in the logic area is smaller than the distance between the active fin structures in the static random access memory unit U1, so the present invention in the static random access memory unit U1 A sacrificial fin structure 112k/112l/112m/112n/112o is added between each active fin structure 112e/112f/112g/112h/112i/112j to enable each fin structure 112 in the static random access memory unit U1 The distance between them is equal to or close to the distance between the active fin structures in the logic area.

Therefore, the spirit of the present invention is to add at least one sacrificial fin-like structure between the active fin-like structures, so that the fin-like structures in the same area or different areas are close to each other, or even reach the same, so that the fins formed The width, contour or shape of the structure are similar, which can improve the stability of the process and the reliability of the device. Because, when the width of the fin structure is different, it will affect the performance of the formed static random access memory; when the shape of the fin structure is different, it will affect the stability of the process. Furthermore, a maximum pitch in each fin structure is bound to be less than twice the minimum pitch in each fin structure (otherwise, a sacrificial fin structure can be added between the maximum pitch). Furthermore, the illustration of this embodiment only shows the static random access memory unit area A, and the static random access memory unit U1 is located in the static random access memory unit area A, but the substrate 110 may further include a Logic area, and the pitch of each fin structure 112 in the static random access memory cell area A is preferably less than twice the pitch of the fin structure in the logic area (otherwise, when in the static random access memory (When the pitch of the fin structures 112 in the cell area A is greater than or equal to twice the pitch of the fin structures in the logic area, at least one sacrificial fin structure can be added between the pitches of the fin structures 112) , So that the fin structure in the static random access memory unit area U1 The width, shape, and outline of 112 are the same as, or approximately the same as, those of the fin structure in the logic area.

The static random access memory unit U1 of (1,1,1) type includes two boost transistors (PU FinFET) PU1, two channel transistors (PG FinFET) PG1, and two step-down piezoelectric crystals (PD FinFET) PD1. In the static random access memory unit U1 of the (1,1,1) type, each channel transistor PG1 shares a single active fin structure 112h/112g with two corresponding booster transistors, and two adjacent boost transistors A single sacrificial fin structure 112k is provided between the two active fin structures 112e/112f spanned by PU1. In a preferred embodiment, the pitch P between the fin structures 112 is equal. Similarly, the single active fin structure 112h/112g shared by each channel transistor PG1 and the corresponding one buck piezoelectric crystal PD1 and the two boost transistors PU1 closest to the single active fin structure 112h/112g span the active The sacrificial fin structures 112l/112m are respectively arranged between the fin structures 112f/112e; between the shared active fin structures in two adjacent memory cells, which means between the active fin structures 112h/112j and the active fins The sacrificial fin-like structures 112o/112n are respectively arranged between the 112g/112i-like structures.

It is emphasized here that the pitch P between the fin structures 112 will directly affect the width w and shape of the fin structures 112 formed. Specifically, the greater the pitch P between the fin structures 112, the greater the slope of the cross-sectional profile of the formed fin structures 112, which means the greater the angle θ; The smaller the pitch P, the steeper the cross-sectional profile of the formed fin structure 112, which means the smaller the angle θ. Therefore, when the pitch P between the fin structures 112 is different, the width of each formed fin structure 112 and the inclination of the cross-sectional profile are different. When the width and cross-sectional profile of each fin-shaped structure 112 are not uniform, performance such as process stability and reliability of the formed device will be deteriorated. In this embodiment, the sacrificial fin structures 112k/112l/112m/112n/112o are supplemented between the active fin structures 112e/112f/112g/112h/112i/112j to adjust between the fin structures 112 The distance P, so that each fin structure The distance P between 112 and the distance between the fin structures of other regions (such as logic regions) are as close as possible. In this embodiment, only a single sacrificial fin structure 112k/112l/112m/112n/112o is filled between the active fin structures 112e/112f/112g/112h/112i/112j, but the present invention does not take this as limit. In the present invention, sacrificial fin structures 112k/112l/112m/112n/112o can be selectively supplemented between active fin structures 112e/112f/112g/112h/112i/112j, or two adjacent active fin structures Fill two or more sacrificial fin structures 112k/112l/112m/112n/112o between 112e/112f/112g/112h/112i/112j, depending on the distance P between each fin structure 112 and the relative The spacing between fin structures depends.

Furthermore, the (1,1,1) type static random access memory unit U1 may further include a polysilicon gate 120 spanning the fin structure 112, and the interconnection metal 130 connects each transistor including a channel transistor PG1, step-down crystal PD1 and step-up transistor PU1, and the contact plug 140 are physically connected to the polysilicon gate 120 and the interconnect metal 130. The structure and operation method of the static random access memory unit U1 of type (1,1,1) are well known in the art, so they will not be described in detail.

In addition, the present invention can also be applied to a (1,2,2) type static random access memory cell array, as shown in FIG. 8. The difference between (1,2,2) type static random access memory unit U2 and (1,1,1) type static random access memory unit U1 is: (1,1,1) type static random The active fin structure 112h in the access memory unit U1 is replaced by two active fin structures 112h1/112h2, and the (1,2,2) type static random access memory unit U2 has a channel transistor (PG FinFET) PG2 shares the two active fin structures 112h1/112h2 with the corresponding PD FinFET PD2; the active fin structure in the (1,1,1) type static random access memory unit U1 112g is replaced by two active fin structures 112g1/112g2, and another channel transistor (PG FinFET) PG2 in the (1,2,2) type static random access memory unit U2 and a corresponding buck piezoelectric crystal (PD FinFET) PD2 shares the two active fin structures 112g1/112g2. (1,1,1) The active fin structure 112i on the side of the static random access memory unit U1 is replaced with two active fin structures 112i1/112i2, and the side of the (1,1,1) type static random access memory unit U1 The active fin structure 112j is replaced by two active fin structures 112j1/112j2. A single sacrificial fin structure 112k is still disposed between the two active fin structures 112e/112f across two adjacent boost transistors PU2.

Because the pitch P1 between the two active fin structures 112h1/112h2, the pitch P2 between the two active fin structures 112i1/112i2, and the pitch P3 between the two active fin structures 112j1/112j2 are smaller than other fin structures There is no P4 between the two active fin structures 112h1/112h2, between the two active fin structures 112i1/112i2, and between the two active fin structures 112j1/112j2 In addition, sacrificial fin structures 112k/112l/112m/112n/112o are provided between other fin structures 112. Therefore, in this embodiment, the spacing between the fin structures 112 can be adjusted so that the spacing between the fin structures 112 is as uniform as possible. In this way, each of the formed fin structures 112 can have the same width and shape, which can promote the reliability of the manufacturing process and further improve the performance of the static random access memory.

In addition, active fin structures 112e/112f/112g(112g1/112g2)/112h(112h1/112h2)/112i(112i1/112i2)/112j(112j1/112j2) and sacrificial fin structures 112k/112l/112m/ After 112n/112o, an insulating structure 40 can be formed between the active fin structures 112e/112f/112g(112g1/112g2)/112h(112h1/112h2)/112i(112i1/112i2)/112j(112j1/112j2), where Active fin structure 112e/112f/112g(112g1/112g2)/112h(112h1/112h2)/112i(112i1/112i2)/112j(112j1/112j2) protruding the insulating structure 40, but the insulating structure 40 covers all the sacrificial fins Structure 112k/112l/112m/112n/112o.

In summary, the present invention proposes a static random access memory cell array and its formation A method of patterning a plurality of fin-like structures on a substrate, wherein the fin-like structures may include a plurality of active fin-like structures and a plurality of sacrificial fin-like structures, and then at least part of the sacrificial fins are removed In this way, the sacrificial fin structure can be added to the desired active fin structure layout so that the spacing between the fin structures is the same, or nearly the same, so that the width of each fin structure can be Same shape. The fin structures with the same width and shape formed by the invention can promote the stability of the manufacturing process and the reliability of the device.

In detail, each static random access memory in the static random access memory cell array formed by the present invention includes two boost transistors, two channel transistors, and two drop piezoelectric crystals. Each channel transistor (PG FinFET) and the corresponding one of the reduced piezoelectric crystal (PD FinFET) share at least an active fin structure, for example, the present invention can form a (1,1,1) type static random access memory unit Array, each channel transistor and the corresponding step-down crystal only share a single active fin structure, or the invention can form a (1,2,2) type static random access memory cell array, each channel The crystal and the corresponding voltage-reducing crystal share only two active fin structures. It is emphasized here that the present invention is provided with at least one sacrificial fin structure between two active fin structures straddling two adjacent boost transistors in a static random access memory cell, so that (usually having a larger The spacing between the two active fin structures can be similar to the spacing between other active fin structures in the static random access memory unit, or between the fin structures in other regions (such as logic regions) spacing. According to the method of the present invention, a maximum pitch in each fin structure is bound to be less than twice the minimum pitch in each fin structure (otherwise, a sacrificial fin structure can be added between the maximum pitch). The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

40: Insulation structure

110: base

112e, 112f, 112g, 112h, 112i, 112j: active fin structure

112k, 112l, 112m, 112n, 112o: sacrificial fin structure

112a’, 112b’, 112c’, 112d’: the rest

120: Polysilicon gate

130: interconnection metal

140: contact plug

A: Static random access memory unit area

P: pitch

PD1: step-down piezoelectric crystal

PG1: channel transistor

PU1: Boost transistor

U1: (1,1,1) type static random access memory unit

w: width

θ: angle

Claims (19)

A method for forming a static random-access memory (SRAM) cell array includes: patterning to form a plurality of fin structures on a substrate, wherein the fin structures include a plurality of active fins Structure and a plurality of sacrificial fin structures, each channel transistor (PG FinFET) and the corresponding one of the reduced piezoelectric crystals (PD FinFET) share at least one active fin structure, two adjacent lifts in a memory cell At least one sacrificial fin structure is disposed between the two active fin structures spanned by a piezoelectric crystal (PU FinFET); at least a part of the sacrificial fin structures is removed; and the sacrificial fins are removed Before at least a part of the fin-like structure, the fin-like structures are cut. The method for forming a static random access memory cell array as described in item 1 of the patent scope, wherein each of the static random access memory includes two boost transistors, two channel transistors and two step-down piezoelectric crystals. The method for forming a static random access memory cell array as described in item 1 of the scope of the patent application further includes: at least one of the sacrificial fin structures is disposed in the shared active fin structure and the closest shared active fin structure One of the two booster transistors (PU FinFET) of the structure spans between the two active fin structures. The method for forming a static random access memory cell array as described in item 1 of the patent scope further includes: at least one of the sacrificial fin structures is disposed in the shared active fin junction in two adjacent memory cells Between the structure. The method for forming a static random access memory cell array as described in item 1 of the patent application scope, wherein the method of cutting the fin structures includes a first fin structure cutting and a second fin structure cutting , Wherein the first fin-shaped structure is cut in a first direction, and the second fin-shaped structure is cut in a second direction. The method for forming a static random access memory cell array as described in item 5 of the patent application scope, wherein the first direction cut is perpendicular to the second direction cut. The method for forming a static random access memory cell array as described in item 6 of the patent application scope, wherein the cutting of the first fin-shaped structure includes cutting the tail ends of the fin-shaped structures, and the second fin-shaped structure Cutting includes removing the edge-like fin structures among the fin-like structures. The method for forming an array of static random access memory cells as described in item 1 of the patent scope, wherein a maximum pitch of the fin structures is less than twice a minimum pitch of the fin structures. The method for forming a static random access memory cell array as described in item 1 of the patent scope, wherein the substrate includes a static random access memory cell area, and the static random access memory cells are located in the static random In the access memory cell area, and a logic area, wherein the pitch of the fin structures in the static random access memory cell area is less than twice the pitch of the fin structures in the logic area . Static random-access memory (SRAM) unit The array includes: a plurality of fin-like structures on a substrate, the fin-like structures including a plurality of active fin-like structures and a plurality of remaining sacrificial fin-like structures shorter than the active fin-like structures, wherein each channel The transistor (PG FinFET) and the corresponding one of the reduced piezoelectric crystal (PD FinFET) share at least one active fin structure, and two adjacent boost transistors (PU FinFET) across the two in a memory cell At least one remaining sacrificial fin structure is disposed between the active fin structures. The static random access memory cell array as described in item 10 of the patent application scope, wherein each of the static random access memories includes two boost transistors, two channel transistors and two drop piezoelectric crystals. The static random access memory cell array as described in item 10 of the patent scope further includes: at least one of the remaining sacrificial fin structures is disposed in the shared active fin structure and the closest shared active fin structure One of the two booster transistors (PU FinFET) of the structure spans between the two active fin structures. The static random access memory cell array as described in item 10 of the patent application scope further includes: at least one of the remaining sacrificial fin structures is disposed in the shared active fin structure in two adjacent memory cells between. The static random access memory cell array as described in item 10 of the patent application scope further includes: A plurality of insulating structures are located between the active fin structures and cover all the remaining sacrificial fin structures. The static random access memory cell array as described in item 10 of the patent application range, wherein a maximum pitch of the fin structures is less than twice a minimum pitch of the fin structures. The static random access memory cell array as described in item 10 of the patent scope, wherein the substrate includes a static random access memory cell area, and the static random access memory cells are located in the static random access memory In the body cell area, and a logic area, wherein the pitch of the fin structures in the static random access memory cell area is less than twice the pitch of the fin structures in the logic area. The static random access memory cell array as described in item 16 of the patent application range, wherein the contours of the fin-shaped structures in the static random access memory cell area and the fin-shaped structures in the logic area The outline of the structure is the same. The static random access memory cell array as described in item 10 of the patent application scope, wherein each of the channel transistor (PG FinFET) and the corresponding reduced piezoelectric crystal (PD FinFET) share only one active fin structure. The static random access memory cell array as described in item 10 of the patent application scope, wherein each of the channel transistor (PG FinFET) and the corresponding reduced piezoelectric crystal (PD FinFET) share only two active fin structures.

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