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TWI686879B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI686879B
TWI686879B TW105113924A TW105113924A TWI686879B TW I686879 B TWI686879 B TW I686879B TW 105113924 A TW105113924 A TW 105113924A TW 105113924 A TW105113924 A TW 105113924A TW I686879 B TWI686879 B TW I686879B
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TW201740475A (zh
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許智凱
洪裕祥
程偉麒
傅思逸
鄭志祥
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聯華電子股份有限公司
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Priority to TW105113924A priority Critical patent/TWI686879B/zh
Priority to US15/170,954 priority patent/US10566285B2/en
Publication of TW201740475A publication Critical patent/TW201740475A/zh
Priority to US16/732,336 priority patent/US10978398B2/en
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
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    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，然後形成一閘極結構於基底上。接著形成一凹槽於閘極結構旁，形成一磊晶層於凹槽內，形成一層間介電層於閘極結構上，形成一第一接觸洞於層間介電層中且位於閘極結構旁，最後再形成一遮蓋層於第一接觸洞內，其中遮蓋層之上表面切齊或低於基底之上表面。

Description

半導體元件及其製作方法
本發明關於一種製作半導體元件的方法，尤指一種形成接觸洞後於接觸洞中形成遮蓋層的方法。
為了能增加半導體結構的載子遷移率，可以選擇對於閘極通道施加壓縮應力或是伸張應力。舉例來說，若需要施加的是壓縮應力，習知技術常利用選擇性磊晶成長(selective epitaxial growth,SEG)技術於一矽基底內形成晶格排列與該矽基底相同之磊晶結構，例如矽鍺(silicon germanium,SiGe)磊晶結構。利用矽鍺磊晶結構之晶格常數(lattice constant)大於該矽基底晶格之特點，對P型金氧半導體電晶體的通道區產生應力，增加通道區的載子遷移率(carrier mobility)，並藉以增加金氧半導體電晶體的速度。反之，若是N型半導體電晶體則可選擇於矽基底內形成矽碳(silicon carbide,SiC)磊晶結構，對閘極通道區 產生伸張應力。
現今以磊晶成長方式形成具有磊晶層的MOS電晶體過程中通常會先於成長完磊晶層之後再去除部分層間介電層形成接觸洞，然後填入金屬材料形成接觸插塞。然而，此製程順序容易損害已成長的磊晶層表面並影響元件運作。因此，如何改良現有製程技術以解決現有瓶頸即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，然後形成一閘極結構於基底上。接著形成一凹槽於閘極結構旁，形成一磊晶層於凹槽內，形成一層間介電層於閘極結構上，形成一第一接觸洞於層間介電層中且位於閘極結構旁，最後再形成一遮蓋層於第一接觸洞內，其中遮蓋層之上表面切齊或低於基底之上表面。
本發明另一實施例揭露一種半導體元件，包含：一基底；一閘極結構設於基底上；一磊晶層設於閘極結構旁之基底中；以及一遮蓋層設於磊晶層上，其中遮蓋層之上表面切齊或低於基底之上表面。
12:基底
14:閘極結構
16:閘極結構
18:閘極介電層
20:閘極材料層
22:硬遮罩
24:側壁子
26:輕摻雜汲極
28:緩衝層
30:磊晶層
32:V型輪廓
34:差排缺陷
36:高介電常數介電層
38:功函數金屬層
40:低阻抗金屬層
42:硬遮罩
44:接觸洞蝕刻停止層
46:層間介電層
48:接觸洞
50:遮蓋層
52:圖案化光阻
54:接觸洞
56:金屬矽化物
58:接觸插塞
60:接觸插塞
62:第一金屬層
64:第二金屬層
66:第三金屬層
68:倒V型輪廓
70:V型輪廓
第1圖至第6圖為本發明較佳實施例製作一半導體元件之方法示意圖。
第7圖為本發明一實施例之半導體元件之結構示意圖。
第8圖為本發明一實施例之半導體元件之結構示意圖。
請參照第1圖至第6圖，第1圖至第6圖為本發明較佳實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，然後於基底上形成閘極結構14、16。在本實施例中，形成閘極結構14、16的方式較佳依序形成一閘極介電層、一閘極材料層以及一硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分硬遮罩、部分閘極材料層以及部分閘極介電層，然後剝除圖案化光阻，以於基底12上形成至少由圖案化之閘極介電層18、圖案化之閘極材料層20以及圖案化之硬遮罩22所構成的閘極結構14、16。
需注意的是，為了凸顯後續於閘極結構14、16之間形成磊晶層的相關步驟，本實施例主要以基底12上形成兩個閘極結構14、16為例，並僅繪示兩個閘極結構14、16的部分結構與兩個閘極結構14、16之間的區域。
在本實施例中，基底12例如是矽基底、磊晶矽基底、碳化矽基底或矽覆絕緣(silicon-on-insulator,SOI)基底等之半導體基底，但不以此為限。閘極介電層18可包含二氧化矽(SiO2)、氮化矽(SiN)或高介電常數(high dielectric constant,high-k)材料；閘極材料層20可包含金屬材料、多晶矽或金屬矽化物(silicide)等導電材料；硬遮罩22可選自由 氧化矽、氮化矽、碳化矽(SiC)以及氮氧化矽(SiON)所構成的群組，但不侷限於此。
此外，在一實施例中，還可選擇預先在基底12中形成複數個摻雜井(未繪示)或複數個作為電性隔離之用的淺溝渠隔離(shallow trench isolation,STI)。並且，本實施例雖以平面型電晶體為例，但在其他變化實施例中，本發明之半導體製程亦可應用於非平面電晶體，例如是鰭狀電晶體(Fin-FET)，此時，第1圖所標示之基底12即相對應代表為形成於一基底12上的鰭狀結構。
然後在閘極結構14、16側壁形成至少一側壁子24，並選擇性進行一輕摻雜離子佈植，利用約930℃溫度進行一快速升溫退火製程活化植入基底12的摻質，以於側壁子24兩側的基底12中形成一輕摻雜汲極26。在本實施例中，側壁子24可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子(圖未示)以及一主側壁子(圖未示)，偏位側壁子與主側壁子較佳包含不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組，但不侷限於此。
如第2圖所示，隨後進行一乾蝕刻及/或濕蝕刻製程，利用閘極結構14、16與側壁子24作為蝕刻遮罩，沿著側壁子24向下單次或多次蝕刻基底12，以於閘極結構14、16兩側的基底12中形成一凹槽(圖未示)。
接著依序形成一緩衝層28以及一磊晶層30於凹槽內，其中緩 衝層28較佳覆蓋凹槽表面且較佳具有均一厚度。磊晶層30則填滿大部分凹槽，且磊晶層30中可利用現場摻雜或另外以離子佈植植入摻質而形成一源極/汲極區域。其中所填入的磊晶層30上表面包含一V型輪廓32，且V型輪廓32略低於基底12上表面。在本實施例中，緩衝層28及磊晶層30均較佳包含磷化矽(SiP)，其中磊晶層30的磷濃度較佳高於緩衝層28的磷濃度。依據本發明一實施例，緩衝層28與磊晶層30又可依據電晶體的型態包含鍺化矽，此實施例也屬本發明所涵蓋的範圍。另外在本實施例中，在利用選擇性磊晶成長製程形成磊晶層30的同時可能會伴隨形成差排缺陷34於磊晶層30內，且差排缺陷34較佳完全鑲嵌於磊晶層30內。更具體而言，差排缺陷34本身可呈現一V型輪廓，且差排缺陷34的二頂點與一谷點均低於基底12表面。
隨後如第2圖所示，進行一金屬閘極置換製程將閘極結構14、16轉換為金屬閘極。例如可先形成一層間介電層(圖未示)完全覆蓋閘極結構14、16，接著進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing,CMP)去除部分層間介電層暴露硬遮罩22表面，並再以蝕刻去除硬遮罩22暴露出由多晶矽所構成的閘極材料層20。
然後進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除閘極結構14、16中的閘極材料層20，以於層間介電層中形成一凹槽(圖未示)。之後依序形成一高介電常數介電層36以及至少包含U型功函數金屬層38與低阻抗金屬層40的 導電層於凹槽內，並再搭配進行一平坦化製程使U型高介電常數介電層36、U型功函數金屬層38與低阻抗金屬層40的表面與層間介電層表面齊平。
在本實施例中，高介電常數介電層36包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide,SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
功函數金屬層38較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層38可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層38可選用功函數為4.8eV~5.2eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層38與低阻抗金屬層40之間可包含另一阻障層(圖未示)，其中 阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層40則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。
接著可去除部分高介電常數介電層36、部分功函數金屬層38與部分低阻抗金屬層40形成凹槽(圖未示)，並填入一硬遮罩42於凹槽內並使硬遮罩42與層間介電層表面齊平，其中硬遮罩42可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。然後可完全去除設於閘極結構周圍的層間介電層並同時去除差排缺陷34，沉積一由氮化矽所構成的接觸洞蝕刻停止層(contact etch stop layer,CESL)44於閘極結構14、16上與磊晶層30表面，並再形成另一層間介電層46於接觸洞蝕刻停止層44上。
接著如第3圖所示，進行一微影暨蝕刻製程，去除閘極結構14、16之間的部分層間介電層46、部分接觸洞蝕刻停止層44與部分磊晶層30，以形成一接觸洞48於閘極結構4、16之間的層間介電層46中並暴露出部分磊晶層30。
此外依據本發明一實施例，也可以在形成磊晶層30之後，就直接形成接觸洞蝕刻停止層(CESL)與下層間介電層，然後進行金屬閘極置換製程，接著再形成另一上層間介電層46於下層間介電層之上，進行微影暨蝕刻製程，以形成接觸洞48並暴露出部分磊晶層30，此實 施例也屬本發明所涵蓋的範圍。
如第4圖所示，然後形成一遮蓋層50於接觸洞48內，其中遮蓋層50之上表面較佳切齊基底12上表面或低於基底12上表面。在本實施例中，緩衝層28、磊晶層30以及遮蓋層50均較佳包含磷化矽(SiP)，其中遮蓋層50的磷濃度較佳高於磊晶層30的磷濃度，同時磊晶層30的磷濃度也較佳高於緩衝層28的磷濃度。另外依據本發明一實施例，若遮蓋層50、磊晶層30與緩衝層28均由鍺化矽所構成，遮蓋層50中鍺於鍺化矽中所佔據的組成百分比以及/或例如硼等摻雜於鍺化矽中所佔據的濃度比例均較佳大於磊晶層30中鍺所佔據的組成百分比以及/或硼等摻雜所佔據的濃度比例。
隨後如第5圖所示，再形成一圖案化遮罩，例如一圖案化光阻52填滿接觸洞48但暴露閘極結構14、16正上方的部分區域，然後利用圖案化光阻52為遮罩進行一蝕刻製程，去除閘極結構14、16正上方的部分層間介電層46、部分接觸洞蝕刻停止層44及部分硬遮罩42，以於閘極結構14、16上分別形成一接觸洞54暴露出部分閘極結構14、16中的金屬材料。
之後如第6圖所示，先去除圖案化光阻52，再接著進行一接觸插塞製程搭配金屬矽化物製程形成一金屬矽化物56於接觸洞48中，並分別形成接觸插塞58電連接並接觸閘極結構14、16與接觸插塞60電連接並接觸閘極結構14、16之間的磊晶層30或源極/汲極區域。在本實施例中，接觸插塞製程可依序沉積一第一金屬層62與第二金屬層64於 接觸洞中，其中第一金屬層62與第二金屬層64較佳共形地(conformally)形成於遮蓋層50表面及接觸洞48、54的內側側壁。在本實施例中，第一金屬層62較佳選自鈦、鈷、鎳及鉑等所構成的群組，且最佳為鈦，第二金屬層64則較佳包含氮化鈦、氮化鉭等金屬化合物。
在連續沉積第一金屬層62與第二金屬層64之後，依序進行一第一熱處理製程與一第二熱處理製程以形成金屬矽化物56於遮蓋層50上。在本實施例中，第一熱處理製程包含一常溫退火(soak anneal)製程，其溫度較佳介於500℃至600℃，且最佳為550℃，而其處理時間則較佳介於10秒至60秒，且最佳為30秒。第二熱處理製程包含一峰值退火(spike anneal)製程，其溫度較佳介於600℃至950℃，且最佳為600℃，而其處理較佳時間則較佳介於100毫秒至5秒，且最佳為5秒。
迨進行兩次熱處理製程後，形成一第三金屬層66並填滿接觸洞48、54。在本實施例中，第三金屬層66較佳包含鎢，但不侷限於此。最後進行一平坦化製程，例如以CMP製程部分去除第三金屬層66、部分第二金屬層64及部分第一金屬層62，甚至可視製程需求接著去除部分層間介電層46，以形成接觸插塞58、60電連接閘極結構14、16與磊晶層30。至此即完成本發明較佳實施例一半導體元件的製作。
請繼續參照第7圖，第7圖為本發明另一實施例之半導體元件之結構示意圖。如第7圖所示，相較於第6圖中遮蓋層50上表面切齊或低於基底12上表面，本實施例的遮蓋層50上表面較佳包含一向上突起的倒V型輪廓68，其中倒V型輪廓68的頂點較佳切齊或略低於基底12 表面。從另一角度來看，由於遮蓋層50上表面具有倒V型輪廓68，因此設於其上的金屬矽化物56上表面與下表面均同時具有倒V型輪廓。
請繼續參照第8圖，第8圖為本發明另一實施例之半導體元件之結構示意圖。如第8圖所示，本實施例的遮蓋層50上表面較佳包含一向下凹入的V型輪廓70，其中V型輪廓70的二頂點較佳切齊或略低於基底12表面。從另一角度來看，由於遮蓋層50上表面具有V型輪廓70，因此設於其上的金屬矽化物56上表面與下表面均同時具有V型輪廓。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底
24:側壁子
26:輕摻雜汲極
28:緩衝層
30:磊晶層
36:高介電常數介電層
38:功函數金屬層
40:低阻抗金屬層
42:硬遮罩
44:接觸洞蝕刻停止層
46:層間介電層
50:遮蓋層
56:金屬矽化物
58:接觸插塞
60:接觸插塞
62:第一金屬層
64:第二金屬層
66:第三金屬層

Claims (20)

  1. 一種製作半導體元件的方法，包含：提供一基底；形成一閘極結構於該基底上；形成一磊晶層於該閘極結構旁，其中該磊晶層的一上表面自該基底的一上表面凹入並且具有一V型輪廓；形成一層間介電層於該閘極結構上；形成一第一接觸洞於該層間介電層中且位於該閘極結構旁；以及形成一遮蓋層於該第一接觸洞內，其中該遮蓋層之上表面切齊或低於該基底之上表面。
  2. 如申請專利範圍第1項所述之方法，另包含：形成一金屬層於該遮蓋層上並填滿該第一接觸洞；以及平坦化該金屬層以形成一第一接觸插塞。
  3. 如申請專利範圍第2項所述之方法，另包含形成一金屬矽化物於該第一接觸插塞及該遮蓋層之間。
  4. 如申請專利範圍第1項所述之方法，另包含：形成一第二接觸洞於該層間介電層中並暴露該閘極結構；形成一金屬層於該第二接觸洞內；以及平坦化該金屬層以形成一第二接觸插塞。
  5. 如申請專利範圍第1項所述之方法，另包含：形成一接觸洞蝕刻停止層於該閘極結構及該基底上；形成該層間介電層；以及去除部分該層間介電層及部分該接觸洞蝕刻停止層以形成該第一接觸洞。
  6. 如申請專利範圍第1項所述之方法，其中該遮蓋層及該磊晶層包含相同材料。
  7. 如申請專利範圍第6項所述之方法，其中該遮蓋層之摻質濃度大於該磊晶層之摻質濃度。
  8. 如申請專利範圍第1項所述之方法，另包含於形成該磊晶層之前形成一緩衝層。
  9. 如申請專利範圍第8項所述之方法，其中該緩衝層、該磊晶層及該遮蓋層包含相同材料。
  10. 如申請專利範圍第1項所述之方法，其中該遮蓋層之上表面包含一倒V型輪廓。
  11. 如申請專利範圍第1項所述之方法，其中該遮蓋層之上表面包含一V型輪廓。
  12. 一種半導體元件，包含：一基底；一閘極結構設於該基底上；一磊晶層設於該閘極結構旁之該基底中，其中該磊晶層的一上表面自該基底的一上表面凹入並且具有一V型輪廓；以及一遮蓋層設於該磊晶層上並且位於該V型輪廓的一谷點上，其中該遮蓋層之上表面切齊或低於該基底之上表面。
  13. 如申請專利範圍第12項所述之半導體元件，另包含：一層間介電層設於該閘極結構上；以及一第一接觸插塞設於該層間介電層中並接觸該遮蓋層。
  14. 如申請專利範圍第13項所述之半導體元件，另包含一第二接觸插塞設於該層間介電層中並接觸該閘極結構。
  15. 如申請專利範圍第12項所述之半導體元件，另包含一緩衝層設於該磊晶層及該基底之間。
  16. 如申請專利範圍第15項所述之半導體元件，另包含一接觸洞蝕刻停止層設於該閘極結構上並接觸該緩衝層及該磊晶層。
  17. 如申請專利範圍第15項所述之半導體元件，其中該緩衝層、該磊晶層及該遮蓋層包含相同材料。
  18. 如申請專利範圍第17項所述之半導體元件，其中該遮蓋層之摻質濃度高於該磊晶層之摻質濃度。
  19. 如申請專利範圍第12項所述之半導體元件，其中該遮蓋層之上表面包含一倒V型輪廓。
  20. 如申請專利範圍第12項所述之半導體元件，其中該遮蓋層之上表面包含一V型輪廓。
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