TWI681629B - Buffer circuit - Google Patents

Abstract

A buffer circuit including a switching circuit and an operational amplifier (OPA) circuit is provided. The switching circuit is coupled between an input terminal of the buffer circuit and a node and receives an input voltage signal from the input terminal. A non-inverting input terminal of the OPA circuit is coupled to the node. An output terminal of the OPA circuit is coupled to an inverting input terminal of the OPA circuit and outputs an output voltage signal. After a first time interval when the input voltage signal begins transition, the switching circuit is switched from an on state to an off state, such that the OPA circuit operates in an over driving mode to increase a transition amplitude of the output voltage signal.

Description

Buffer circuit

The present invention relates to a buffer circuit, and particularly to a buffer circuit with an overdrive function.

The buffer circuit is a basic circuit with wide application. For example, in the driving circuit of the liquid crystal display, the output buffer circuit can charge and discharge the load (that is, the parasitic capacitance of the data line and the liquid crystal capacitance) according to the analog signal output by the digital-to-analog converter of the previous stage to drive the liquid crystal The corresponding pixel unit on the display. However, as the size and resolution of LCDs increase, the amount of data that the drive circuit of the LCD needs to output per unit time is increasing, and the parasitic capacitance on the data line increases with the size and resolution of the panel, so the output The driving capacity of the buffer circuit needs to be increased accordingly to ensure that the liquid crystal capacitor can be charged to the ideal voltage level. Therefore, how to improve the driving capability of the buffer circuit is one of the important issues facing those skilled in the art.

In view of this, the present invention provides a buffer circuit with an overdrive function Circuit, when the input voltage signal transitions, it can increase the transition amplitude of its output voltage signal to improve the driving capacity of the buffer circuit.

The buffer circuit of the present invention includes a switching circuit and an operational amplifier circuit. The switch circuit is coupled between the input end of the buffer circuit and a node for receiving the input voltage signal from the input end. The non-inverting input terminal of the operational amplifier circuit is coupled to the aforementioned node. The output terminal of the operational amplifier circuit is coupled to the inverting input terminal of the operational amplifier circuit and outputs an output voltage signal. After the first period of time when the input voltage signal starts to transition, the switch circuit is switched from the on state to the off state, causing the operational amplifier circuit to operate in the overdrive mode to increase the transition amplitude of the output voltage signal.

In an embodiment of the present invention, in the above-mentioned over-driving mode, the operational amplifier circuit uses an external capacitor to raise or lower the voltage of the node, thereby increasing the transient amplitude of the output voltage signal.

In an embodiment of the invention, the difference between the transition amplitude of the output voltage signal and the voltage amplitude of the input voltage signal is positively correlated with the voltage amplitude of the input voltage signal.

In an embodiment of the present invention, after the second period when the switch circuit is switched from the on-state to the off state, the switch circuit is switched from the off-state to the on state, causing the operational amplifier circuit to operate in the normal driving mode to allow The output voltage signal follows the input voltage signal.

In an embodiment of the invention, in the normal driving mode, the node voltage signal of the node follows the input voltage signal.

In an embodiment of the invention, the operational amplifier circuit includes an input stage, an amplifier Benefit level and output level. The input stage is used to receive the node voltage signal and the output voltage signal, and determine the voltage difference between the node voltage signal and the output voltage signal to generate the first differential pair signal and the second differential pair signal. The gain stage is coupled to the input stage to receive the first differential pair signal and the second differential pair signal, and accordingly generate a current corresponding to the above voltage difference. The output stage is coupled to the gain stage and generates an output voltage signal.

In an embodiment of the invention, the input stage includes an N-type differential pair and a P-type differential pair. The first differential input of the N-type differential pair receives the node voltage signal. The second differential input of the N-type differential pair receives the output voltage signal. The first differential output terminal of the N-type differential pair outputs one of the first differential pair signals. The second differential output terminal of the N-type differential pair outputs the other signal of the first differential pair signal. The first differential input of the P-type differential pair receives the node voltage signal. The second differential input of the P-type differential pair receives the output voltage signal. The first differential output terminal of the P-type differential pair outputs one of the signals of the second differential pair signal. The second differential output terminal of the P-type differential pair outputs the other signal of the second differential pair signal.

In an embodiment of the invention, the N-type differential pair includes a first N-type transistor, a second N-type transistor, and a first current source. The first terminal of the first N-type transistor is coupled to the first common terminal. The second end of the first N-type transistor is coupled to the first differential output end of the N-type differential pair. The control terminal of the first N-type transistor is coupled to the first differential input terminal of the N-type differential pair to receive the node voltage signal. The first terminal of the second N-type transistor is coupled to the first common terminal. The second end of the second N-type transistor is coupled to the second differential output end of the N-type differential pair. The control end of the second N-type transistor is coupled to the second differential input end of the N-type differential pair to receive the output voltage signal. The first current source is coupled to the first common terminal Between ground voltage terminals. The P-type differential pair includes a first P-type transistor, a second P-type transistor, and a second current source. The first terminal of the first P-type transistor is coupled to the second common terminal. The second end of the first P-type transistor is coupled to the first differential output end of the P-type differential pair. The control terminal of the first P-type transistor is coupled to the first differential input terminal of the P-type differential pair to receive the node voltage signal. The first terminal of the second P-type transistor is coupled to the second common terminal. The second end of the second P-type transistor is coupled to the second differential output end of the P-type differential pair. The control terminal of the second P-type transistor is coupled to the second differential input terminal of the P-type differential pair to receive the output voltage signal. The second current source is coupled between the power voltage terminal and the second common terminal.

In an embodiment of the invention, there is an external capacitor between the first common terminal and the first differential input terminal of the N-type differential pair. In the over-driving mode and the output voltage signal undergoes a falling transition, the operational amplifier circuit pulls down the node voltage signal through an external capacitor, thereby increasing the transition amplitude of the output voltage signal.

In an embodiment of the invention, there is an external capacitor between the second common terminal and the first differential input terminal of the P-type differential pair. When the output voltage signal rises and transitions in the overdrive mode, the operational amplifier circuit raises the node voltage signal through an external capacitor, thereby increasing the transition width of the output voltage signal.

Based on the above, in the buffer circuit provided by the embodiment of the present invention, an external capacitor may be additionally connected between the first common connection end of the N-type differential pair and the first differential input end, or the P-type differential pair An external capacitor is additionally connected between the second common terminal and the first differential input terminal. When the switch circuit is in the off state, the external capacitor can be used to increase the transition amplitude of the output voltage signal. In this way, the driving ability of the output voltage signal can be effectively improved to achieve the effect of overdriving.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

100‧‧‧buffer circuit

120‧‧‧Switch circuit

140‧‧‧Operation amplifier circuit

142‧‧‧ input level

144‧‧‧Gain stage

146‧‧‧ output stage

250, 260‧‧‧ voltage waveform

A1, A1’‧‧‧ voltage amplitude

A2, A2’‧‧‧Transition amplitude

ANC, APC‧‧‧ common contact

C1, C2‧‧‧Capacitance

CL‧‧‧Capacitor

DP_N‧‧‧N type differential pair

DP_P‧‧‧P differential pair

DPS1‧‧‧First differential pair signal

DPS2‧‧‧Second differential pair signal

GND‧‧‧Ground voltage terminal

HOD‧‧‧switch signal

I1, I2‧‧‧ current source

IN‧‧‧input

IT1, IP1‧‧‧First differential input

IT2, IP2‧‧‧second differential input

MN1, MN2 ‧‧‧N-type transistor

MP1, MP2‧‧‧P type transistor

ND‧‧‧Node

OP1, OT1‧‧‧First differential output

OP2, OT2 ‧‧‧ second differential output

PWR‧‧‧Power voltage terminal

RL‧‧‧Resistance

T0~T5‧‧‧time

TP1~TP5‧‧‧‧

VIN‧‧‧Input voltage signal

VL‧‧‧ Load voltage

VND‧‧‧ Node voltage signal

VO‧‧‧Output voltage signal

ΔV, ΔV’‧‧‧ difference

The drawings below are part of the description of the present invention, and illustrate exemplary embodiments of the present invention. The drawings together with the description of the description illustrate the principle of the present invention.

FIG. 1 is a schematic circuit block diagram of a buffer circuit according to an embodiment of the invention.

FIG. 2 is a signal timing diagram of a buffer circuit according to an embodiment of the invention.

3 is a block diagram of an operational amplifier circuit according to an embodiment of the invention.

4 is a schematic diagram of a circuit structure of an input stage according to an embodiment of the invention.

FIG. 5 is a signal timing diagram of a buffer circuit according to an embodiment of the invention.

6 is a signal timing diagram of a buffer circuit according to another embodiment of the invention.

Reference will now be made in detail to exemplary embodiments of the present invention, illustrated in the accompanying drawings. Examples of the exemplary embodiment are described. In addition, wherever possible, elements/components using the same reference numerals in the drawings and embodiments represent the same or similar parts.

FIG. 1 is a schematic circuit block diagram of a buffer circuit according to an embodiment of the invention. Referring to FIG. 1, the buffer circuit 100 includes a switch circuit 120 and an operational amplifier circuit 140, but the present invention is not limited thereto. The switch circuit 120 is coupled between the input terminal IN and the node ND of the buffer circuit 100 for receiving the input voltage signal VIN from the input terminal IN. The switching circuit 120 can be turned on or turned off under the control of the switching signal HOD. In this embodiment, the switch circuit 120 can be turned off in response to the switching signal HOD of the logic high level, and can be turned on in response to the switching signal HOD of the logic low level, but the invention is not limited thereto. Those of ordinary skill in the art know that the relationship between whether the switch circuit 120 is turned on and the logic level of the switch signal HOD can be defined by the designer according to actual needs.

The non-inverting input terminal of the operational amplifier circuit 140 is coupled to the node ND. The output terminal of the operational amplifier circuit 140 is coupled to the inverting input terminal of the operational amplifier circuit 140. The output terminal of the operational amplifier circuit 140 provides the output voltage signal VO. The output voltage signal VO can be used to drive an external load (such as a liquid crystal display, but not limited to this). In the embodiment of FIG. 1, the external load is represented by the equivalent resistance RL and capacitance CL.

In an embodiment of the invention, the switch circuit 120 may be, for example, a transmission gate, but the invention is not limited thereto. The invention does not limit the implementation of the switch circuit 120.

The operation of the buffer circuit 100 will be described below with reference to FIG. 2. FIG. 2 is a signal timing diagram of a buffer circuit according to an embodiment of the invention. Please refer to 1 and 2, after the first period TP1 (the fourth period TP4) of the input voltage signal VIN starts to transition, the switch circuit 120 is switched from the on-state to the off-state, causing the operational amplifier circuit 140 to operate in overdrive Mode to increase the transition amplitude A2(A2') of the output voltage signal VO.

In detail, the input voltage signal VIN starts to rise and transition at the time point T0. After the first period TP1, at the time point T1, the switching signal HOD is switched from the logic low level to the logic high level, so the switch circuit 120 is turned off, so that the node ND is in a floating state. Then, the operational amplifier circuit 140 can raise the voltage of the node ND (that is, the voltage of the node voltage signal VND) through an external capacitor, thereby increasing the transient amplitude A2 of the output voltage signal VO, where the transient amplitude A2 of the output voltage signal VO is greater than The voltage amplitude A1 of the input voltage signal VIN.

After the second period TP2, at the time point T2, the switching signal HOD is switched from the logic high level to the logic low level, so the switch circuit 120 is switched from the off state to the on state, causing the node voltage signal VND of the node ND to follow the input The voltage signal VIN, therefore, the operational amplifier circuit 140 operates in the normal driving mode so that the output voltage signal VO also follows the input voltage signal VIN.

In addition, after the third period TP3, the input voltage signal VIN starts to fall and transition at the time point T3. After the fourth period TP4, at the time point T4, the switching signal HOD transitions from the logic low level to the logic high level, so the switch circuit 120 is turned off, causing the node ND to be in a floating state. Then, the operational amplifier circuit 140 can pull down the voltage of the node ND (that is, the voltage of the node voltage signal VND) through an external capacitor, thereby increasing the transition amplitude A2' of the output voltage signal VO, where the output voltage The transition amplitude A2' of the signal VO is greater than the voltage amplitude A1 of the input voltage signal VIN.

After the fifth period TP5, at the time point T5, the switching signal HOD is switched from the logic high level to the logic low level, so the switch circuit 120 is switched from the off state to the on state, causing the node voltage signal VND of the node ND to follow the input The voltage signal VIN, therefore, the operational amplifier circuit 140 operates in the normal driving mode so that the output voltage signal VO also follows the input voltage signal VIN.

Since the operational amplifier circuit 140 can increase the transition amplitudes A2 and A2' of the output voltage signal VO when the switch circuit 120 is in the off state (ie, the second period TP2 and the fifth period TP5), the output voltage signal VO can be effectively increased. Drive ability to achieve the effect of overdriving, thereby accelerating the switching speed of the load voltage VL. As shown in FIG. 2, the voltage waveform 250 is the voltage waveform of the load voltage VL driven by the buffer circuit 100 of the embodiment of the present invention, and the voltage waveform 260 is driven by a buffer circuit that generally does not have an overdrive function The voltage waveform of the load voltage VL. It can be clearly seen from FIG. 2 that the transition speed of the voltage waveform 250 is significantly faster than the transition speed of the voltage waveform 260.

3 is a block diagram of an operational amplifier circuit according to an embodiment of the invention. Please refer to Figure 3. The operational amplifier circuit 140 includes an input stage 142, a gain stage 144, and an output stage 146, but the invention is not limited thereto. The input stage 142 is used to receive the node voltage signal VND and the output voltage signal VO, and determine the voltage difference between the node voltage signal VND and the output voltage signal VO to generate the first differential pair signal DPS1 and the second differential pair signal DPS2 . The gain stage 144 is coupled to the input stage 142 to receive the first differential pair signal DPS1 and the second differential pair signal DPS2, and generate a pair accordingly The current corresponding to this voltage difference. The output stage 146 is coupled to the gain stage 144 and generates an output voltage signal VO.

In an embodiment of the invention, the gain stage 144 and the output stage 146 can be implemented using known gain stage circuits and output stage circuits, respectively.

4 is a schematic diagram of a circuit structure of an input stage according to an embodiment of the invention. Please refer to Figure 3 and Figure 4 together. The input stage 142 may include an N-type differential pair DP_N and a P-type differential pair DP_P. The first differential input terminal IT1 of the N-type differential pair DP_N receives the node voltage signal VND. The second differential input terminal IT2 of the N-type differential pair DP_N receives the output voltage signal VO. The first differential output terminal OT1 of the N-type differential pair DP_N outputs one of the first differential pair signal DPS1. The second differential output terminal OT2 of the N-type differential pair DP_N outputs the other one of the first differential pair signal DPS1.

The first differential input terminal IP1 of the P-type differential pair DP_P receives the node voltage signal VND. The second differential input terminal IP2 of the P-type differential pair DP_P receives the output voltage signal VO. The first differential output terminal OP1 of the P-type differential pair DP_P outputs one of the second differential pair signal DPS2. The second differential output terminal OP2 of the P-type differential pair DP_P outputs another one of the second differential pair signal DPS2.

In detail, the N-type differential pair DP_N includes N-type transistors MN1, MN2 and a current source I1. The first terminal of the N-type transistor MN1 is coupled to the common terminal ANC. The second terminal of the N-type transistor MN1 is coupled to the first differential output terminal OT1 of the N-type differential pair DP_N. The control terminal of the N-type transistor MN1 is coupled to the first differential input terminal IT1 of the N-type differential pair DP_N to receive the node voltage signal VND. N-type transistor MN2 first The terminal is coupled to the common terminal ANC. The second terminal of the N-type transistor MN2 is coupled to the second differential output terminal OT2 of the N-type differential pair DP_N. The control terminal of the N-type transistor MN2 is coupled to the second differential input terminal IT2 of the N-type differential pair DP_N to receive the output voltage signal VO. The current source I1 is coupled between the common terminal ANC and the ground voltage terminal GND.

The P-type differential pair DP_P includes P-type transistors MP1, MP2 and a current source I2. The first end of the P-type transistor MP1 is coupled to the common terminal APC. The second terminal of the P-type transistor MP1 is coupled to the first differential output terminal OP1 of the P-type differential pair DP_P. The control terminal of the P-type transistor MP1 is coupled to the first differential input terminal IP1 of the P-type differential pair DP_P to receive the node voltage signal VND. The first end of the P-type transistor MP2 is coupled to the common terminal APC. The second terminal of the P-type transistor MP2 is coupled to the second differential output terminal OP2 of the P-type differential pair DP_P. The control terminal of the P-type transistor MP2 is coupled to the second differential input terminal IP2 of the P-type differential pair DP_P to receive the output voltage signal VO. The current source I2 is coupled between the power supply voltage terminal PWR and the common terminal APC.

In an embodiment of the present invention, the N-type transistors MN1 and MN2 may be, for example, N-type metal oxide half field effect transistors, and the P-type transistors MP1, MP2 may be, for example, P-type metal oxide half field effect transistors, but this The invention is not limited to this.

In an embodiment of the invention, the common terminal ANC and the first differential input terminal IT1 of the N-type differential pair DP_N have a capacitor C1, and the first terminal APC and the P-type differential pair DP_P have a first difference There is a capacitor C2 between the dynamic input terminal IP1, wherein the capacitor C1 is an external capacitor, and the capacitor C2 is an external capacitor, but the invention is not limited thereto.

FIG. 5 is a signal timing diagram of a buffer circuit according to an embodiment of the invention. Please refer to Figure 1, Figure 4 and Figure 5 together. Input voltage signal VIN at The point T0 begins to rise and transition. Since the switching signal HOD is at a logic low level, the switching circuit 120 is in an on state, so that the node voltage signal VND follows the input voltage signal VIN. In the first period TP1, the node voltage signal VND gradually changes from a low potential to a high potential following the input voltage signal VIN. However, due to the internal circuit delay of the operational amplifier circuit 140 and the influence of external loads (such as the resistor RL and the capacitor CL), the speed of the rising transition of the output voltage signal VO is slower than the speed of the rising transition of the node voltage signal VND. Since the N-type differential pair DP_N and the P-type differential pair DP_P in the operational amplifier circuit 140 are controlled by the node voltage signal VND and the output voltage signal VO, therefore, in the N-type differential pair DP_N shown in FIG. 4, the current is large Some will flow from the N-type transistor MN1 to the current source I1, so that the voltage of the common contact ANC follows the node voltage signal VND. In the P-type differential pair DP_P, most of the current of the current source I2 flows into the P-type transistor MP2, so that the voltage of the common contact APC follows the output voltage signal VO.

At time T1, the voltage of the node voltage signal VND approaches the voltage of the input voltage signal VIN, so the switching signal HOD is switched from the logic low level to the logic high level to turn off the switching circuit 120, so that the node ND is in a floating state. At this time, the output voltage signal VO is still in the process of rising transition, so the output voltage signal VO continues to rise, and the voltage of the common contact APC also continues to rise following the output voltage signal VO. Since the node ND is in the floating state, the node voltage signal VND will be boosted by the voltage of the common contact APC through the external capacitor C2. As shown in FIG. 5, in the overdrive mode of the second period TP2, the voltage value of the node voltage signal VND is raised to exceed the voltage value of the input voltage signal VIN, resulting in an output voltage signal VO also rises, thereby increasing the transient amplitude of the output voltage signal VO to achieve the effect of overdriving.

It is worth mentioning that the difference ΔV between the transition amplitude A2 of the output voltage signal VO and the voltage amplitude A1 of the input voltage signal VIN is positively related to the voltage amplitude A1 of the input voltage signal VIN. That is to say, if the voltage amplitude A1 of the input voltage signal VIN is larger, the difference ΔV is also larger, and vice versa.

After the second period TP2, at the time point T2, the switching signal HOD is switched from the logic high level to the logic low level, so the switch circuit 120 is turned on, causing the node voltage signal VND and the output voltage signal VO to follow the input voltage signal VIN.

6 is a signal timing diagram of a buffer circuit according to another embodiment of the invention. Please refer to Figure 1, Figure 4 and Figure 6 together. The input voltage signal VIN begins to fall and transition at time T3. Since the switching signal HOD is at a logic low level, the switching circuit 120 is in an on state, so that the node voltage signal VND follows the input voltage signal VIN. In the fourth period TP4, the node voltage signal VND gradually transitions from the high potential to the low potential following the input voltage signal VIN. However, due to the internal circuit delay of the operational amplifier circuit 140 and the influence of external loads (such as the resistor RL and the capacitor CL), the speed of the falling transition of the output voltage signal VO is slower than the speed of the falling transition of the node voltage signal VND. Since the N-type differential pair DP_N and the P-type differential pair DP_P in the operational amplifier circuit 140 are controlled by the node voltage signal VND and the output voltage signal VO, therefore, in the N-type differential pair DP_N shown in FIG. 4, the current is large Some will flow from the N-type transistor MN2 to the current source I1, causing the voltage of the common contact ANC to chase With the output voltage signal VO. In the P-type differential pair DP_P, most of the current of the current source I2 flows into the P-type transistor MP1, so that the voltage of the common contact APC follows the node voltage signal VND.

At time T4, the voltage of the node voltage signal VND approaches the voltage of the input voltage signal VIN, so the switching signal HOD is switched from the logic low level to the logic high level to turn off the switching circuit 120, so that the node ND is in a floating state. At this time, the output voltage signal VO is still in the process of falling transition, so the output voltage signal VO still continues to fall, and the voltage of the common contact ANC also continues to fall following the output voltage signal VO. Since the node ND is in the floating state, the node voltage signal VND will be pulled down by the voltage of the common contact ANC through the external capacitor C1. As shown in FIG. 6, in the overdriving mode of the fifth period TP5, the voltage value of the node voltage signal VND is pulled down to be lower than the voltage value of the input voltage signal VIN, resulting in the output voltage signal VO also dropping, thereby increasing the output voltage The transient amplitude of the signal VO achieves the effect of overdriving.

Similarly, the difference ΔV' of the transition amplitude A2' of the output voltage signal VO and the voltage amplitude A1' of the input voltage signal VIN is positively related to the voltage amplitude A1' of the input voltage signal VIN. In detail, the larger the voltage amplitude A1' of the input voltage signal VIN, the larger the difference ΔV', and vice versa.

After the fifth period TP5, at the time point T5, the switching signal HOD is switched from the logic high level to the logic low level, so the switch circuit 120 is turned on, causing the node voltage signal VND and the output voltage signal VO to follow the input voltage signal VIN.

In summary, in the buffer circuit provided in the embodiment of the present invention, an external capacitor can be connected between the common connection end of the N-type differential pair and the first differential input end of the N-type differential pair, and An external capacitor is connected between the common connection end of the type differential pair and the first differential input end of the P type differential pair, so that when the switch circuit is in the off state, the external capacitor is used to increase the transient amplitude of the output voltage signal. In this way, the driving ability of the output voltage signal can be effectively improved to achieve the effect of overdriving.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100‧‧‧buffer circuit

120‧‧‧Switch circuit

140‧‧‧Operation amplifier circuit

CL‧‧‧Capacitor

HOD‧‧‧switch signal

IN‧‧‧input

ND‧‧‧Node

RL‧‧‧Resistance

VIN‧‧‧Input voltage signal

VL‧‧‧ Load voltage

VND‧‧‧ Node voltage signal

VO‧‧‧Output voltage signal

Claims (9)

A buffer circuit includes: a switching circuit coupled between an input terminal and a node of the buffer circuit for receiving an input voltage signal from the input terminal; and an operational amplifier circuit The inverting input terminal is coupled to the node, and the output terminal of the operational amplifier circuit is coupled to the inverting input terminal of the operational amplifier circuit and outputs an output voltage signal, wherein after a first period when the input voltage signal begins to transition , The switch circuit is switched from an on state to an off state, causing the operational amplifier circuit to operate in an overdrive mode to increase a transitional amplitude of the output voltage signal through an external capacitor. After a second period when the on-state is switched to the off-state, the switch circuit is switched from the off-state to the on-state, causing the operational amplifier circuit to operate in a normal driving mode to allow the output voltage signal to follow the Input voltage signal. The buffer circuit as described in item 1 of the patent application scope, wherein in the overdrive mode, the operational amplifier circuit raises or pulls down a voltage of the node through the external capacitor, thereby increasing the transient amplitude of the output voltage signal . The buffer circuit as recited in item 1 of the patent application range, wherein a difference between the transient amplitude of the output voltage signal and a voltage amplitude of the input voltage signal is positively correlated with the voltage amplitude of the input voltage signal. The buffer circuit as described in item 1 of the patent application scope, wherein in the normal driving mode, a node voltage signal of the node follows the input voltage signal. The buffer circuit as described in item 1 of the patent application scope, wherein the operational amplifier circuit includes: an input stage for receiving a node voltage signal and the output voltage signal of the node, and determining the node voltage signal and the output voltage A voltage difference between the signals to generate a first differential pair signal and a second differential pair signal; a gain stage coupled to the input stage to receive the first differential pair signal and the second differential pair A signal to generate a current corresponding to the voltage difference; and an output stage coupled to the gain stage and generating the output voltage signal. The buffer circuit as described in item 5 of the patent application scope, wherein the input stage includes: an N-type differential pair, a first differential input terminal of the N-type differential pair receives the node voltage signal, and the N-type differential A second differential input of the dynamic pair receives the output voltage signal, a first differential output of the N-type differential pair outputs one of the first differential pair signals, and the N-type differential pair A second differential output of the second output of the first differential pair signal; and a P-type differential pair, a first differential input of the P-type differential pair receives the node voltage signal, A second differential input terminal of the P-type differential pair receives the output voltage signal, a first differential output terminal of the P-type differential pair outputs one of the second differential pair signals, and the P A second differential output terminal of the type differential pair outputs another signal of the second differential pair signal. The buffer circuit as described in item 6 of the patent application scope, wherein the N-type differential pair includes: a first N-type transistor, and a first end of the first N-type transistor is coupled to a first common connection End, a second end of the first N-type transistor is coupled to the first differential output end of the N-type differential pair, and a control end of the first N-type transistor is coupled to the N-type differential pair The first differential input terminal to receive the node voltage signal; a second N-type transistor, a first end of the second N-type transistor is coupled to the first common terminal, the second N-type A second end of the crystal is coupled to the second differential output end of the N-type differential pair, and a control end of the second N-type transistor is coupled to the second differential input end of the N-type differential pair To receive the output voltage signal; and a first current source, coupled between the first common terminal and a ground voltage terminal, the P-type differential pair includes: a first P-type transistor, the first A first terminal of the P-type transistor is coupled to a second common terminal, a second terminal of the first P-type transistor is coupled to the first differential output terminal of the P-type differential pair, and the first A control terminal of a P-type transistor is coupled to the first differential input terminal of the P-type differential pair to receive the node voltage signal; a second P-type transistor, a first of the second P-type transistor The terminal is coupled to the second common terminal, a second terminal of the second P-type transistor is coupled to the second differential output terminal of the P-type differential pair, and the control terminal of the second P-type transistor The second differential input terminal of the P-type differential pair is coupled to receive the output voltage signal; and a second current source coupled between a power voltage terminal and the second common terminal between. The buffer circuit as recited in item 7 of the patent application range, wherein the external capacitor is coupled between the first common terminal and the first differential input terminal of the N-type differential pair, wherein in the overdrive mode and When the output voltage signal undergoes a falling transition, the operational amplifier circuit pulls down the node voltage signal through the external capacitor, thereby increasing the transition amplitude of the output voltage signal. The buffer circuit as recited in item 7 of the patent application range, wherein the external capacitor is coupled between the second common terminal and the first differential input terminal of the P-type differential pair, wherein in the overdrive mode When the output voltage signal rises and transitions, the operational amplifier circuit lifts the node voltage signal through the external capacitor, thereby increasing the transition amplitude of the output voltage signal.

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