TWI678699B - Flash memory storage device and method thereof - Google Patents

Abstract

A flash memory storage device includes a memory cell array and a memory control circuit. The memory cell array includes a plurality of well regions. Each well area includes a plurality of memory blocks and a recording block. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to perform an erasing operation on a memory block of each well area, and record the erasure times of each well area in a respective recording block. In addition, a method for operating a flash memory storage device is also proposed.

Description

Flash memory storage device and operation method thereof

The invention relates to a memory storage device and an operation method thereof, and in particular to a flash memory storage device and an operation method thereof.

For a flash memory storage device, a cycling operation is likely to generate an interface state at its drain junction, and an oxide trap is generated at its tunneling oxide layer. Generally, the loop operation includes an erase operation and a program operation. Flash memory cells are often easily degraded after multiple cycles of operation. For example, the reliability of the memory block will decrease, or the erase time and programming time will increase, that is, the operation speed will be slower. In addition, after many cycles of operation, some of the bits in the unit cell will not meet the specifications due to premature wear. These worn bits are difficult to remove during the testing phase. Therefore, if the number of erasures of each well region including a plurality of memory blocks in the memory cell array can be obtained, it will be helpful to evaluate the performance of the flash memory storage device in subsequent applications or manufacturing processes.

The invention provides a flash memory storage device and an operation method thereof, which can record the number of erasures of a well area therein.

The flash memory storage device of the present invention includes a memory cell array and a memory control circuit. The memory cell array includes a plurality of well regions. Each well area includes a plurality of memory blocks and a recording block. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to perform an erasing operation on a memory block of each well area, and record the erasure times of each well area in a respective recording block.

The operation method of the flash memory storage device of the present invention includes: performing an erasing operation on a plurality of memory blocks in a memory cell array; judging whether the number of erasures recorded in at least one record row reaches an upper limit; If the number of erasures recorded in at least one record row has reached the upper limit, the erase operation is performed on at least one record row while the memory block in the memory cell array is being erased; and The number of erasures recorded in one record row does not reach the upper limit, and the data of the erasure times is recorded in at least one record row. The memory block and the recording block are located in the same well area.

Based on the above, in the exemplary embodiment of the present invention, the flash memory storage device can automatically record the number of times each well area is erased. The recorded data can be used for subsequent evaluation of the performance of the flash memory storage device.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a flash memory storage device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a well region in the memory cell array of the embodiment shown in FIG. 1. FIG. Please refer to FIG. 1 and FIG. 2. The flash memory storage device 100 in this embodiment includes a memory cell array 110 and a memory control circuit 120. The memory control circuit 120 is coupled to the memory cell array 110. In this embodiment, the flash memory storage device 100 is, for example, a coded flash memory (NOR Flash).

In this embodiment, the memory cell array 110 includes a plurality of well regions 112 as shown in FIG. 2. FIG. 2 illustrates only one well region 112 in the memory cell array 110, but the number is not intended to limit the present invention. The well region 112 is, for example, a P well. The well area 112 includes a plurality of memory blocks 111_1 to 111_N and a recording block 113, where N is a positive integer greater than 0. The memory blocks 111_1 to 111_N are used to store data. The recording block 113 is used for storing the erasure times of the well area 112.

In this embodiment, the memory control circuit 120 is configured to perform an erasing operation on the memory blocks 111_1 to 111_N of the well area 112 and record the erasure times of the well area 112 in the recording block 113. For example, the memory control circuit 120 performs an erase operation on the target memory block 111_2 during the erase. At this time, a positive high voltage is applied to the well region 112, a negative high voltage is applied to the gate of the memory cell array in the target memory block 111_2, and the remaining memory blocks 111_1, 111_3, A positive voltage is applied to the gates of the memory cell array in 111_ (N-1) and 111_N. In this embodiment, the memory block 111_2 is erased, and the number of erasures of the well region 112 is increased by one. Then, the memory control circuit 120 records the number of erasures in the recording block 113. Any one of the memory blocks 111_1 to 111_N is erased, and the number of erasures of the well region 112 is increased once.

In an embodiment of multiple well regions, the memory control circuit 120 performs an erase operation on the memory blocks of each well region, and records the number of erasures of each well region in a respective recording block.

In this embodiment, the memory control circuit 120 may be implemented by any suitable circuit structure in the technical field to which it belongs. The present invention is not limited thereto, and the circuit structure and operation method thereof can be obtained from the general knowledge in the technical field Teaching, suggestions and implementation instructions.

FIG. 3 is a schematic diagram of a recording block in the embodiment of FIG. 1. Referring to FIG. 3, the record block 113 of this embodiment includes a plurality of record columns 310_1 to 310_M, where M is a positive integer greater than 0. The record columns 310_1 to 310_M include a plurality of bytes 312. The number of bytes in each record column can be the same or different. Record rows 310_1 to 310_M are used to store data of the number of erasures. For example, each record row is, for example, a character line, which is coupled to a plurality of memory cells (not shown), and some of the memory cells are used to store data of the number of erasures. For example, in one embodiment, a plurality of memory cells corresponding to two bytes of data in each record row are used to store data of the number of erasures. In one embodiment, a plurality of memory cells corresponding to four bytes of data in each record row are used to store data of the number of erasures.

In this embodiment, the memory control circuit 120 sequentially records data of the number of erasures to the last record row 310_M starting from the first record row 310_0. Taking the first record row 310_1 including two bytes as an example, the memory control circuit 120 starts from the least significant bit LSB of the byte 312_1 and sequentially records the data of the erasure number to the most significant bit. MSB. For example, after the memory control circuit 120 performs an erase operation on any of the memory blocks 111_1 to 111_N of the well region 112, the least significant bit LSB in the byte 312_1 is programmed from the state "1" to the state "0" "To indicate that the number of erasures of the well region 112 was increased by one and recorded in byte 312_1. In this way, the memory control circuit 120 sequentially records data of the number of erasures to the most significant bit MSB in the byte group 312_1.

Then, the memory control circuit 120 starts from the least significant bit LSB of the byte 312_2 and sequentially records the data of the number of erasures to the most significant bit MSB of the byte 312_2. Therefore, when all the bits of the two bytes 312_1 and 312_2 in the record row 310_1 are programmed from the state “1” to the state “0”, it means that the number of erasures of the well region 112 is 16 times. These 16 times are the upper limit of the number of erasures recorded in the record column 310_1. When the number of erasures recorded in record row 310_1 (first record row) has reached the upper limit of record row 310_1, memory control circuit 120 uses its next record row 310_2 (second record row) to record record row 310_1. Number of erases recorded.

For example, when the number of erasures recorded in the record column 310_1 has reached the upper limit of 16 times, the memory control circuit 120 performs an erasing operation on any memory block during erasing, and simultaneously The record row 310_1 performs an erasing operation to erase all the bits of the two byte groups 312_1 and 312_2 from the state “0” to the state “1” to re-record the number of erasures. At this time, when the record row 310_1 is erased once, the memory control circuit 120 programs the least significant bit LSB in the byte 312_3 of the record row 310_2 from the state "1" to the state "0" to indicate the record The number of erasures of column 310_1 is one, which also indicates that the number of erasures of well region 112 has accumulated 17 times and is recorded in byte 312_3. In this way, the memory control circuit 120 sequentially records data of the number of erasures to the most significant bit MSB of the byte group 312_3.

In this embodiment, after the erase operation is performed on the record row 310_1, the memory control circuit 120 records the data of the number of erasures again in the bytes 312_1 and 312_2 of the record row 310_1, and reuses the record row 310_1 To increase the maximum number of recordings in the recording block 113.

Then, the memory control circuit 120 sequentially records the data of the number of erasures to the most significant bit MSB of the byte 312_4 starting from the least significant bit LSB of the byte 312_4. Therefore, when all the bits of the two bytes 312_3 and 312_4 in the record row 310_2 are programmed from the state "1" to the state "0", it means that the number of erasures of the well region 112 is 256 times. These 256 times are the upper limit of the number of erasures recorded in the record column 310_2. If the number of erasures recorded in the record row 310_1 and the record row 310_2 has reached the upper limit, the memory control circuit 120 performs an erase operation on the record row 310_1 and the record row 310_2 at the same time to re-record the number of erases. At this time, when the record row 310_1 and the record row 310_2 are erased, the memory control circuit 120 programs the least significant bit LSB in the byte 312_5 of the record row 310_3 from the state "1" to the state "0", The number of erasures of the well region 112 has been accumulated 257 times, and is recorded in the byte 312_5. In this way, the memory control circuit 120 sequentially records data of the number of erasures to the most significant bit MSB of the byte group 312_5.

In this embodiment, after the erase operation is performed on the record row 310_1 and the record row 310_2, the memory control circuit 120 records the data of the number of erasures again in the bytes 312_1, 312_2 and the record row 310_2 In the bytes 312_3 and 312_4, the record bytes of the record row 310_1 and the record row 310_2 are repeatedly used to increase the upper limit of the number of records of the record block 113.

By analogy, if the goal is to record the number of erasures of 100 thousand times (100k), the record block 113 includes 4 record rows, and the first to third record rows correspond to the data amount of storing two bytes. To store the data of the number of erasures, and the fourth record row stores the data of the number of erasures by multiple memory cells corresponding to the amount of data stored in three bytes. When the number of erasures recorded in the last record row (for example, 310_M) has reached the upper limit of the record row, it is the upper limit of the number of erasures recorded in its record block. Erase the last record column.

In another embodiment, the record block 113 includes, for example, four record rows, and the first to third record rows store erasure times with a plurality of memory cells corresponding to a data amount of four bytes. The fourth record row stores data of the number of erasures with multiple memory cells corresponding to the amount of data stored in one byte. Therefore, in this example, the recording block 113 can record about 256 thousand (256k) erasure times.

In this embodiment, each record row is, for example, a character line, which is coupled to a plurality of memory cells (not shown), and some of the memory cells are used to store data of the number of erasures. Compared to the character lines coupled to the memory blocks 111_1 to 111_N, the character lines coupled to the record block 113 (that is, the record row) are characters additionally set in the well area 112 to record the number of erasures. Yuan line. When the memory control circuit 120 programs a valid bit in the byte of the record row 310_1 (LSB record row) from the state “1” to the state “0”, the number of erasures of the record well region 112 is increased once. When the number of erasures recorded in the record row 310_1 reaches the upper limit and is erased once, the memory control circuit 120 programs a valid bit in the byte of the next record row 310_2 from the state "1" to The state "0" indicates that the number of erasures of the record row 310_1 is increased by one. When the erase times recorded in the bytes of the record rows 310_1 to 310_2 all reach the upper limit and are erased at the same time, the memory control circuit 120 deletes a valid bit in the bytes of the next record row 310_3. It is programmed from the state "1" to the state "0" to indicate that the number of erasures of the record row 310_2 is increased by one. The number of erasures of the well region 112 can be calculated from data of unequal values in the bytes of each record column.

FIG. 4 is a flowchart illustrating a method of operating a flash memory storage device according to an embodiment of the invention. The operation method of this embodiment is applicable to, for example, a coded NOR flash storage device. Please refer to FIGS. 1 to 4. In step S100, the memory control circuit 120 erases the memory blocks 111_1 to 111_N located in the same well region 112 in the memory cell array 110. In step S110, the memory control circuit 120 determines whether the number of erasures recorded in the record column 310_1 in the record block 113 has reached the upper limit. If yes, the memory control circuit 120 executes step S120 to perform an erasing operation on the record row 310_1 while performing an erasing operation on the memory blocks 111_1 to 111_N, and records data of the number of erasures in the record row 310_2 . If not, the memory control circuit 120 executes step S130 to record the data of the erasure times in the record row 310_1.

In addition, the operation method of the flash memory storage device according to the embodiment of the present invention can obtain sufficient teaching, suggestions, and implementation description from the description of the embodiment of FIG. 1 to FIG. 3.

FIG. 5 is a flowchart illustrating a method of operating a flash memory storage device according to another embodiment of the present invention. The operation method of this embodiment is applicable to, for example, a coded NOR flash storage device. Please refer to FIG. 5. In this embodiment, the memory control circuit 120 erases the memory blocks 111_1 to 111_N located in the same well region 112 in the memory cell array 110. The erase operation includes a pre-program operation (step S210), an erase operation (step S220), and a post-program operation (step S230) on the target memory block 111_2. To softly program the memory cell over-erased in the target memory block and refresh the blocks 111_1 and 111_3 to 111_N outside the target memory (step S240) to Stylized for already programmed memory cells in non-target memory blocks. In this embodiment, performing a pre-programmed operation, an erase operation, a post-programmed operation on the target memory block 111_2, and a refresh operation on the blocks 111_1 and 111_3 to 111_N other than the target memory may be performed in the technical field to which they belong Adequate teaching, advice and implementation instructions are usually obtained from the knowledge.

In this embodiment, before step S210 is performed, in step S200, the memory control circuit 120 first scans the bytes 312_1 and 312_2 in the record column 310_1 to determine which bits have a status of "1" . If at least one of the bits 312_1 and 312_2 has a status of “1”, the memory control circuit 120 may record data of the number of erasures in a bit of status “1” in step S250. If the state of all the bits in the bytes 312_1, 312_2 is "0", the memory control circuit 120 may record data of the number of erasures in the record row 310_2, that is, the stylized record row 310_2, in step S250. Furthermore, in step S220, the memory control circuit 120 performs an erase operation on the target memory block 111_2 while performing an erase operation on the record row 310_1.

In step S200, after scanning, if the memory control circuit 120 determines that the state of all the bits in the byte rows 310_1 and 320_2 is "0", the memory control circuit 120 may erase the state in step S250. The number of times is recorded in the next record column of record column 310_2. Furthermore, in step S220, the memory control circuit 120 performs an erase operation on the target memory block 111_2 while performing an erase operation on the record rows 310_1 and 310_2. The erasing operation of the memory control circuit 120 on the remaining records can be deduced by analogy.

In this embodiment, the memory control circuit 120 performs post-programming operations and refresh operations on the memory blocks 111_1 to 111_N in steps S230 and S240, and also performs post-programming on the recording block 113. Operation and refresh operation. In addition, the method for operating the flash memory storage device according to the embodiment of the present invention can obtain sufficient teaching, suggestions, and implementation description from the description of the embodiment of FIGS. 1 to 4.

FIG. 6 is a detailed flowchart of step S200 in FIG. 5. Please refer to FIG. 3 and FIG. 6. In step S300, the memory control circuit 120 sets the reading mode in the recording block 113, and sets reading from the recording row 310_1. In step S310, the memory control circuit 120 reads the data of the byte 312_1 from the least significant bit LSB of the byte 312_1. In step S320, the memory control circuit 120 determines whether the status of the read data is all "0".

If the data status is not all "0", for example, at least one data status is "1", the memory control circuit 120 executes step S330 to load the address of the byte 312_1 and its data into the register and in step In S250, it is programmed, for example, a one-bit program is performed on the bits whose data status is not "0" in byte 312_1 to record the number of erasures. After step S330, the memory control circuit 120 returns to the flow of FIG. 5 and executes step S210.

If the data status is all “0”, the memory control circuit 120 executes step S340 to determine whether the read byte is the last byte in the record row 310_1. If the read byte is not the last byte in the record column 310_1, the memory control circuit 120 returns to step S310 to read the next byte, that is, the byte 312_2. If the read byte is the last byte in the record row 310_1, the memory control circuit 120 executes step S350 to determine whether the read record row is the last record row 310_M in the record block 113.

If the read record row is not the last record row 310_M in the record block 113, the memory control circuit 120 returns to step S310 to read the first byte of the next record row, for example, the bit of record row 310_2 Tuple 312_3. If the data status is not all “0”, the memory control circuit 120 executes step S330 to load the address of the byte 312_3, its data, and the address of the record upper limit record row into the register. While performing the erasing operation on the target memory block in steps S210 to S240, the erasing operation is performed on the record row 310_1, and the data state of the byte 312_3 is not "0" in step S250. Program one bit to record the number of erases. If the read record row is the last record row 310_M in the record block 113, the memory control circuit 120 executes step S360 to end the setting of reading the data of the byte. After step S360, the memory control circuit 120 returns to the flow of FIG. 5 and executes step S210.

In summary, in the exemplary embodiment of the present invention, the flash memory storage device can automatically record the number of times each well area is erased in its respective recording block. The character string in the record block is additionally provided with character lines in the well area in order to record the number of erasures. A part or all of the coupled memory cells can be used to store the data of the number of erasures. The recorded data can be used for subsequent evaluation of the performance of the flash memory storage device.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧Flash memory storage device

110‧‧‧Memory Cell Array

111_1, 111_2, 111_3, 111_ (N-1), 111_N‧‧‧ memory blocks

112‧‧‧well area

113‧‧‧Record block

120‧‧‧Memory control circuit

310_1, 310_2, 310_3, 310_M‧‧‧ record column

312, 312_1, 312_2, 312_3, 312_4, 312_5‧‧‧ bytes

LSB‧‧‧ Least Significant Bit

MSB‧‧‧Most significant bits S100, S110, S120, S130, S200, S210, S220, S230, S240, S250, S300, S310, S320, S330, S340, S350, S360‧‧‧Method steps

FIG. 1 is a schematic diagram of a flash memory storage device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a well region in the memory cell array of the embodiment shown in FIG. 1. FIG. FIG. 3 is a schematic diagram of a recording block in the embodiment of FIG. 1. FIG. 4 is a flowchart illustrating a method of operating a flash memory storage device according to an embodiment of the invention. FIG. 5 is a flowchart illustrating a method of operating a flash memory storage device according to another embodiment of the present invention. FIG. 6 is a detailed flowchart of step S200 in FIG. 5.

Claims (11)

A flash memory storage device includes: a memory cell array including a plurality of well areas, each well area including a plurality of memory blocks and a recording block; and a memory control circuit coupled to The memory cell array is configured to perform an erase operation on the memory blocks in each well region, and record a number of erase times in each well region in the respective record block. The flash memory storage device according to item 1 of the scope of patent application, wherein the record block includes a plurality of record rows for storing data of the number of erasures, and each record row includes a plurality of bytes. The flash memory storage device according to item 2 of the scope of patent application, wherein the memory control circuit starts from the first record row of the recording block, and sequentially records the data of the erasure number to the recording area. The last record column of the block. The flash memory storage device according to item 3 of the scope of patent application, wherein the memory control circuit starts from the least significant bit of each byte and sequentially records the data of the number of erasures to each of the The most significant bit of a byte. The flash memory storage device according to item 2 of the scope of patent application, wherein the number of erasures recorded in each record row has an upper limit, and the record rows include a first record row and a second record Column, when the number of erasures recorded in the first record column has reached the upper limit of the first record column, the memory control circuit uses the second record column to record the record recorded in the first record column The number of erasures until the number of erasures recorded in the second record column reaches the upper limit of the second record column. The flash memory storage device according to item 5 of the scope of patent application, wherein when the number of erasures recorded in the first record row has reached the upper limit of the first record row, the memory control circuit is in The erasing operation is performed on the first record row during an erasing. The flash memory storage device according to item 6 of the scope of application for a patent, wherein the memory control circuit performs the erase operation on the memory blocks during the erasing operation and simultaneously deletes the first memory block. The record column performs this erasing operation. The flash memory storage device according to item 6 of the scope of patent application, wherein after the erasing operation is performed on the first record row, the memory control circuit re-stores the data of the number of erasures in the erased The first record column. A method for operating a flash memory storage device, wherein the flash memory storage device includes a memory cell array, the memory cell array includes a recording block, and the recording block includes at least one record row. The operation method includes: performing an erase operation on a plurality of memory blocks in the memory cell array, wherein the memory blocks and the recording block are located in a same well area; judging the at least one recording column Whether the number of recorded erasures reaches an upper limit; if the number of erasures recorded in the at least one record column has reached the upper limit, perform the operation on the memory blocks in the memory cell array At the same time as the erasing operation, the erasing operation is performed on the at least one record row; and if the number of erasing times recorded in the at least one record row does not reach the upper limit value, the data of the erasing times is recorded in the at least one In a record column. The operating method according to item 9 of the scope of patent application, wherein the at least one record line includes a first record line and a second record line, and the at least one recorded record of the number of erasing times that has reached the upper limit is at least In the step of performing the erasing operation in a record row, when the number of erasures recorded in the first record row has reached the upper limit of the first record row, the numbers in the memory cell array The memory block performs the erase operation while performing the erase operation on the first record row. The operation method according to item 10 of the scope of patent application, wherein in the step of recording the data of the number of erasures in the at least one record row, after performing the erase operation in the first record row, re-applying The data of the number of erasures is stored in the first record row that is erased.