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TWI676249B - 半導體元件與其製造方法 - Google Patents

半導體元件與其製造方法 Download PDF

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Publication number
TWI676249B
TWI676249B TW106137450A TW106137450A TWI676249B TW I676249 B TWI676249 B TW I676249B TW 106137450 A TW106137450 A TW 106137450A TW 106137450 A TW106137450 A TW 106137450A TW I676249 B TWI676249 B TW I676249B
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TW
Taiwan
Prior art keywords
layer
bump
under
metallurgical
semiconductor wafer
Prior art date
Application number
TW106137450A
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English (en)
Other versions
TW201907534A (zh
Inventor
李韓亐
Han Ul Lee
金鎭洙
Jin Su Kim
高永寬
Young Gwan Ko
Original Assignee
南韓商三星電子股份有限公司
Samsung Electronics Co., Ltd.
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Application filed by 南韓商三星電子股份有限公司, Samsung Electronics Co., Ltd. filed Critical 南韓商三星電子股份有限公司
Publication of TW201907534A publication Critical patent/TW201907534A/zh
Application granted granted Critical
Publication of TWI676249B publication Critical patent/TWI676249B/zh

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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
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Abstract

本發明提供一種半導體元件,包括半導體晶片,具有其上配置有連接墊的主動面;包封體,包封半導體晶片的至少部分;連接構件,配置於半導體晶片的主動面上,並包括電性連接至連接墊的重佈線層;鈍化層,配置於所述連接構件上;以及凸塊下冶金(UBM)層,嵌入鈍化層中並電性連接至連接構件的重佈線層。凸塊下冶金層包括凸塊下冶金墊以及凸塊下冶金通孔,凸塊下冶金墊嵌入鈍化層中並具有凹陷部分,且凸塊下冶金通孔貫穿鈍化層的部分並使連接構件的重佈線層與凸塊下冶金墊彼此電性連接。

Description

半導體元件與其製造方法
本揭露是關於一種半導體元件與其製造方法。
[相關申請案的交叉引用]
本申請案主張2017年7月4日在韓國智慧財產局中申請的韓國專利申請案第10-2017-0085041號的優先權的權益,所述申請案的揭露內容以全文引用的方式併入本文中。
隨著設備規格的提升以及高頻寬記憶體的使用,晶粒至晶粒中介層(die interposer)的市場已經增長。目前,矽(silicon)主要作為中介層的材料,但為了增加面積並減小成本,已經開始發展玻璃或有機的方式。將中介層連接至設備的主板等的連接部分已知為凸塊下冶金(under bump metallurgy,UBM)層,而且由於凸塊下冶金層對於所述連接部分的可靠性有相當大的影響,需要使凸塊下冶金層最佳化。
在根據相關技術領域的中介層中,形成重佈線層 (redistribution layer,RDL),將晶粒附加至重佈線層,進行晶粒模製的封裝製程,令封裝自載體分離,以及凸塊下冶金層藉由形成通孔的製程、曝光製程、電鍍製程等形成在接觸載體的封裝的下表面上。然而,在此情況下,由於封裝中的翹曲(warpage)而難以進行製程。因此,需要進一步使用單獨的載體,且需要建立形成凸塊下冶金層的製程的專屬產線(dedicated line)。另外,由於通過低潔淨度(cleanliness)的封裝產線(package line)的產品會再次通過高潔淨度的曝光製程及電鍍製程,故存在製程品質的風險、良率降低的風險等。
本揭露的一個態樣可提供一種半導體元件,具有能夠經由簡化的製程製造並確保高可靠性的凸塊下冶金層的結構。
根據本揭露的一個態樣,可提供一種半導體元件,其中在連接構件的重佈線層形成之前,藉由將根據相關技術領域中的最後製作凸塊下冶金層方法(UBM layer final method)改成優先製作凸塊下冶金層方法(UBM layer first method),使凸塊下冶金墊的部分嵌入最終封裝結構中的鈍化層以形成凸塊下冶金層。
根據本揭露的一個態樣,半導體元件可包括:半導體晶片,具有其上配置有連接墊的主動面;包封體,包封半導體晶片的至少部分;連接構件,配置於半導體晶片的主動面上,並包括電性連接至連接墊的重佈線層;鈍化層,配置於連接構件上;以 及凸塊下冶金層,嵌入鈍化層中並電性連接至連接構件的重佈線層。凸塊下冶金層包括凸塊下冶金墊以及凸塊下冶金通孔,凸塊下冶金墊嵌入鈍化層中並具有凹陷部分(recess portion),且凸塊下冶金通孔貫穿鈍化層的部分並使連接構件的重佈線層與凸塊下冶金墊彼此電性連接。
根據本揭露的另一個態樣,半導體元件可包括半導體晶片,具有其上配置有連接墊的主動面;包封體,包封半導體晶片的至少部分;連接構件,配置於半導體晶片的主動面上,並包括電性連接至連接墊的重佈線層;鈍化層,配置於連接構件上;凸塊下冶金墊,嵌入鈍化層中並具有凹陷部分;凸塊下冶金通孔,貫穿鈍化層的至少部分並使連接構件的重佈線層與凸塊下冶金墊彼此電性連接;以及連接端子,填充凸塊下冶金墊的凹陷部分。與連接構件的重佈線層接觸的各凸塊下冶金通孔的上表面的寬度大於與個別凸塊下冶金墊接觸的各凸塊下冶金通孔的下表面的寬度。
100‧‧‧半導體元件
111‧‧‧第一半導體晶片
112‧‧‧第二半導體晶片
113‧‧‧第三半導體晶片
111B‧‧‧凸塊
112B‧‧‧凸塊
113B‧‧‧凸塊
111P‧‧‧連接墊
112P‧‧‧連接墊
113P‧‧‧連接墊
115‧‧‧連接構件
120‧‧‧連接構件
121‧‧‧絕緣層
121a‧‧‧第一絕緣層
121b‧‧‧第二絕緣層
122‧‧‧重佈線層
122a‧‧‧第一重佈線層
122b‧‧‧第二重佈線層
122c‧‧‧第三重佈線層
123‧‧‧通孔
123a‧‧‧第一通孔
130‧‧‧鈍化層
131‧‧‧開口
140‧‧‧凸塊下冶金層
142‧‧‧凸塊下冶金墊
142R、142R1、142R2、142R3‧‧‧凹陷部分
143‧‧‧凸塊下冶金通孔
150‧‧‧連接端子
160‧‧‧包封體
170‧‧‧底部填充樹脂
210‧‧‧載體
211‧‧‧核心層
212‧‧‧金屬層
213‧‧‧金屬層
220‧‧‧樹脂層
221‧‧‧開口
230‧‧‧光阻劑
240‧‧‧乾膜
240P‧‧‧圖案
1000‧‧‧電子裝置
1010‧‧‧主板
1020‧‧‧晶片相關組件
1030‧‧‧網路相關組件
1040‧‧‧其他組件
1050‧‧‧相機模組
1060‧‧‧天線
1070‧‧‧顯示裝置
1080‧‧‧電池
1090‧‧‧信號線
1100‧‧‧智慧型電話
1110‧‧‧母板
1101‧‧‧本體
1120‧‧‧電子組件
1130‧‧‧相機模組
2100‧‧‧扇出型半導體元件
2120‧‧‧半導體晶片
2121‧‧‧本體
2122‧‧‧連接墊
2130‧‧‧包封體
2140‧‧‧連接構件
2141‧‧‧絕緣層
2142‧‧‧重佈線層
2143‧‧‧通孔
2150‧‧‧鈍化層
2200‧‧‧扇入型半導體元件
2220‧‧‧半導體晶片
2221‧‧‧本體
2222‧‧‧連接墊
2223‧‧‧鈍化層
2240‧‧‧連接構件
2241‧‧‧絕緣層
2242‧‧‧佈線圖案
2243‧‧‧通孔
2243h‧‧‧通孔孔洞
2250‧‧‧鈍化層
2251‧‧‧開口
2260‧‧‧凸塊下冶金層
2270‧‧‧焊球
2280‧‧‧底部填充樹脂
2290‧‧‧模製材料
2301、2302‧‧‧中介基板
2500‧‧‧主板
A‧‧‧區域
A’‧‧‧區域
A”‧‧‧區域
P‧‧‧表面處理層
下文特舉實施例,並配合所附圖式作詳細說明,本發明的上述及其他態樣、特徵及優點將能更明顯易懂,在所附圖式中:圖1為說明電子裝置系統的實例的方塊示意圖;圖2為說明電子裝置的實例的立體示意圖;圖3A及圖3B為說明扇入型半導體元件在封裝前及封裝後狀 態的剖視示意圖;圖4為說明扇入型半導體元件的封裝製程的剖視示意圖;圖5為說明扇入型半導體元件安裝於中介基板上且最終安裝於電子裝置的主板上之情形的剖視示意圖;圖6為說明扇入型半導體元件嵌入中介基板中且最終安裝於電子裝置的主板上之情形的剖視示意圖;圖7為說明扇出型半導體元件的剖視示意圖;圖8為說明扇出型半導體元件安裝於電子裝置的主板上的情形的剖視示意圖;圖9為說明半導體元件的實例的剖視示意圖;圖10A為說明圖9中半導體元件的A區域的剖視示意圖;圖10B及圖10C為說明圖9中A區域的各種修改後實例的放大剖視示意圖;圖11A及圖11B為說明製造圖9的半導體元件製程的實例的示意圖;圖12為說明圖11A中的製造凸塊下冶金墊的製程的實例的更詳細圖式;圖13A至圖13C為說明圖11B中最終製程的各種更詳細實例的示意圖。
在下文中,將參照所附圖式說明本揭露中的例示性實施例。在所附圖式中,為清晰起見,可誇大或縮小各組件的形狀、尺寸等。
在本揭露中,「下側」、「下部分」、「下表面」等用語用於表示與圖式中剖視圖相對的朝向半導體元件的安裝表面的方向,「上側」、「上部分」、「上表面」等用於表示與前述用語「下側」、「下部分」、「下表面」等相反的方向。然而,這些方向為了方便解釋而定義,專利申請範圍並不受到上述所定義的方向之特別限制。
在說明中組件與另一組件的「連接」的意義包括經由黏合層的間接連接以及在兩個組件之間的直接連接。另外,「電性連接」意為包括物理連接及物理斷接的概念。應理解,當以「第一」及「第二」來指代元件時,所述元件並非由此受到限制。使用「第一」及「第二」可能僅用於將所述元件與其他元件區分開的目的,且可不限制所述元件的順序或重要性。在一些情況下,在不背離本文中所提出的申請專利範圍的條件下,第一元件可被稱作第二元件。相似地,第二元件亦可被稱作第一元件。
本文中所使用的用語「例示性實施例」並不指代同一例示性實施例,而是為強調與另一例示性實施例的特定特徵或特性不同的特定特徵或特性而提供。然而,本文中所提供的例示性實施例被視為能夠藉由彼此整體地或部分地組合而實作。舉例而言,即使並未在另一例示性實施例中說明在特定例示性實施例中說明的一個元件,然而除非在另一例示性實施例中提供了相反或矛盾的說明,否則所述元件亦可被理解為與另一例示性實施例相關的說明。
使用本文中所使用的用語僅為了說明例示性實施例而非限制本揭露。在此情況下,除非在上下文中另有解釋,否則單數形式包括多數形式。
電子裝置
圖1為說明電子裝置系統的實例的方塊示意圖。
參照圖1,電子裝置1000中可容納主板1010。主板1010可包括物理連接或電性連接至其的晶片相關組件1020、網路相關組件1030以及其他組件1040等。這些組件可連接至以下將說明的其他組件,以形成各種訊號線1090。
晶片相關組件1020可包括:記憶體晶片,例如揮發性記憶體(例如動態隨機存取記憶體(dynamic random access memory,DRAM))、非揮發性記憶體(例如唯讀記憶體(read only memory,ROM))、快閃記憶體等;應用處理器晶片,例如中央處理器(例如:中央處理單元(central processing unit,CPU))、圖形處理器(例如:圖形處理單元(graphic processing unit,GPU))、數位訊號處理器、密碼處理器(cryptographic processor)、微處理器、微控制器等;及邏輯晶片,例如類比至數位轉換器(analog-to-digital converter,ADC)、應用專用積體電路(application-specific integrated circuit,ASIC)等。然而晶片相關組件1030不以此為限,亦可包含多種其他無線或有線標準或協定。另外,晶片相關組件1020可彼此組合。
網路相關組件1030可包括例如以下協定:無線保真(wireless fidelity,Wi-Fi)(電氣及電子工程師學會(Institute of Electrical And Electronics Engineers,IEEE)802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access,WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution,LTE)、僅支援資料的演進(evolution data only,Ev-DO)、高速封包存取+(high speed packet access +,HSPA+)、高速下行封包存取+(high speed downlink packet access +,HSDPA+)、高速上行封包存取+(high speed uplink packet access +,HSUPA+)、增強型資料GSM環境(enhanced data GSM environment,EDGE)、全球行動通訊系統(global system for mobile communications,GSM)、全球定位系統(global positioning system,GPS)、通用封包無線電服務(general packet radio service,GPRS)、分碼多重存取(code division multiple access,CDMA)、分時多重存取(time division multiple access,TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications,DECT)、藍芽、3G協定、4G協定、5G協定以及繼上述協定之後指定的任何其他無線協定及有線協定。然而,網路相關組件1030不以此為限,而亦可包括多種其他無線標準或協定或者有線標準或協定。另外,網路相關組件1030可與上述的晶片相關組件1020一起彼此組合。
其他組件1040可包括高頻電感器、鐵氧體電感器(ferrite inductor)、功率電感器(power inductor)、鐵氧體珠粒(ferrite beads)、低溫共燒陶瓷(low temperature co-fired ceramic;LTCC)、電磁干擾(electromagnetic interference;EMI)濾波器、多層陶瓷電容器(multilayer ceramic capacitor;MLCC)等。然而,其他組件1040不以此為限,而亦可包括用於各種其他目的的被動組件等。另外,其他組件1040可與上述的晶片相關組件1020或網路相關組件1030一起彼此組合。
視電子裝置1000的類型,電子裝置1000可包括可物理連接至或電性連接至主板1010的其他組件,或是可不物理連接至或不電性連接至主板1010的其他組件。這些其他組件可包括例如照相機模組1050、天線1060、顯示器裝置1070、電池1080、音訊編解碼器(未繪示)、視訊編解碼器(未繪示)、功率放大器(未繪示)、羅盤(未繪示)、加速度計(未繪示)、陀螺儀(未繪示)、揚聲器(未繪示)、大容量儲存單元(例如硬碟驅動機)(未繪示)、光碟(compact disk,CD)驅動機(未繪示)、數位多功能光碟(digital versatile disk,DVD)驅動機(未繪示)等。然而,這些其他組件不以此為限,而是視電子裝置1000的類型等亦可包括各種用途的其他組件。
電子裝置1000可為智慧型電話、個人數位助理(personal digital assistant,PDA)、數位攝影機、數位照相機(digital still camera)、網路系統、電腦、監視器、平板個人電腦(tablet PC)、筆記型個人電腦、隨身型易網機個人電腦(netbook PC)、電視、視訊遊戲機(video game machine)、智慧型手錶或汽車組件等。 然而,電子裝置1000不以此為限,且可為處理資料的任何其他電子裝置。
圖2為說明電子裝置的實例的立體示意圖。
參照圖2,半導體元件可於上述的電子裝置1000中使用於各種目的。舉例而言,母板1110可容置於智慧型電話1100的本體1101中,且各種電子組件1120可物理連接至或電性連接至母板1110。另外,可物理地連接至或電性連接至母板1110的其他組件,或可不物理連接至或不電性連接至主板1110的其他組件(例如:照相機模組1130)可容置於本體1101中。電子組件1120中的一些電子組件可為晶片相關組件,且半導體元件100可例如為晶片相關組件之中的應用程式處理器,但不以此為限。所述電子裝置不必僅限於智慧型電話1100,而是可為如上所述其他電子裝置。
半導體元件
一般而言,在半導體晶片中整合有許多精密的電路。然而,半導體晶片自身不能充當已完成的半導體產品,且可能因外部物理性或化學性影響而受損。因此,半導體晶片本身無法單獨使用,但可封裝於電子裝置等之中且在電子裝置等中以封裝狀態使用。
此處,由於半導體晶片與電子裝置的主板之間存在電性連接方面的電路寬度差異,因而需要半導體封裝。詳細而言,半 導體晶片的連接墊的尺寸及半導體晶片的連接墊之間的間隔極為精密,但電子裝置中所使用的主板的組件安裝墊的尺寸及主板的組件安裝墊之間的間隔顯著地大於半導體晶片的連接墊的尺寸及間隔。因此,可能難以將半導體晶片直接安裝於主板上,並需要用於緩衝半導體晶片與主板之間的電路寬度差的封裝技術。
視半導體元件的結構及目的,由封裝技術製造的半導體元件可分類為扇入型半導體元件或扇出型半導體元件。
將在下文中參照圖式更詳細地說明扇入型半導體元件及扇出型半導體元件。
扇入型半導體元件
圖3A及圖3B為說明扇入型半導體元件在封裝前及封裝後狀態的剖視示意圖。
圖4為說明扇入型半導體元件的封裝製程的剖視示意圖。
參照圖式,半導體晶片2220可例如是處於裸露狀態下的積體電路(integrated circuit,IC),半導體晶片2220包括:本體2221,包括矽(Si)、鍺(Ge)、砷化鎵(GaAs)等;連接墊2222,形成在本體2221的一個表面上且包括例如鋁(Al)等導電材料;以及鈍化層2223,例如為氧化物膜或氮化物膜等,且形成在本體2221的一個表面上且覆蓋連接墊2222的至少部分。在此情況下,由於連接墊2222在尺寸上是顯著小的,因此難以將積體電路安裝於中級印刷電路板上以及電子裝置的主板等上。
因此,可視半導體晶片2220的尺寸在半導體晶片2220上形成連接構件2240,以重新分佈連接墊2222。可藉由以下步驟來形成連接構件2240:利用例如感光成像介電(photoimagable dielectric,PID)樹脂等絕緣材料在半導體晶片2220上形成絕緣層2241;形成敞開連接墊2222的通孔孔2243h;並接著形成佈線圖案2242及通孔2243。接著,可形成保護連接構件2240的鈍化層2250,可形成開口2251,並可形成凸塊下冶金層2260等。亦即,可藉由一系列的製程來製造包括例如半導體晶片2220、連接構件2240、鈍化層2250及凸塊下冶金層2260的扇入型半導體元件2200。
如上所述,扇入型半導體元件可具有半導體晶片的例如輸入/輸出(input/output,I/O)端子等所有的連接墊均配置於所述半導體晶片內的封裝形式,且可具有優異的電性特性並且可以低成本進行生產。因此,已以扇入型半導體元件的形式製造出安裝於智慧型電話中的許多部件。詳細而言,已開發出安裝於智慧型電話中的許多部件以在具有小型尺寸的同時實施快速訊號傳遞。
然而,由於所有輸入/輸出端子都需要配置於扇入型半導體元件中的半導體晶片內部,因此扇入型半導體元件的空間限制大。因此,難以將此結構應用於具有大量輸入/輸出端子的半導體晶片或具有較小尺寸的半導體晶片。另外,由於上述缺點,扇入型半導體元件無法在電子裝置的主板上直接安裝並使用。原因在於,即使藉由重佈線製程增大半導體晶片的輸入/輸出端子的尺寸 及半導體晶片的輸入/輸出端子之間的間隔,在此情況下,半導體晶片的輸入/輸出端子的尺寸及半導體晶片的輸入/輸出端子之間的間隔可能仍不足以使扇入型半導體元件直接安裝於電子裝置的主板上。
圖5為說明扇入型半導體元件安裝於中介基板上且最終安裝於電子裝置的主板上之情形的剖視示意圖。
圖6為說明扇入型半導體元件嵌入中介基板中且最終安裝於電子裝置的主板上之情形的剖視示意圖。
參照圖式,在扇入型半導體元件2200中,半導體晶片2220的連接墊2222(亦即,輸入/輸出端子)可經由中介基板2301重新分佈,且扇入型半導體元件2200可在其安裝於中介基板2301上的狀態下最終安裝於電子裝置的主板2500上。在此情況下,可藉由底部填充樹脂2280等來固定焊球2270等,且半導體晶片2220的外側可以模製材料2290等覆蓋。或者,扇入型半導體元件2200可嵌入單獨的中介基板2302中,半導體晶片2220的連接墊2222(亦即,輸入/輸出端子)可在扇入型半導體封裝2200嵌入於中介基板2302中的狀態中,由中介基板2302重新分佈,且扇入型半導體元件2200可最終安裝於電子裝置的主板2500上。
如上所述,可能難以直接在電子裝置的主板上安裝及使用扇入型半導體元件。因此,扇入型半導體元件可安裝於單獨的中介基板上,並接著藉由封裝製程安裝於電子裝置的主板上;或者扇入型半導體元件可在扇入型半導體元件嵌入於中介基板中的 狀態下在電子裝置的主板上安裝及使用。
扇出型半導體元件
圖7為說明扇出型半導體元件的剖視示意圖。
參照圖式,在扇出型半導體元件2100中,舉例而言,半導體晶片2120的外側由包封體2130保護,且半導體晶片2120的連接墊2122可藉由連接構件2140而朝向半導體晶片2120之外進行重新佈線。在此情況下,在連接構件2140上可進一步形成鈍化層2150,且在鈍化層2150的開口中可進一步形成凸塊下冶金層2160。在凸塊下冶金層2160上可進一步形成焊球2170。半導體晶片2120可為包括本體2121、連接墊2122、鈍化層(圖中未繪示)等的積體電路。連接構件2140可包括絕緣層2141、形成在絕緣層2141上的重佈線層2142,以及將連接墊2122與重佈線層2142彼此電性連接的通孔2143。
如上所述,扇出型半導體元件可具有其中半導體晶片的輸入/輸出端子經由形成在半導體晶片上的連接構件而重新分佈並朝向半導體晶片之外配置的形式。如上所述,在扇入型半導體元件中,半導體晶片的所有輸入/輸出端子均需要配置於半導體晶片內。因此,當半導體晶片的尺寸減小時,須減小球的尺寸及間距,進而使得標準化球佈局(standardized ball layout)無法在扇入型半導體元件中使用。另一方面,如上所述,所述扇出型半導體元件具有其中半導體晶片的輸入/輸出端子經由形成在半導體晶片上 的連接構件而重新分佈並朝向半導體晶片之外配置的形式。因此,即使在半導體晶片的尺寸減小的情況下,標準化球佈局亦可照樣用於扇出型半導體元件中,使得扇出型半導體元件可安裝於電子裝置的主板上而無需使用單獨的中介基板,如下所述。
圖8為說明扇出型半導體元件安裝於電子裝置的主板上的情形的剖視示意圖。
參照圖式,扇出型半導體元件2100可經由焊球2170等安裝於電子裝置的主板2500上。亦即,如上所述,扇出型半導體元件2100包括連接構件2140,連接構件2140形成在半導體晶片2120上,並能夠將連接墊2122重新分佈至半導體晶片2120外的扇出區域,進而使得實際上可在扇出型半導體元件2100中使用標準化球佈局。因此,扇出型半導體元件2100可在不使用單獨的中介基板等的條件下安裝於電子裝置的主板2500上。
如上所述,由於扇出型半導體元件可安裝於電子裝置的主板上而無需使用單獨的中介基板,因此扇出型半導體元件可在其厚度小於使用中介基板的扇入型半導體元件的厚度的情況下實施。因此,可使扇出型半導體元件小型化且薄化。另外,扇出型半導體元件具有優異的熱特性及電性特性,進而使得扇出型半導體元件尤其適合用於行動產品。因此,扇出型半導體元件可被實作成較使用印刷電路板(PCB)的一般堆疊式封裝(package-on-package,POP)類型的形式更小型(compact)的形式,且可解決因出現翹曲現象而造成的問題。
以下將說明一種半導體元件,其凸塊下冶金層的結構能夠簡化製程並確保高可靠性。
圖9為說明半導體元件的實例的剖視示意圖。
圖10A為說明圖9中半導體元件的A區域的剖視示意圖。
參照圖式,根據本揭露例示性實施例的半導體元件100可包括半導體晶片111、半導體晶片112、半導體晶片113、包封體160、連接構件120、鈍化層130、凸塊下冶金層140以及連接端子150。半導體晶片111、半導體晶片112以及半導體晶片113分別具有其上配置有連接墊111P、連接墊112P以及連接墊113P的主動面,包封體160包封半導體晶片111的至少部分、半導體晶片112的至少部分以及半導體晶片113的至少部分,連接構件120配置於半導體晶片111的主動面、半導體晶片112的主動面以及半導體晶片113的主動面上並包括電性連接至個別的連接墊111P、連接墊112P以及連接墊113P的重佈線層122,鈍化層130配置在連接構件120上,凸塊下冶金層140嵌入鈍化層130中並電性連接至連接構件120的重佈線層122,而連接端子150連接至凸塊下冶金層140。凸塊下冶金層140可包括凸塊下冶金墊142以及凸塊下冶金通孔143,凸塊下冶金墊142嵌入鈍化層130中並具有凹陷部分142R,而凸塊下冶金通孔143嵌入鈍化層130中並使連接構件120的重佈線層122與凸塊下冶金墊142彼此電性連接。連接端子150可填充凹陷部分142R。凸塊下冶金墊142的下表面所配置的水平高度可與鈍化層130的下表面所配置的水平高 度相同。
同時,如上所述,在根據相關技術領域的中介基板中,將重佈線層形成於絕緣層上,將晶粒附加於重佈線層,進行模製晶粒的封裝製程,令封裝自載體分離,以及凸塊下冶金層藉由製程(例如:形成通孔的製程、曝光製程、電鍍製程等)形成在與載體接觸的封裝的下表面上。由於凸塊下冶金層是最後形成,根據相關技術領域的此類方法一般稱為「最後製作凸塊下冶金層方法」(UBM layer final method)。舉例而言,在最後製作凸塊下冶金層方法中,由於封裝中的翹曲,而難以進行製程以形成凸塊下冶金層。因此,需要進一步使用單獨的載體,且需要建立形成凸塊下冶金層製程的專屬產線(dedicated line)。另外,由於通過低潔淨度(cleanliness)的封裝線(package line)的產品再次通過高潔淨度的曝光製程及電鍍製程,故存在製程品質的風險、良率降低的風險等。一般而言,在使用最後製作凸塊下冶金層方法的情況下,凸塊下冶金墊形成在鈍化層上,且凸塊下冶金通孔沿著在鈍化層中所形成的通孔孔洞形成。
同時,根據例示性實施例的半導體元件100可藉由優先製作凸塊下冶金層方法製造,如以下將說明的製程中所見。亦即,在連接構件120形成之前,凸塊下冶金層140以及鈍化層130可形成在形成連接構件120的產線上。因此,不需額外的載體而可省略用於形成凸塊下冶金層的專屬產線,並且可降低封裝製程後外來材質(foreign material)所帶來的風險。在此製程中,凸塊下 冶金層140可嵌入鈍化層130中。因此,凸塊下冶金墊142的下表面所配置的水平高度可與鈍化層130的下表面所配置的水平高度相同。「水平高度相同」意指凸塊下冶金墊142的下表面與鈍化層130的下表面彼此共面。「水平高度實質地相同」意指當因一些製程或測量而可能存在的彎曲(flexion)等被忽略時,鈍化層130的下表面與凸塊下冶金墊142的下表面彼此共面。然而,凸塊下冶金墊142可具有形成在其中的凹陷部分142R。在此情況下,凹陷部分142R可以連接端子150填充,以具有優異的連接可靠性。
同時,在根據例示性實施例的半導體元件100中,與連接構件120的重佈線層122接觸之凸塊下冶金通孔143的上表面的寬度可大於與凸塊下冶金墊142接觸之凸塊下冶金通孔143的下表面的寬度。此處,所述寬度依據剖視圖而決定。在如相關技術領域中使用最後製作凸塊下冶金層方法的情況下,凸塊下冶金通孔的上表面的寬度一般小於凸塊下冶金通孔的下表面的寬度。另一方面,在根據例示性實施例的半導體元件100中,使用優先製作凸塊下冶金層方法,從而凸塊下冶金通孔143可形成為上表面的寬度大於下表面的寬度的倒梯形。另外,由於凸塊下冶金墊142以及凸塊下冶金通孔143的形成方式與連接構件120的重佈線層122以及通孔123的形成方式相同,因此凸塊下冶金通孔143可基本上為填充通孔(filled-via)。
以下將詳細說明根據例示性實施例的半導體元件100所包括的個別組件。
各半導體晶片111、半導體晶片112以及半導體晶片113可例如為處理器晶片,例如中央處理器(例如:中央處理單元(central processing unit,CPU))、圖形處理器(例如:圖形處理單元(graphic processing unit,GPU))、場域可程式閘陣列(field programmable gate array,FPGA)、數位訊號處理器、密碼處理器(cryptographic processor)、微處理器、微控制器等;邏輯晶片,例如類比至數位轉換器(analog-to-digital converter,ADC)、應用專用積體電路(application-specific integrated circuit,ASIC)等;或為記憶體晶片,例如揮發性記憶體(例如:動態隨機存取記憶體(dynamic random access memory,DRAM))、非揮發性記憶體(例如:唯讀記憶體(read only memory,ROM))、快閃記憶體、高頻寬記憶體(high bandwidth memory,HBM)等。另外,上述部件亦可彼此組合並且配置。作為非限制性實例,第一半導體晶片111及第三半導體晶片113可例如為高頻寬記憶體(HBM)等,且第二半導體晶片112可為處理器晶片,例如應用處理器(application processor,AP)。然而,半導體晶片111、半導體晶片112以及半導體晶片113的數量及/或功能不以此為限。半導體元件100可僅包括一個半導體晶片、兩個半導體晶片或包括大於三個半導體晶片。
半導體晶片111、半導體晶片112以及半導體晶片113可為於單一晶片中整合的數百至數百萬個部件或更多的數量設置的積體電路(IC)。在此情況下,半導體晶片的各本體的基礎材料可 為矽(Si)、鍺(Ge)、砷化鎵(GaAs)等。可在各本體中形成各種電路。半導體晶片111的連接墊111P、半導體晶片112的連接墊112P以及半導體晶片113的連接墊113P可使半導體晶片111、半導體晶片112以及半導體晶片113電性連接至其他組件。各連接墊111P、連接墊112P以及連接墊113P的材料可為導電材料,例如鋁(Al)等。暴露連接墊111P、連接墊112P以及連接墊113P的鈍化層可在各本體中形成,且鈍化層可為氧化物膜或氮化物膜等或為氧化物膜及氮化物膜的雙層。絕緣層等可進一步在所需的位置中配置。必要時,重佈線層可進一步形成在半導體晶片111的主動面、半導體晶片112的主動面以及半導體晶片113的主動面上,且分別而言,凸塊111B、凸塊112B以及凸塊113B等亦可連接至連接墊111P、連接墊112P以及連接墊113P。凸塊111B、凸塊112B以及凸塊113B可由金屬或焊料形成。半導體晶片111、半導體晶片112以及半導體晶片113可經由連接墊111P、連接墊112P以及連接墊113P及/或凸塊111B、凸塊112B以及凸塊113B而連接至連接構件120的被暴露的上重佈線層122c,且連接構件115(例如:焊料等)可用於連接。個別的半導體晶片111、半導體晶片112以及半導體晶片113可藉由底部填充樹脂170固定至連接構件120上。
連接構件120可重新分佈半導體晶片111的連接墊111P、半導體晶片112的連接墊112以及半導體晶片113的連接墊113P。各半導體晶片111、半導體晶片112以及半導體晶片113 的數十至數百個具有各種功能的連接墊111P、連接墊112P以及連接墊113P可藉由連接構件120重新分佈,且視所述功能,可經由連接端子150而物理連接或電性連接至外源(external source)。連接構件120可包括絕緣層121、重佈線層122以及通孔123,重佈線層122形成在絕緣層121之上或之中,且通孔123貫穿絕緣層121並使不同的層上所形成的重佈線層122彼此電性連接。連接構件120的層數可大於或小於圖式中所示的數量。具有此形式的連接構件120可作為2.5維度(2.5D)中介層。
舉例而言,絕緣材料可作為各絕緣層121中的材料。在此情況下,所述絕緣材料可為:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺樹脂;熱固性樹脂及熱塑性樹脂與無機填料混合的樹脂,例如味之素構成膜(Ajinomoto Build up Film,ABF)等。或者,感光性絕緣材料(例如:感光成像介電(photoimagable dielectric,PID)樹脂)可作為絕緣材料使用。亦即,各絕緣層121可為感光性絕緣層。當絕緣層121具有感光特性時,可使絕緣層121形成較薄的厚度,且通孔123的精密間距可較容易達成。當絕緣層121為多層時,絕緣層121的材料可為彼此相同,必要時亦可為彼此不同。當絕緣層121為多層時,絕緣層121可視製程而彼此整合,進而使得絕緣層之間的邊界亦可為不明顯。
重佈線層122可用於對連接墊111P、連接墊112P以及連接墊113P實質地進行重新分佈。各重佈線層122的材料可為導電 材料,例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金等。重佈線層122可視其對應層的設計而執行各種功能。舉例而言,重佈線層122可包括接地圖案、電源圖案、訊號圖案等。此處,訊號圖案可包括除了接地圖案、電源圖案等之外的各種訊號,例如資料訊號等。另外,重佈線層122可包括通孔接墊、連接端子接墊等。
通孔123可使不同的層上所形成的重佈線層122彼此電性連接,進而在半導體元件100中產生電性路徑。各通孔123的材料可為導電材料,例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。通孔123可以導電材料完全填充,但不以此為限。
連接構件120可包括第一絕緣層121a、第一重佈線層122a、第二重佈線層122b以及第一通孔123a。第一絕緣層121a接觸鈍化層130。第一重佈線層122a嵌入第一絕緣層121a中並接觸鈍化層130以及凸塊下冶金通孔143。第二重佈線層122b配置於第一絕緣層121a上。而第一通孔123a貫穿第一絕緣層121a的至少部分並使第一重佈線層122a與第二重佈線層122b彼此電性連接。藉由對具有此多層形式的絕緣層、重佈線層以及通孔進行配置而形成連接構件120。與第二重佈線層122b接觸的第一通孔123a的上表面的寬度可大於與第一重佈線層122a接觸的第一通孔123a的下表面的寬度。亦即,連接構件120的通孔123的剖面形狀可與凸塊下冶金通孔143的剖面形狀實質地相同。亦即,通孔 123的剖面形狀可大致為倒梯形。
連接構件120可包括第二絕緣層121b以及第三重佈線層122c,第二絕緣層121b接觸包封體160及/或底部填充樹脂170,而第三重佈線層122c配置於第二絕緣層121b上。第三重佈線層122c可以突出的形式形成在第二絕緣層121b(連接構件120的最頂端絕緣層)的上表面上。第三重佈線層122c可作為用於安裝半導體晶片111、半導體晶片112以及半導體晶片113的接墊。表面處理層P可形成在第三重佈線層122c的表面上。表面處理層P只要為已知相關技術所知即不受特別限制,且可藉由例如電解鍍金、無電鍍金、有機可焊性保護劑(organic solderability preservative,OSP)、或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金(electroless nickel plating/substituted gold plating)、直接浸金(direct immersion gold,DIG)鍍覆、熱空氣焊料均塗(hot air solder leveling,HASL)等製程而形成,但不以此為限。第三重佈線層122c及/或表面處理層P可經由連接構件115(例如:焊料等)而連接至半導體晶片111的連接墊111P、半導體晶片112的連接墊112P以及半導體晶片113的連接墊113P及/或半導體晶片111的凸塊111B、半導體晶片112的凸塊112B以及半導體晶片113的凸塊113B。
鈍化層130可保護連接構件120等不受外部物理或化學損害。鈍化層130的材料不受特別限制。舉例而言,絕緣材料可作為鈍化層130的材料。在此情況下,絕緣材料可為上述連接構 件120的絕緣層121的絕緣材料所說明的材料,例如味之素構成膜(ABF)。
凸塊下冶金層140可改善連接端子150的連接可靠性,進而改善半導體元件100的板級可靠性(board level reliability)。凸塊下冶金層140可包括凸塊下冶金墊142以及凸塊下冶金通孔143,凸塊下冶金墊142嵌入鈍化層130中並具有凹陷部分142R,而凸塊下冶金通孔143嵌入鈍化層130中並使連接構件120的重佈線層122與凸塊下冶金墊142彼此電性連接。連接端子150可填充凹陷部分142R,並可配置以突出在鈍化層130上。凸塊下冶金墊142的下表面所配置的水平高度可與鈍化層130的下表面所配置的水平高度相同或實質地相同。「水平高度相同」意指凸塊下冶金墊142的下表面與鈍化層130的下表面彼此共面。「水平高度實質地相同」意指當因一些製程或測量而可能存在的彎曲(flexion)等被忽略時,鈍化層130的下表面與凸塊下冶金墊142的下表面彼此共面。
與連接構件120的重佈線層122接觸的凸塊下冶金通孔143的上表面的寬度可大於與凸塊下冶金墊142接觸的凸塊下冶金通孔143的下表面的寬度。此處,所述寬度依據剖視圖而決定。在如相關技術領域中使用最後製作凸塊下冶金層方法的情況下,凸塊下冶金通孔的上表面的寬度一般小於凸塊下冶金通孔的下表面的寬度。另一方面,在根據例示性實施例的半導體元件100中,使用優先製作凸塊下冶金層方法,從而凸塊下冶金通孔143可形 成為上表面的寬度大於下表面的寬度的倒梯形。另外,由於凸塊下冶金墊142以及凸塊下冶金通孔143的形成方式與連接構件120的重佈線層122以及通孔123的形成方式相同,因此凸塊下冶金通孔可基本上為填充通孔。凸塊下冶金通孔143的上表面所配置的水平高度可與鈍化層130的上表面所配置的水平高度相同或實質地相同。「水平高度相同」意指凸塊下冶金通孔143的上表面與鈍化層130的上表面彼此共面。「水平高度質實地相同」意指當因一些製程或測量而可能存在的彎曲(flexion)等被忽略時,鈍化層130的上表面與凸塊下冶金通孔143的上表面彼此共面。
連接端子150可外部(externally)物理連接或電性連接半導體元件100。舉例而言,半導體元件100可經由連接端子150安裝於電子裝置的主板上。各連接端子150可由導電材料形成,例如焊料等。然而,此僅為舉例說明,且各連接端子150的材料不以此為限。各連接端子150可為接腳(land)、球、引腳等。連接端子150可形成為多層結構或單層結構。當連接端子150形成為多層結構時,連接端子150可包括銅柱及焊料。當連接端子150形成為單層結構時,連接端子150可包括錫-銀焊料或銅。然而,此僅為舉例說明,連接端子150不以此為限。
連接端子150的數量、間隔或配置等不受特別限制,且可由此項技術領域中具有通常知識者視設計細節而充分修改。舉例而言,根據連接墊111P、連接墊112P以及連接墊113P的數量,連接端子150可設置為數十至數千的數量,且亦可設置為數十至 數千或更多的數量或者數十至數千或更少的數量。連接端子150中至少一者可配置於扇出區域中。扇出區域為半導體晶片111、半導體晶片112以及半導體晶片113所配置的區域以外的區域。亦即,根據例示性實施例的半導體元件100可為扇出型半導體元件。相較於扇入型封裝而言,扇出型封裝可具有優異的可靠性,扇出型封裝可實施多個輸入/輸出端子,且扇出型封裝可有利於三維連接(3D interconnection)。另外,相較於球柵陣列(ball grid array,BGA)封裝、接腳柵陣列(land grid array,LGA)封裝等而言,扇出型封裝可被製造為小的厚度,並可具有價格競爭力。
包封體160可保護半導體晶片111、半導體晶片112以及半導體晶片113等。包封體160的包封形式不受特別限制,且包封體160的包封形式可為包封體160環繞半導體晶片111的至少部分、半導體晶片112的至少部分以及半導體晶片113的至少部分之形式。包封體160的材料不受特別限制。舉例而言,絕緣材料可作為包封體160的材料。在此情況下,所述絕緣材料可為:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺樹脂;熱固性樹脂及熱塑性樹脂與無機填料混合的樹脂,例如味之素構成膜(ABF)等。然而,包封體160的材料不以此為限,而所述材料亦可為包括玻璃纖維的預浸體(prepreg)等。或者,包封體160的材料亦可使用已知的環氧模製化合物(epoxy molding compound,EMC)等。
底部填充樹脂170可將半導體晶片111、半導體晶片112 以及半導體晶片113固定至連接構件120上。包括已知的環氧化物(epoxy)等可作為底部填充樹脂170的材料。必要時,可省略底部填充樹脂170。同時,儘管圖式中未繪示,必要時,被動組件亦可在連接構件120上與半導體晶片111、半導體晶片112以及半導體晶片113並排配置並且封裝。
圖10B及圖10C為說明圖9中A區域的各種修改後實例的A’區域以及A”區域的放大剖視示意圖。
參照圖10B,多個凹陷部分142R1、凹陷部分142R2以及凹陷部分142R3可形成在凸塊下冶金墊142中。所有的凹陷部分142R1、凹陷部分142R2以及凹陷部分142R3可以被連接端子150所填充。在此情況下,凸塊下冶金墊142與連接端子150之間的連接可靠性可因凸塊下冶金墊142與連接端子150之間的界面(interface)增加而進一步獲得改善。
參照圖10C,樹脂層220可進一步配置於鈍化層130上,且敞露凸塊下冶金墊142的下表面的至少部分的開口221可形成在樹脂層220中。凸塊下冶金墊142的下表面可具有相對於樹脂層220的下表面的台階。連接端子150可形成在樹脂層220的開口221中。連接構件120在以下將說明的製程中形成之後,樹脂層220可用於在連接構件120的重佈線層122上進行電氣測試時(electrical test)保持半導體元件100與載體210之間的絕緣,而且當樹脂層不受研磨等時,可能在最終產品中殘留。樹脂層220可例如為包括絕緣樹脂及無機填料的味之素構成膜(ABF),但不 以此為限。形成樹脂層220的材料可與形成鈍化層130的材料相同。在此情況下,樹脂層220與鈍化層130之間的邊界可為不明顯,但不以此為限。
儘管未繪示,當用於形成區域A’的剖視圖中所示的結構依據以下將說明的圖13B的內容進行修改時,圖10B中所示的區域A’的剖視圖中的結構可被修改以具有圖10C的樹脂層220。
圖11A及圖11B為說明圖9中製造半導體元件製程的實例的示意圖。
參照圖式,可優先製備載體210。載體210可包括核心層211以及在核心層211相對兩側的金屬層212,且載體210可進一步包括形成在金屬層212其中一層上的金屬層213。核心層211可例如由包括絕緣樹脂、無機填料以及玻璃纖維的預浸體形成。金屬層212以及金屬層213可包括金屬,例如銅(Cu)、鈦(Ti)等。可在金屬層212與金屬層213之間進行表面處理,以使得金屬層212與金屬層213可易於彼此分離。或者,金屬層212與金屬層213之間可設置釋放層(release layer)。載體210可為一般的拆離核心(detach core)。必要時,樹脂層220亦可形成在載體210上。樹脂層220可用於使載體210與製成的半導體元件100之間電性絕緣。亦即,樹脂層220可用於在連接構件120的重佈線層122上進行電氣測試(electrical test)時保持半導體元件100與載體210之間的絕緣。樹脂層220可藉由膜形式(film form)的層疊而形成或是藉由液態形式的施加或硬化而形成。亦可省略樹脂層220。
接著,可形成鈍化層130以及凸塊下冶金層140,並接著形成連接構件120。亦即,連接構件120、鈍化層130以及凸塊下冶金層140可形成在相同的產線上。凸塊下冶金層140可藉由以下步驟來形成,例如:在樹脂層220上形成晶種層;使用乾膜等形成圖案;使用電鍍製程填充圖案來形成凸塊下冶金墊142;以鈍化層130覆蓋凸塊下冶金墊142;在鈍化層130中形成通孔孔洞;接著使用電鍍製程等填充通孔孔洞來形成凸塊下冶金通孔143。當省略樹脂層220時,可使用載體210的第二金屬層213作為晶種層以形成凸塊下冶金層140。同時,當凸塊下冶金通孔143形成時,連接構件120的第一重佈線層122a(如圖9中所示)可形成在鈍化層130上。亦即,凸塊下冶金層140、連接構件120的重佈線層122(如圖9中所示)以及通孔123(如圖9中所示)可連續形成在相同的產線上。
接著,表面處理層P等可形成於在連接構件120的上部分所形成的第三重佈線層122c上(如圖9中所示)。另外,可進行重佈線層122的四路測試(quad route test)、電氣測試等。接著,可安裝半導體晶片111、半導體晶片112以及半導體晶片113。連接構件115(如圖9中所示),例如焊料等可用於安裝半導體晶片111、半導體晶片112以及半導體晶片113。接著,半導體晶片111、半導體晶片112以及半導體晶片113可藉由底部填充樹脂170而固定。接著,包封半導體晶片111、半導體晶片112以及半導體晶片113的包封體160可形成在連接構件120上。包封體160可藉 由膜形式的層壓而形成或藉由液態型式的施加或硬化而形成。同時,必要時,可在包封體160上進行研磨。半導體晶片111的上表面、半導體晶片112的上表面以及半導體晶片113的上表面可藉由研磨而配置在相同的水平高度上。亦即,半導體晶片111的厚度、半導體晶片112的厚度以及半導體晶片113的厚度可實質地彼此相同。
接著,可分離載體210。可藉由使金屬層212與金屬層213彼此分離而將載體210分離。在此情況下,在分離之後,可藉由蝕刻製程移除金屬層213。在移除載體210之後,可藉由研磨等移除樹脂層220。然而,當省略樹脂層220時,亦可省略研磨。接著,可使用雷射移除填充凸塊下冶金墊142的凹陷部分142R(如圖9中所示)的暫時材料(例如:以下將說明的圖案化光阻劑(patterned photo-resist)),以暴露凹陷部分142R的表面(如圖9中所示)。接著,可進行除膠渣製程(desmear processing)、附加連接端子150至凹陷部分142R的被暴露的表面上(如圖9中所示)、回焊(reflow)等。可經由一系列的製程製造根據例示性實施例的半導體元件100。
圖12為說明圖11A中的製造凸塊下冶金墊的製程的實例的更詳細圖式。
參照圖式,光阻劑230可形成在樹脂層220上。當樹脂層220被省略時,光阻劑230可形成在載體210的金屬層213上。光阻劑230可經由曝光以及顯影(exposure and development)圖 案化為對應於凹陷部分142R的形狀。接著,乾膜240可形成在樹脂層220或形成在金屬層213上(當省略樹脂層220時),且可藉由曝光以及顯影形成用於形成凸塊下冶金墊142的圖案240P。可藉由電鍍填充在乾膜240中所形成的圖案240P,以形成凸塊下冶金墊142。在凸塊下冶金墊142形成之後,可剝離乾膜240。儘管圖式中未繪示,晶種層可在必要時用於電鍍中。同時,可使用另一具有塊狀形式(block form)的材料,(例如鎳(Ni)的金屬等)而非使用圖案化光阻劑230。
圖13A至圖13C為說明圖11B中最終製程的各種更詳細實例的示意圖。
參照圖13A,可藉由蝕刻移除在載體210分離後殘留的金屬層213。接著,可藉由研磨而移除樹脂層220。接著,可使用雷射鑽孔等移除光阻劑230等,以形成凹陷部分142R。接著,可進行除膠渣製程,並且可形成填充凹陷部分142R的連接端子150。在此情況下,最終產品中可能不會有樹脂層220殘留。
參照圖13B,可藉由蝕刻移除在載體210分離後殘留的金屬層213。接著,可使用雷射鑽孔等直接在樹脂層220中形成開口221,而無需進行研磨。上述製程以外的製程與前述的製程實質地相同。在此情況下,在最終產品中,樹脂層220可作為鈍化層130的最外層而保留,且在樹脂層220中所形成的開口221可暴露凸塊下冶金墊142的下表面的至少部分。當樹脂層220的材料與鈍化層130的材料彼此相同時,樹脂層220與鈍化層130之間的 邊界可為不明顯。當使用金屬等形成圖案時,可能需要額外的蝕刻製程。
參照圖13C,可在製程中省略樹脂層220。在此情況下,可對在載體210分離後殘留的金屬層213進行蝕刻,並且可使用直接雷射鑽孔等移除光阻劑230等,無需進行研磨來形成凹陷部分142R。上述製程以外的製程與前述的製程實質地相同。最終產品可實質地與上述使用研磨的情況中的最終產品相同。
如前所述,根據本揭露的例示性實施例,可提供一種半導體元件,其凸塊下冶金層的結構能夠簡化製程並確保高可靠性。
由於半導體元件是以(例如)優先製作凸塊下冶金層方法進行製造,因此可在製程中省略額外的載體,並可省略用於形成凸塊下冶金層的專屬產線,從而可降低封裝製程後外來材質所產生的風險。另外,在最終結構中,凸塊下冶金墊可嵌入鈍化層中並可具有以連接端子填充的凹陷部分,以使得凸塊下冶金墊與連接端子之間的連接可靠性可改善。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾。

Claims (19)

  1. 一種半導體元件,包括:半導體晶片,具有其上配置有連接墊的主動面;包封體,包封所述半導體晶片的至少部分;連接構件,配置於所述半導體晶片的所述主動面上,並包括電性連接至所述連接墊的重佈線層;鈍化層,配置於所述連接構件上;以及凸塊下冶金層,嵌入所述鈍化層中並電性連接至所述連接構件的所述重佈線層,其中所述凸塊下冶金層包括凸塊下冶金墊及凸塊下冶金通孔,所述凸塊下冶金墊嵌入所述鈍化層中,而所述凸塊下冶金通孔貫穿所述鈍化層的部分並使所述連接構件的所述重佈線層與所述凸塊下冶金墊彼此電性連接,且所述凸塊下冶金墊包括自所述凸塊下冶金墊的下表面朝向所述凸塊下冶金通孔凹陷的凹陷部分以及自所述凹陷部分的兩側突出的側壁部分。
  2. 如申請專利範圍第1項所述的半導體元件,進一步包括連接至所述凸塊下冶金層的連接端子,其中所述連接端子填充所述凹陷部分。
  3. 如申請專利範圍第1項所述的半導體元件,其中所述凸塊下冶金墊包括額外一個或更多個凹陷部分。
  4. 如申請專利範圍第1項所述的半導體元件,其中所述凸塊下冶金墊的所述側壁部分的下表面所配置的水平高度與所述鈍化層的下表面所配置的水平高度相同。
  5. 如申請專利範圍第1項所述的半導體元件,進一步包括配置在所述鈍化層上的樹脂層,其中所述樹脂層具有暴露所述凸塊下冶金墊的所述側壁部分的下表面的至少部分的開口。
  6. 如申請專利範圍第5項所述的半導體元件,其中所述凸塊下冶金墊的所述側壁部分的所述下表面具有相對於所述樹脂層的下表面的台階。
  7. 如申請專利範圍第1項所述的半導體元件,其中與所述連接構件的所述重佈線層接觸的所述凸塊下冶金通孔的上表面的寬度大於與所述凸塊下冶金墊接觸的所述凸塊下冶金通孔的下表面的寬度。
  8. 如申請專利範圍第7項所述的半導體元件,其中所述凸塊下冶金通孔為倒梯形的剖面形狀。
  9. 如申請專利範圍第7項所述的半導體元件,其中所述凸塊下冶金通孔為填充通孔。
  10. 如申請專利範圍第1項所述的半導體元件,其中所述凸塊下冶金通孔的上表面所配置的水平高度與所述鈍化層的上表面所配置的水平高度相同。
  11. 如申請專利範圍第1項所述的半導體元件,其中所述半導體晶片包括處理器晶片及記憶體晶片,且所述處理器晶片及所述記憶體晶片經由所述連接構件而彼此電性連接。
  12. 一種半導體元件,包括:半導體晶片,具有其上配置有連接墊的主動面;包封體,包封所述半導體晶片的至少部分;連接構件,配置於所述半導體晶片的所述主動面上並包括電性連接至所述連接墊的重佈線層;鈍化層,配置於所述連接構件上;樹脂層,配置於所述鈍化層上;凸塊下冶金墊,嵌入所述鈍化層中並具有凹陷部分;凸塊下冶金通孔,貫穿所述鈍化層的至少部分並使所述連接構件的所述重佈線層與所述凸塊下冶金墊彼此電性連接;以及連接端子,填充所述凸塊下冶金墊的所述凹陷部分,其中所述樹脂層具有暴露所述凸塊下冶金墊的下表面的至少部分的開口。
  13. 如申請專利範圍第12項所述的半導體元件,其中所述連接構件包括絕緣層,接觸所述鈍化層;第一重佈線層,嵌入所述絕緣層中並接觸所述鈍化層及所述凸塊下冶金通孔;第二重佈線層,配置於所述絕緣層上;以及通孔,貫穿所述絕緣層的至少部分並使所述第一重佈線層與所述第二重佈線層彼此電性連接,且與所述第二重佈線層接觸的各通孔的上表面的寬度大於與所述第一重佈線層接觸的各通孔的下表面的寬度。
  14. 如申請專利範圍第13項所述的半導體元件,其中所述絕緣層的下表面所配置的水平高度與所述第一重佈線層的下表面所配置的水平高度相同。
  15. 一種用於形成半導體元件的方法,所述方法包括:在載體上形成其中部分嵌有凸塊下冶金層的鈍化層;形成所述鈍化層以及所述凸塊下冶金層之前,在所述載體上形成暫時圖案;形成所述凸塊下冶金層的凸塊下冶金墊以完全覆蓋所述暫時圖案;形成絕緣層至所述載體以及所述凸塊下冶金墊上;形成貫穿所述絕緣層的孔洞,以暴露所述凸塊下冶金墊的部分並將所述絕緣層轉換為所述鈍化層,並且以導電材料填充所述孔洞以形成所述凸塊下冶金層的凸塊下冶金通孔;在形成所述鈍化層以及所述凸塊下冶金層之後,在所述鈍化層以及所述凸塊下冶金層上形成包括重佈線層的連接構件;將半導體晶片配置於所述連接構件上,以使得所述半導體晶片的連接墊至少經由所述重佈線層而電性連接至所述凸塊下冶金層;移除所述載體;以及在移除所述載體之後,形成連接端子至所述凸塊下冶金層上。
  16. 如申請專利範圍第15項所述的形成半導體元件的方法,進一步包括在所述載體移除之後移除所述暫時圖案,其中所述連接端子填充所述暫時圖案被移除的空間。
  17. 如申請專利範圍第15項所述的形成半導體元件的方法,進一步包括:在形成所述鈍化層及所述凸塊下冶金層之前,在所述載體上形成樹脂層;以及在移除所述載體之後,移除將所述暫時圖案覆蓋的所述樹脂層的部分以及將所述凸塊下冶金墊的所述下表面的部分覆蓋的所述樹脂層的另一部分,以及將藉由移除所述樹脂層的所述部分而被暴露的所述暫時圖案移除。
  18. 如申請專利範圍第15項所述的形成半導體元件的方法,進一步包括:將所述半導體晶片以包封體進行包封;以及將所述包封體研磨到至少暴露所述半導體晶片的水平高度。
  19. 一種用於形成半導體元件的方法,所述方法包括:在載體上形成樹脂層;在載體上形成其中部分嵌有凸塊下冶金層的鈍化層;在形成所述鈍化層以及所述凸塊下冶金層之後,在所述鈍化層以及所述凸塊下冶金層上形成包括重佈線層的連接構件;將半導體晶片配置於所述連接構件上,以使得所述半導體晶片的連接墊至少經由所述重佈線層而電性連接至所述凸塊下冶金層;移除所述載體;將所述樹脂層研磨,以使得所述鈍化層及所述凸塊下冶金層暴露;以及研磨所述樹脂層之後,形成連接端子至所述凸塊下冶金層上。
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