TWI672007B - Fast channel detection and compensation circuit and communication device using same - Google Patents

Abstract

A fast-path detection and compensation circuit includes an amplifier, a decision feedback equalizer, and a unit impulse response detection unit. The unit is used to generate at least one feedback coefficient according to a unit impulse response to perform a compensation operation on an input data signal. Thus, an inter-symbol interference phenomenon caused by the input data signal due to a transmission channel is eliminated.

Description

Fast-path detection and compensation circuit and communication device using the same

The invention relates to a fast-path detection and compensation circuit, in particular to a fast-path detection and compensation circuit for realizing a high-speed transmission interface circuit.

In high-speed serial data communication, due to the influence of channel attenuation and skin effects, the receiving end data will be subject to severe inter-symbol interference (ISI).

In order to solve the problem of inter-symbol interference, a common method is to compensate channel attenuation by an equalizer at the receiving end of the serial data. For example, a decision feedback equalizer is used to eliminate inter-symbol interference. However, due to the uncertainty of the channel attenuation amplitude and the equalizer's process deviation, the compensation circuit is prone to under- or over-compensation.

Existing compensation modes generally include: method (1) agreement compensation adjustment between the transmitting end and the receiving end after power-on, and method (2) self-adjusting channel compensation based on the least squares method. However, method (1) requires a secondary channel to complete, while method (2) requires complex calculations.

Therefore, there is an urgent need in the art for a novel fast-path detection and compensation circuit.

An object of the present invention is to disclose a fast channel detection and compensation circuit, which can quickly and accurately compensate a channel attenuation effect by quickly obtaining a unit pulse response of a communication channel to adjust a compensation parameter of a decision feedback equalizer.

Another object of the present invention is to disclose a fast channel detection and compensation circuit, which can quickly obtain the unit pulse response of a communication channel to adjust the compensation parameters of a decision feedback equalizer, thereby quickly and accurately eliminating the sign of the data signal. Interference phenomenon.

Another object of the present invention is to disclose a fast channel detection and compensation circuit, which can quickly obtain the unit pulse response of a communication channel to adjust the compensation parameter of a decision feedback equalizer, thereby quickly and accurately correcting the circuit parameter due to the process. The effect of deviations.

Another object of the present invention is to disclose a fast channel detection and compensation circuit, which can turn off a unit impulse response detection unit after one compensation adjustment is completed to save power consumption.

To achieve the foregoing object, a fast-path detection and compensation circuit has been proposed, which has:

An amplifier for performing an amplification operation on an input data signal to generate an input voltage signal, the input data signal is a signal transmitted by a serial data signal through a channel;

A decision feedback equalizer has at least two feedback coefficient input terminals, a first signal input terminal and a data output terminal. The at least two feedback coefficient input terminals are used to receive at least two feedback coefficients. The first The signal input terminal is used to receive the input voltage signal, and the data output terminal is used to provide an output data signal. The decision feedback equalizer generates the output data signal according to the input voltage signal and a compensation voltage signal, and The compensation voltage signal is generated according to a sum of a product of a current voltage value of the output data signal and at least a previous voltage value respectively with a feedback coefficient; and

A unit impulse response detection unit has a second signal input terminal, a sampling clock signal input terminal and at least two feedback coefficient output terminals. The second signal input terminal is used to receive the input voltage signal and the sampling clock signal input. The terminal is used to receive a sampling clock signal, and there is a phase difference between the sampling clock signal and the serial data signal, and the unit impulse response detection unit is used to extract a unit impulse response according to the sampling clock signal to generate The at least two feedback coefficients, and the at least two feedback coefficient output terminals output the at least two feedback coefficients.

In one embodiment, the decision feedback equalizer has:

A first adder for performing a first addition operation on the input voltage signal and the compensation voltage signal to generate a data voltage signal;

A comparator for performing a comparison operation on the data voltage signal to generate the output data signal;

At least one delay unit coupled to the output data signal to generate the current voltage value and the at least one previous voltage value of the output data signal;

At least two amplitude adjustment units for respectively multiplying the current voltage value and the at least one previous voltage value of the output data signal by a feedback coefficient to generate at least two adjustment voltage signals; and

A second adder is configured to perform a second addition operation on the at least two adjusted voltage signals to generate the compensation voltage signal.

In one embodiment, the unit impulse response detection unit has:

A sample-and-hold unit for performing a sample-and-hold operation on the input voltage signal to generate a sample voltage signal according to the sample clock signal;

An analog-to-digital conversion circuit for performing an analog-to-digital conversion operation on the sampling voltage signal to generate a digital signal; and

A feedback coefficient generating unit is configured to generate the at least two feedback coefficients according to the digital signal.

In one embodiment, the feedback coefficient generating unit has:

A digital filter for performing a digital filtering operation on the digital signal to generate the at least two feedback coefficients; and

A memory for temporarily storing the at least two feedback coefficients.

To achieve the foregoing object, a communication device is proposed, which has a fast-path detection and compensation circuit as described above.

In order to enable your reviewers to further understand the structure, characteristics, and purpose of the present invention, drawings and detailed descriptions of the preferred embodiments are attached below.

Since the inter-symbol interference can be represented by the convolution of a communication channel and an original transmitted data signal, a schematic diagram thereof is shown in FIG. 1. Therefore, the present invention performs a phase shift sampling operation on an input data signal to Obtain a channel impulse response, and adjust the working parameters of a decision feedback equalizer according to the channel impulse response to eliminate an inter-symbol interference phenomenon.

Please refer to FIG. 2, which illustrates a block diagram of an embodiment of the fast-path detection and compensation circuit of the present invention.

As shown in FIG. 2, the fast-path detection and compensation circuit of the present invention includes an amplifier 100, a decision feedback equalizer 110, and a unit impulse response detection unit 120.

The amplifier 100 is configured to perform an amplification operation on an input data signal RX_DATA to generate an input voltage signal V _IN , wherein the input data signal RX_DATA is a signal transmitted by a serial data signal (not shown) through a channel.

The decision feedback equalizer 110 has at least two feedback coefficient input terminals, a first signal input terminal and a data output terminal, and has a first adder 111, a comparator 112, at least one delay unit 113, at least Two amplitude adjusting units 114 and a second adder 115.

The at least two feedback coefficient input terminals are used to receive at least two feedback coefficients h _k-1 , h _k-2 , ... h _{k -n} , where k is an integer greater than or equal to 0, n is a positive integer, and Each of the feedback coefficients is a real number; the first signal input terminal is used to receive the input voltage signal V _IN , and the data output terminal is used to provide an output data signal S _D. The decision feedback equalizer is based on The input voltage signal V _IN and a compensation voltage signal V _COMP generate the output data signal S _D , and the compensation voltage signal V _{COMP is} based on the current voltage value of the output data signal S _D and at least one previous voltage value S _D [m -1], S _D [m-2], ... S _D [m-n + 1] are respectively generated by the sum of the products of the feedback coefficients, where m is an integer greater than or equal to 0.

The first adder 111 is configured to perform a first addition operation on the input voltage signal V _IN and the compensation voltage signal V _COMP to generate a data voltage signal V _D.

The comparator 112 is used to perform a comparison operation on the data voltage signal V _D to generate the output data signal S _D.

Said at least one delay unit 113 connected to the output line data signal S _D output coupled to generate the data signal S _D of the current voltage value and the voltage value of the at least one previously _{S D [m-1],} S D [ m-2], ... S _D [m-n + 1].

The at least two amplitude adjustment system 114 for causing the data signal S _D output voltage of the current value and the voltage value of the at least one previously are multiplied with the coefficients to generate a feedback voltage signal to adjust the at least two V _a1 , V _a2 , V _a3 ... V _an .

The second adder 115 is configured to perform a second addition operation on the at least two adjustment voltage signals V _a1 , V _a2 , V _a3, ... V _an to generate the compensation voltage signal V _COMP .

The unit impulse response detection unit 120 has a second signal input terminal, a sampling clock signal input terminal and at least two feedback coefficient output terminals, and has a sample and hold unit 121, an analog-to-digital conversion circuit 122, and a feedback coefficient. A generating unit. The feedback coefficient generating unit may be implemented by a memory 124 or a digital filter 123 and a memory 124.

The second signal input terminal is used to receive the input voltage signal V _IN . The sampling clock signal input terminal is used to receive a sampling clock signal CLK. The sampling clock signal CLK has a phase difference with the serial data signal. And the unit impulse response detection unit 120 is configured to extract a unit impulse response according to the sampling clock signal CLK to generate the at least two feedback coefficients, and cause the at least two feedback coefficient output terminals to output the at least two Feedback coefficients.

The sample and hold unit 121 is configured to perform a sample and hold operation on the input voltage signal according to the sample clock signal CLK to generate a sample voltage signal. The sample clock signal CLK may be generated by a delay phase locked loop or a delay circuit. Generated so that there is a phase difference between the sampling clock signal CLK and the serial data signal. Please refer to FIG. 3, which is a timing diagram of performing a phase shift sampling operation on the input data signal RX_DATA by the sampling clock signal CLK to obtain a unit pulse response.

The analog-to-digital conversion circuit 122 is configured to perform an analog-to-digital conversion operation on the sampling voltage signal to generate a digital signal.

The feedback coefficient generating unit is configured to generate the at least two feedback coefficients according to the digital signal. When the feedback coefficient generating unit is implemented by the digital filter 123 and the memory 124, the digital filter 123 is configured to The digital signal is subjected to a digital filtering operation to generate the at least two feedback coefficients, and the memory 124 is configured to temporarily store the at least two feedback coefficients.

In addition, the aforementioned fast-path detection and compensation circuit can be applied in a communication device to provide an efficient and high-quality high-speed serial data communication performance.

With the design disclosed above, the present invention can provide the following advantages:

1. The fast channel detection and compensation circuit of the present invention can quickly and accurately compensate a channel attenuation effect by quickly obtaining a unit pulse response of a communication channel to adjust a compensation parameter of a decision feedback equalizer.

2. The fast channel detection and compensation circuit of the present invention can quickly obtain the unit pulse response of a communication channel to adjust the compensation parameters of a decision feedback equalizer, thereby quickly and accurately eliminating the intersymbol interference phenomenon of the data signal.

3. The fast-path detection and compensation circuit of the present invention can quickly obtain the unit pulse response of a communication channel to adjust the compensation parameters of a decision feedback equalizer, thereby quickly and accurately correcting the effects of circuit parameters due to process variations.

4. The fast-path detection and compensation circuit of the present invention can turn off a unit impulse response detection unit after one compensation adjustment is completed to save power consumption.

What is disclosed in this case is a preferred embodiment. For example, those who have partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those skilled in the art, do not depart from the scope of patent rights in this case.

To sum up, regardless of the purpose, method and effect, this case is showing its technical characteristics that are quite different from the conventional ones, and its first invention is practical, and it is also in line with the patent requirements of the invention. Granting patents at an early date will benefit society and feel good.

100‧‧‧ amplifier

110‧‧‧ Decision Equalizer

111‧‧‧The first adder

112‧‧‧ Comparator

113‧‧‧Delay Unit

114‧‧‧Amplitude adjustment unit

115‧‧‧Second Adder

120‧‧‧Unit impulse response detection unit

121‧‧‧Sampling and holding unit

122‧‧‧ Analog-to-digital conversion circuit

123‧‧‧Digital Filter

124‧‧‧Memory

FIG. 1 is a schematic diagram showing inter-symbol interference represented by a convolution of a communication channel's impulse response and an original transmitted data signal. FIG. 2 is a block diagram of an embodiment of a fast-path detection and compensation circuit according to the present invention. FIG. 3 is a timing diagram of performing a phase shift sampling operation on the input data signal RX_DATA by the sampling clock signal CLK to obtain a unit pulse response.

Claims (5)

A fast channel detection and compensation circuit includes: an amplifier for performing an amplification operation on an input data signal to generate an input voltage signal, the input data signal being a signal transmitted by a serial data signal through a channel; A decision feedback equalizer has at least one feedback coefficient input terminal, a first signal input terminal and a data output terminal. The at least two feedback coefficient input terminals are used to receive at least two feedback coefficients, the first signal. The input terminal is used to receive the input voltage signal, and the data output terminal is used to provide an output data signal. The decision feedback equalizer is used to perform a first addition operation on the input voltage signal and a compensation voltage signal. To generate a data voltage signal, and perform a comparison operation on the data voltage signal to generate the output data signal, and the compensation voltage signal is based on the current voltage value of the output data signal and at least one previous voltage value separately from one Generated by the sum of products of feedback coefficients; and a unit impulse response detection unit having a second signal output Terminal, a sampling clock signal input terminal and at least two feedback coefficient output terminals, the second signal input terminal is used to receive the input voltage signal, the sampling clock signal input terminal is used to receive a sampling clock signal, the sampling clock There is a phase difference between the signal and the serial data signal, and the unit impulse response detection unit is configured to capture a unit impulse response according to the sampling clock signal to generate the at least two feedback coefficients, and make the at least two feedback coefficients The two feedback coefficient output terminals output the at least two feedback coefficients. The fast-path detection and compensation circuit according to item 1 of the scope of patent application, wherein the decision feedback equalizer has a first adder for performing the first mentioned input voltage signal and the compensated voltage signal. An addition operation to generate the data voltage signal; a comparator for performing the comparison operation on the data voltage signal to generate the output data signal; at least one delay unit coupled to the output data signal to generate the output The current voltage value of the data signal and the at least one previous voltage value; at least two amplitude adjustment units for causing the current voltage value of the output data signal and the at least one previous voltage value to be different from one The feedback coefficients are multiplied to generate at least two adjustment voltage signals; and a second adder is configured to perform a second addition operation on the at least two adjustment voltage signals to generate the compensation voltage signal. According to the fast channel detection and compensation circuit described in the first or second item of the patent application scope, the unit impulse response detection unit has a sample and hold unit for performing a sample and hold on the input voltage signal according to the sampling clock signal. Operations to generate a sampling voltage signal; an analog-to-digital conversion circuit for performing an analog-to-digital conversion operation on the sampling voltage signal to generate a digital signal; and a feedback coefficient generating unit for generating the digital signal based on the digital signal Describe at least two feedback coefficients. The fast-path detection and compensation circuit according to item 3 of the scope of patent application, wherein the feedback coefficient generating unit has: a digital filter for performing a digital filtering operation on the digital signal to generate the at least two feedback coefficients And a memory for temporarily storing the at least two feedback coefficients. A communication device has a fast-path detection and compensation circuit as described in any one of claims 1 to 4 of the scope of patent application.