TWI657648B - Power supply device and power supply system using the same - Google Patents

Abstract

The control device (14) of the stabilized power supply device (1) includes a comparator (35) and a frequency adjustment section (32). The comparator (35) compares a voltage command value (Vir) and a triangle wave signal (Cu). And the gate signals (Au, Bu, ...) of the IGBTs (Q1 to Q6) used to control the converter (6) are generated according to the comparison result, and the frequency adjustment section (32) is based on a DC voltage (Vdc ) Can be set to the range of the reference DC voltage (Vr), and the frequency of the triangular wave signal (Cu) can be adjusted to the lower limit value (fL). Therefore, the switching loss caused by the IGBTs (Q1 to Q6) of the converter (6) can be reduced.

Description

Power supply device and power supply system using the same

The present invention relates to a power supply device and a power supply system, and particularly to a power supply device including a forward converter that converts AC power to DC power, and a power supply system using the power supply device.

For example, Japanese Patent Application Laid-Open No. 2008-92734 (Patent Document 1) discloses a power supply device including a forward converter and a control device. The forward converter includes a plurality of switching elements and converts AC power at a commercial frequency into DC. Electric power, and the control device generates a control signal for controlling a plurality of switching elements according to a comparison result of a sine wave signal of a commercial frequency and a triangle wave signal of a frequency sufficiently higher than the commercial frequency. Each of the plurality of switching elements is turned on (ON) and turned off (OFF) at a frequency corresponding to the value of the frequency of the triangular wave signal.

(Prior technical literature) (Patent Literature)

Patent Document 1: Japanese Patent Application Laid-Open No. 2008-92734

However, in the conventional power supply device, a switching loss occurs every time the switching element is turned on and off, and there is a problem that the efficiency of the power supply device is reduced.

Therefore, the main object of the present invention is to provide a high-efficiency power supply device and a power supply system using the same.

The power supply device of the present invention is provided with a forward converter including a plurality of switching elements and converting AC power at a commercial frequency into DC power. The first control unit is configured to reference the DC voltage and the output DC voltage of the forward converter. It outputs a commercial frequency sine wave signal without deviation. The second control unit compares the level of the sine wave signal and the triangular wave signal with a frequency higher than the commercial frequency. Based on the comparison result, it generates a number of switches to control The control signal of the component; and the frequency adjustment unit adjusts the frequency of the triangular wave signal to a lower limit value within a range where the deviation can be eliminated.

Since the power supply device of the present invention adjusts the frequency of the triangular wave signal to a lower limit within a range that can eliminate the deviation between the reference DC voltage and the output DC voltage of the forward converter, it can turn on and off the number of times of the switching element. Adjust to the lower limit. Therefore, the switching loss caused by the switching element can be minimized, and the efficiency of the power supply device can be improved.

1‧‧‧ stabilized power supply unit

2, 12‧‧‧ electromagnetic contactor

3, 9‧‧‧ current detector

4, 4a, 4b, 4c‧‧‧ capacitors

5, 5a, 5b, 5c‧‧‧ reactor

6, 55‧‧‧ converter

7, 11, 11a, 11b, 11c‧‧‧ capacitors

8, 37, 59‧‧‧ Inverter

10, 10a, 10b, 10c‧‧‧ reactor

13, 66‧‧‧Operation Department

14, 67, 70‧‧‧ control device

15‧‧‧Commercial AC Power

16‧‧‧Load

21‧‧‧reference voltage generating circuit

22‧‧‧Voltage Detector

23, 25‧‧‧ Subtractor

24‧‧‧Output voltage control circuit

26‧‧‧Output current control circuit

27‧‧‧Gate control circuit

31‧‧‧ Judgment

32, 41, 42‧‧‧ Frequency Adjustment Department

33‧‧‧ Oscillator

34‧‧‧Triangular wave generator

35‧‧‧ Comparator

36‧‧‧Buffer

43‧‧‧Switch

45‧‧‧ Bypass AC Power

51, 57‧‧‧ electromagnetic contactor

52, 60‧‧‧ current detector

53, 58, 62‧‧‧ capacitors

54, 61‧‧‧ reactor

56‧‧‧Bidirectional Chopper

63, 65‧‧‧ electromagnetic contactor

64‧‧‧Semiconductor Switch

B0, B1, B2 ‧‧‧ batteries

D1, D2, D3, D4, D5, D6, D11, D12, D13, D14, D15, D16‧‧‧ diode

LD1, LD2‧‧‧Load

Q1, Q2, Q3, Q4, Q5, Q6, Q11, Q12, Q13, Q14, Q15, Q16‧‧‧IGBT

T1, T1a, T1b, T1c, T11‧‧‧ AC input terminals

T2, T2a, T2b, T2c, T14‧‧‧ AC output terminals

T12‧‧‧bypass input terminal

T13‧‧‧battery terminal

U0, U1, U2‧‧‧ Uninterruptible Power Supply Unit

43a‧‧‧First terminal

43b‧‧‧Second terminal

43c‧‧‧common terminal

6a, 6b, 6c‧‧‧ input nodes

8a, 8b, 8c‧‧‧ output nodes

Au, Bu, Av, Bv, Aw, Bw‧‧‧ Gate signals

Cu‧‧‧ triangle wave signal

Ii‧‧‧AC input current

Iif‧‧‧Signal

Io‧‧‧AC output current

Iof‧‧‧ signal

L1, L11, L2‧‧‧ DC line

N1, N2, N11, N12‧‧‧ nodes

NP‧‧‧Neutral point

Vb‧‧‧ Battery voltage

Vdc‧‧‧DC voltage

Vdcf‧‧‧ Signal

Vi‧‧‧AC voltage

Vir‧‧‧ Voltage Command Value

Vo‧‧‧AC output voltage

Vr‧‧‧Reference DC voltage

Xu, Yu, Xv, Yv, Xw, Yw‧‧‧ Gate signals

△ Vdc‧‧‧deviation

31‧‧‧output signal

33‧‧‧Output clock signal

43‧‧‧Signal

FIG. 1 is a circuit block diagram showing a configuration of a stabilized power supply device according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram showing a main part of the stabilized power supply device shown in FIG. 1. FIG.

FIG. 3 is a block diagram showing the configuration of a part related to the control of the converter among the control devices shown in FIG. 1. FIG.

FIG. 4 is a circuit block diagram showing a main part of the gate control circuit shown in FIG. 3.

FIG. 5 is a timing chart illustrating waveforms of a voltage command value, a triangle wave signal, and a gate signal shown in FIG. 4.

Fig. 6 is a circuit block diagram showing a modified example of the first embodiment.

Fig. 7 is a circuit block diagram showing another modification of the first embodiment.

Fig. 8 is a circuit block diagram showing still another modification of the first embodiment.

Fig. 9 is a block diagram showing the structure of a uninterruptible power supply system according to a second embodiment of the present invention.

FIG. 10 is a circuit block diagram showing the configuration of the uninterruptible power supply device U1 shown in FIG.

Fig. 11 is a block diagram showing the structure of a uninterruptible power supply system according to a third embodiment of the present invention.

FIG. 12 is a circuit block diagram showing the structure of the uninterruptible power supply unit U0 shown in FIG. 11.

Embodiment 1

FIG. 1 is a circuit block diagram showing a configuration of a stabilized power supply device 1 according to Embodiment 1 of the present invention. This stabilized power supply device 1 converts three-phase AC power from a commercial AC power source 15 into DC power, and then converts the DC power into stabilized three-phase AC power and supplies it to a load 16. FIG. 1 shows a circuit corresponding to only one of the three phases (U-phase, V-phase, and W-phase) (for example, U-phase) for simplicity of illustration and description.

In FIG. 1, the stabilized power supply device 1 includes an AC input terminal T1, an AC output terminal T2, an electromagnetic contactor 2, 12, a current detector 3, 9, a reactor 5, 10, and a converter. 6, DC line L1, capacitors 4, 7, 11, and inverter (inverter, according to the National Computer Research Institute of the Republic of China computer terminology reference book is called a converter or inverter, sometimes called (Inverter) 8, operation unit 13, and control device 14.

The AC input terminal T1 receives AC power of a commercial frequency from the commercial AC power source 15. The AC output terminal T2 is connected to the load 16. The load 16 is driven by AC power. The electromagnetic contactor 2 and the reactor 5 are connected in series between the AC input terminal T1 and the input node of the converter 6. The capacitor 4 is connected to a node N1 between the electromagnetic contactor 2 and the reactor 5. The electromagnetic contactor 2 is turned on during use of the stabilized power supply device 1, and is turned off during maintenance of the stabilized power supply device 1, for example.

The instantaneous value of the AC input voltage Vi appearing at the node N1 is detected by the control device 14. The current detector 3 detects the AC input current Ii flowing through the node N1, and displays a signal Iif showing the detected value. Transfer to control device 14.

The capacitor 4 and the reactor 5 constitute a low-pass filter, so that commercial-frequency AC power passes from the commercial AC power source 15 to the converter 6 and prevents signals of a switching frequency generated by the converter 6 from passing through the commercial AC power source 15.

The converter 6 is controlled by the control device 14 and converts AC power supplied from the commercial AC power source 15 into DC power and outputs the DC power to the DC line L1. The capacitor 7 is connected to the DC line L1 and smoothes the voltage of the DC line L1. The output voltage of the converter 6 can be controlled to a desired value. The instantaneous value of the DC voltage Vdc appearing on the DC line L1 is detected by the control device 14. The DC line L1 is connected to the input node of the inverter 8.

The inverter 8 is controlled by the control device 14, and converts DC power supplied from the converter 6 via the DC line L1 into AC power of a commercial frequency and outputs the AC power. The output voltage of the inverter 8 can be controlled to a desired value. The output node of the inverter 8 is connected to one terminal of the reactor 10, and the other terminal (node N2) of the reactor 10 is connected to the AC output terminal T2 via the electromagnetic contactor 12. The capacitor 11 is connected to the node N2.

The current detector 9 detects an instantaneous value of the output current Io of the inverter 8 and transmits a signal Iof that displays the detected value to the control device 14. The instantaneous value of the AC output voltage Vo appearing at the node N2 is detected by the control device 14.

The reactor 10 and the capacitor 11 constitute a low-pass filter, so that the commercial frequency AC power generated by the inverter 8 passes through the AC output terminal. The sub-T2 prevents the signal of the switching frequency generated by the inverter 8 from passing through the AC output terminal T2. The inverter 8, the reactor 10, and the capacitor 11 constitute an inverse converter. The electromagnetic contactor 12 is turned on during use of the stabilized power supply device 1, and is turned off during maintenance of the stabilized power supply device 1, for example.

The operation unit 13 includes a plurality of buttons operated by a user of the stabilized power supply device 1, an image display unit that displays various information, and the like. The user can turn on and off the power of the stabilized power supply device 1 or operate the stabilized power supply device 1 manually or automatically by operating the operation unit 13.

The control device 14 controls the entire stabilized power supply device 1 based on a signal from the operation unit 13, an AC input current Ii, a DC voltage Vdc, an AC output current Io, and an AC output voltage Vo. That is, the control device 14 controls the converter 6 such that the DC voltage Vdc forms a reference DC voltage Vr.

In addition, the control device 14 operates based on the output signal Iof of the current detector 9 and compares the magnitude of the output current Io (ie, the load current 1L) of the inverter 8 with a predetermined value lc. When Io> lc, the control device 14 determines that AC power is supplied from the stabilized power supply device 1 to the load 16 and selects a normal operation mode (second operation mode). When Io <lc, the control device 14 determines that the AC power is not supplied to the load 16 by the stabilized power supply device 1 and selects a power saving operation mode (first operation mode).

In addition, when the control device 14 selects the normal operation mode, it compares the level of the sine wave signal of the commercial frequency with the triangle wave signal of the frequency fH which is sufficiently higher than the commercial frequency, and generates a result based on the comparison result. A plurality of gate signals (control signals) of the converter 6 are controlled.

In addition, the control device 14 adjusts the frequency of the triangular wave signal to a lower limit value fL when the DC voltage Vdc can be set to the reference DC voltage Vr when the power-saving operation mode is selected, and compares the sine wave signal of the commercial frequency with the commercial frequency. The level of the triangular wave signal at the frequency fL generates a plurality of gate signals for controlling the converter 6 according to the comparison result.

Fig. 2 is a circuit diagram showing a main part of the stabilized power supply device 1 shown in Fig. 1. Figure 1 shows only the parts related to one of the three-phase AC voltages, and Figure 2 shows the parts related to three-phase. The illustrations of the electromagnetic contactors 2, 12, the operation unit 13, and the control device 14 are omitted.

In FIG. 2, the stabilized power supply device 1 includes: AC input terminals T1a, T1b, T1c, AC output terminals T2a, T2b, T2c, current detectors 7, 9, capacitors 4a, 4b, 4c, 11a, 11b, 11c, reactors 5a, 5b, 5c, 10a, 10b, 10c, converter 6, DC lines L1, L2, and inverter 8.

The AC input terminals T1a, T1b, and T1c respectively receive three-phase AC voltages (U-phase AC voltage, V-phase AC voltage, and W-phase AC voltage) from a commercial AC power source 15 (Figure 1). The AC output terminals T2a, T2b, and T2c output a three-phase AC voltage synchronized with the three-phase AC voltage from the commercial AC power source 15. The load 16 is driven by a three-phase AC voltage from the AC output terminals T2a, T2b, and T2c.

One of the terminals of the reactors 5a, 5b, and 5c is connected to the AC input terminals T1a, T1b, and T1c, respectively. The other terminals are connected to the input nodes 6a, 6b, and 6c of the converter 6, respectively. One electrode system of the capacitors 4a, 4b, and 4c is connected to one terminal of the reactors 5a to 5c, and the other electrode system of the capacitors 4a, 4b, and 4c are connected to the neutral point NP.

The capacitors 4a to 4c and the reactors 5a to 5c constitute a low-pass filter, so that three-phase AC power of commercial frequency passes from the AC input terminals T1a, T1b, T1c through the converter 6, and blocks the switching frequency generated by the converter 6. signal of. The instantaneous value of the AC input voltage Vi appearing at one terminal of the reactor 5a is detected by the control device 14 (FIG. 1). The current detector 7 detects an AC input current Ii flowing through the node N1 (that is, the AC input terminal T1a), and transmits a signal Iif displaying the detected value to the control device 14.

The converter 6 includes IGBTs (Insulated Gate Bipolar Transistors) Q1 to Q6, and diodes D1 to D6. The IGBT system constitutes a switching element. The collectors of IGBTs Q1 to Q3 are all connected to the DC line L1, and the emitters of IGBTs Q1 to Q3 are connected to the input nodes 6a, 6b, and 6c, respectively. The collectors of IGBTs Q4 to Q6 are connected to the input nodes 6a, 6b, and 6c, respectively, and the emitters of IGBTs Q4 to Q6 are connected to the DC line L2. The diodes D1 to D6 are connected in parallel to the IGBTs Q1 to Q6, respectively.

IGBTQ1 and Q4 are controlled by the gate signals Au and Bu, IGBTQ2 and Q5 are controlled by the gate signals Av and Bv, and IGBTQ3 and Q6 are controlled by the gate signals Aw and Bw, respectively. The gate signals Bu, Bv, and Bw are reverse signals of the gate signals Au, Av, and Aw, respectively. number.

IGBTs Q1 to Q3 are turned on when the gate signals Au, Av, and Aw are at the “H” level, and turned off when the gate signals Au, Av, and Aw are at the “L” level. IGBT Q4 to Q6 series gate signals Bu, Bv, Bw are set to ON when the "H" level is set, and gate signals Bu, Bv, Bw are set to "L" level to be turned off.

The gate signals Au, Bu, Av, Bv, Aw, and Bw are each a pulse signal train and are PWM (Pulse Width Modulation) signals. The phases of the gate signals Au and Bu, the phases of the gate signals Av and Bv, and the phases of the gate signals Aw and Bw are each offset by 120 degrees. The gate signals Au, Bu, Av, Bv, Aw, Bw are generated by the control device 14. The method of generating the gate signals Au, Bu, Av, Bv, Aw, and Bw is described later.

For example, when the voltage level of the AC input terminal T1a is higher than the voltage level of the AC input terminal T1b, IGBTs Q1 and Q5 are turned on, and the current is from the AC input terminal T1a via the reactor 5a, IGBTQ1, DC line L1, and capacitor 7 The DC line L2, the IGBT Q5, and the reactor 5b flow to the AC input terminal T1b, and the capacitor 7 is charged to a positive voltage.

In contrast, when the voltage level of the AC input terminal T1b is higher than the voltage level of the AC input terminal T1a, IGBTs Q2 and Q4 are set to be conductive, and the current is from the AC input terminal T1b via the reactor 5b, IGBTQ2, DC line L1, and capacitor 7. The DC line L2, the IGBT Q4, and the reactor 5a flow to the AC input terminal T1a, and the capacitor 7 is charged to a positive voltage. The same is true in other cases.

The gate signals Au, Bu, Av, Bv, Aw, Bw are used to turn on and off each of the IGBTs Q1 to Q6 at a predetermined timing, and the respective on-times of the IGBTs Q1 to Q6 are adjusted, so that they can be applied to the input The three-phase AC voltages of the nodes 6a to 6c are converted into a DC voltage (the voltage between the terminals of the capacitor 7).

The inverter 8 includes IGBTs Q11 to Q16, and diodes D11 to D16. The IGBT system constitutes a switching element. The collectors of IGBTs Q11 to Q13 are all connected to the DC line L1, and the emitters of IGBTs Q11 to Q13 are connected to the output nodes 8a, 8b, and 8c, respectively. The collectors of IGBTs 14 to Q16 are connected to output nodes 8a, 8b, and 8c, respectively, and the emitters of IGBTs 14 to Q16 are connected to DC line L2. The diodes D11 to D16 are connected in parallel to the IGBTs Q11 to Q16, respectively.

IGBTQ11 and Q14 are controlled by the gate signals Xu and Yu respectively, IGBTQ12 and Q15 are controlled by the gate signals Xv and Yv respectively, and IGBTQ13 and Q16 are controlled by the gate signals Xw and Yw respectively. The gate signals Yu, Yv, and Yw are reverse signals of the gate signals Xu, Xv, and Xw, respectively.

IGBT Q11 to Q13 series gate signals Xu, Xv, and Xw are set to ON when the “H” level is set, and gate signals Xu, Xv, and Xw are set to “L” to be turned off. IGBT Q14 to Q16 series gate signals Yu, Yv, and Yw are set to be on when the “H” level is respectively, and gate signals Yu, Yv, and Yw are to be turned off when they are “L”.

The gate signals Xu, Yu, Xv, Yv, Xw, and Yw are each a pulse signal train and a PWM signal. Phase of gate signals Xu, Yu, The phases of the gate signals Xv and Yv and the phases of the gate signals Xw and Yw are each offset by 120 degrees. The gate signals Xu, Yu, Xv, Yv, Xw, and Yw are generated by the control device 14.

For example, when IGBTs Q11 and Q15 are turned on, the positive DC line L1 is connected to the output node 8a via IGBT Q11, and the output node 8b is connected to the negative DC line L2 via IGBT Q15. The positive voltage is output to output node 8a. , 8b.

When the IGBTs Q12 and Q14 are turned on, the positive DC line L1 is connected to the output node 8b via the IGBT Q12, and the output node 8a is the DC line L2 connected to the negative side via the IGBT Q14. The negative voltage is output. To the output nodes 8a, 8b.

At predetermined timing, the gate signals Xu, Yu, Xv, Yv, Xw, and Yw are used to set the IGBTs Q11 to Q16 to the on and off states, respectively, and the respective turn-on timings of the IGBTs Q11 to Q16 are adjusted. The DC voltage between the lines L1 and L2 is converted into a three-phase AC voltage.

One terminal of the reactors 10a to 10c is connected to the output nodes 8a, 8b, and 8c of the inverter 8, respectively, and the other terminal of the reactors 10a to 10c is connected to the AC output terminals T2a, T2b, and T2c, respectively. One electrode system of the capacitors 11a, 11b, and 11c is connected to the other terminals of the reactors 10a to 10c, and the other electrode system of the capacitors 11a, 11b, and 11c are connected to the neutral point NP.

The reactors 10a to 10c and the capacitors 11a, 11b, and 11c constitute a low-pass filter. The commercial frequency three-phase AC power from the inverter 8 passes through the AC output terminals T2a, T2b, and T2c, and blocks the inverter 8 Produce Signal of the switching frequency.

The current detector 9 detects an AC output current Io flowing through the reactor 10a, and applies a signal Iof showing the detected value to the control device 14. The instantaneous value of the AC output voltage Vo appearing at the other terminal (node N2) of the reactor 10a is detected by the control device 14 (FIG. 1).

In addition, the voltage fluctuation rate of the three-phase AC voltage appearing at the AC output terminals T2a, T2b, and T2c is smaller than that of the three-phase AC voltage from the commercial AC power source 15. The voltage fluctuation rate of the AC voltage is displayed, for example, within a fluctuation range of the AC voltage when the rated voltage is used as a reference (100%). The voltage change rate of the AC voltage Vi supplied from the commercial AC power source 15 is ± 10% based on the rated voltage. In contrast, the voltage fluctuation rate of the AC voltage Vo output from the self-stabilizing power supply device 1 is ± 2%.

FIG. 3 is a block diagram showing the configuration of the relevant part of the control of the converter 6 in the control device 14 shown in FIG. In FIG. 3, the control device 14 includes a reference voltage generating circuit 21, a voltage detector 22, subtractors 23 and 25, an output voltage control circuit 24, an output current control circuit 26, and a gate control circuit 27.

The reference voltage generating circuit 21 generates a reference DC voltage Vr. The reference DC voltage Vr is a rated voltage of the voltage between the terminals of the capacitor 7 (that is, a DC voltage between the DC lines L1 and L2) Vdc. The voltage detector 22 detects the instantaneous value of the DC voltage Vdc of the capacitor 7 and outputs a signal Vdcf that displays the detected value. The subtractor 23 obtains a deviation ΔVdc between the reference DC voltage Vr and the output signal Vdcf of the voltage detector 22.

The output voltage control circuit 24 generates a current command value lir by a value proportional to the deviation ΔVdc plus an integral value of the deviation ΔVdc. The subtractor 25 obtains a deviation ΔIi between the current command value lir and the signal Iif from the current detector 3. The output current control circuit 26 generates a voltage command value Vir by adding a value proportional to the deviation ΔIi and an integral value of the deviation ΔIi. The voltage command value Vir is a sine wave signal of a commercial frequency.

The gate control circuit 27 generates gate signals Au, Bu, and IGBTs Q1 to Q6 for controlling the converters 6 based on the voltage command value Vir, the output signal Iif of the current detector 3, and the deviation ΔVdc from the subtractor 23. Av, Bv, Aw, Bw.

FIG. 4 is a circuit block diagram showing a main part of the gate control circuit 27. In FIG. 4, the gate control circuit 27 includes a determiner 31, a frequency adjustment section 32, an oscillator 33, a triangle wave generator 34, a comparator 35, a buffer 36, and an inverter 37.

The determiner 31 operates based on the output signal Iof of the current detector 9 (FIG. 1 and FIG. 2), and compares the magnitude of the output current Io (that is, the load current 1L) of the inverter 8 with a predetermined value lc. And output a signal showing the comparison result 31. When Io> lc, the signal Set 31 to the "L" level and select the normal operation mode (second operation mode). When Io <lc, the signal Set 31 to the "H" level and select the power saving operation mode (first operation mode).

The frequency adjustment section 32 is based on the output signal of the determiner 31 31, and the deviation ΔVdc from the subtractor 23 (FIG. 3) to control the oscillation frequency of the oscillator 33 (that is, the output clock signal of the oscillator 33) 33). The oscillator 33 is, for example, a voltage-controlled oscillator. The oscillation frequency of the oscillator 33 (that is, the output clock signal 33 frequency) can be controlled.

The frequency adjustment section 32 is an output signal from the determiner 31 When 31 is at "L" level (in normal operation mode), the clock signal of oscillator 33 is output The frequency of 33 is set to a predetermined frequency fH (for example, 20 KHz) which is sufficiently higher than a commercial frequency (for example, 60 Hz). In this case, since the IGBTs Q1 to Q6 of the converter 6 are converted at a sufficiently high frequency fH, the response speed of the converter 6 can be made faster. Therefore, even if the load current 1L is larger than the predetermined value lc, the DC voltage Vdc can be set as the reference DC voltage Vr, and the deviation ΔVdc = Vr−Vdc from the subtractor 23 becomes zero.

The frequency adjustment unit 32 is based on the output signal of the determiner 31. When 31 is changed from "L" level to "H" level (from normal operation mode to power saving mode), the output clock signal of the oscillator 33 is changed The frequency of 33 gradually decreases from the frequency fH.

Clock signal When the frequency of 33 is decreased, the switching frequencies of the IGBTs Q1 to Q6 of the converter 6 are reduced, and the response speed of the converter 6 is reduced. Therefore, the response speed of the DC voltage Vdc is set to the reference DC voltage Vr, and the deviation ΔVdc = Vr−Vdc from the subtractor 23 becomes a negative value.

The frequency adjustment unit 32 stops the output clock signal of the oscillator 33 when the deviation ΔVdc becomes a negative predetermined value VM. The frequency of 33 drops. In this case, the deviation ΔVdc becomes zero after a certain delay time has elapsed. When the deviation ΔVdc is reduced more than the negative predetermined value VM, the deviation ΔVdc cannot be set to zero. Therefore, when the frequency adjustment unit 32 is in the power saving mode, The frequency of 33 is adjusted so that the DC voltage Vdc can be set to the lower limit value fL within the range of the reference DC voltage Vr.

The triangle wave generator 34 is the output and the oscillator 33 is the output clock signal. 33 triangular wave signal Cu of the same frequency. The comparator 35 compares the voltage command value Vir from the output current control circuit 26 (FIG. 3) with the level of the triangle wave signal Cu from the triangle wave generator 34, and outputs a gate signal Au showing the comparison result. The buffer 36 applies a gate signal Au to the converter 6. The inverter 37 inverts the gate signal Au to generate a gate signal Bu and applies it to the converter 6.

The gate control circuit 27 generates the gate signals Av and Bv and the gate signals Aw and Bw in the same manner as the gate signals Au and Bu. The phases of the gate signals Au and Bu, the phases of the gate signals Av and Bv, and the phases of the gate signals Aw and Bw are each offset by 120 degrees.

(A), (B), and (C) of FIG. 5 are timing charts showing waveforms of the voltage command value Vir, the triangular wave signal Cu, and the gate signals Au and Bu shown in FIG. As shown in FIG. 5 (A), the voltage command value Vir is a sine wave signal of a commercial frequency. The frequency of the triangular wave signal Cu is higher than the frequency (commercial frequency) of the voltage command value Vir. The peak of the positive side of the triangular wave signal Cu is higher than the peak of the positive side of the voltage command value Vir. The peak value on the negative side of the triangular wave signal Cu is lower than the peak value on the negative side of the voltage command value Vir.

As shown in Figs. 5 (A) and (B), when the level of the triangular wave signal Cu is higher than the voltage command value Vir, the gate signal Au forms the "L" level, and the level of the triangular wave signal Cu is relatively high. When the voltage command value Vir is still low, the gate signal Au forms the "H" level. Gate signal Au system forms positive pulse Signal column.

While the voltage command value Vir is positive, when the voltage command value Vir rises, the pulse amplitude of the gate signal Au increases. While the voltage command value Vir is negative, when the voltage command value Vir decreases, the pulse amplitude of the gate signal Au decreases. As shown in FIGS. 5 (B) and (C), the gate signal Bu forms an inverted signal of the gate signal Au. The gate signals Au and Bu are each a PWM signal.

The waveforms of the gate signals Av and Bv and the gate signals Aw and Bw are the same as those of the gate signals Au and Bu. Among them, the phases of the gate signals Au and Bu, the phases of the gate signals Av and Bv, and the phases of the gate signals Aw and Bw are each shifted by 120 degrees.

It can be known from Fig. 5 (A), (B), (C) that when the frequency of the triangular wave signal Cu is increased, the frequencies of the gate signals Au, Bu, Av, Bv, Aw, and Bw become higher, and IGBTs Q1 to The switching frequency (number of on / off times / second) of Q6 becomes higher. When the switching frequencies of the IGBTs Q1 to Q6 become higher, the switching losses generated by the IGBTs Q1 to Q6 increase, and the efficiency of the stabilized power supply device 1 decreases. Among them, when the switching frequencies of the IGBTs Q1 to Q6 become higher and the load current 1L is larger, the voltage fluctuation rate of the DC voltage Vdc can also be reduced. When the DC voltage Vdc is stable, the voltage change rate of the AC output voltage Vo is reduced, and a high-quality AC output voltage Vo is obtained.

Conversely, when the frequency of the triangular wave signal Cu is reduced, the frequencies of the gate signals Au, Bu, Av, Bv, Aw, and Bw become lower, and the switching frequencies of the IGBTs Q1 to Q6 become lower. When the switching frequencies of IGBTs Q1 to Q6 become lower, the switching losses generated by IGBTs Q1 to Q6 are reduced and stability is improved. Efficiency of the power supply device 1. Among them, when the switching frequencies of the IGBTs Q1 to Q6 become low and the load current 1L is large, the voltage fluctuation rate of the DC voltage Vdc increases. When the DC voltage Vdc fluctuates, the voltage fluctuation rate of the AC output voltage Vo increases, and the waveform of the AC output voltage Vo deteriorates.

In the conventional stabilized power supply device, the frequency of the triangular wave signal Cu is fixed to a frequency fH (for example, 20KHz) sufficiently higher than the commercial frequency (for example, 60Hz), and the voltage fluctuation rate is suppressed to a small value (± 2 %). Therefore, it is possible to drive a load 16 (for example, a computer) having a small allowable range of the voltage fluctuation rate. On the contrary, IGBTs Q1 to Q6 generate a large switching loss and stabilize the efficiency of the power supply device.

However, when the load current 1L is sufficiently small, or when the load 16 is in a standby state and does not consume current, the frequency of the triangular wave signal Cu is set to a frequency fL (for example, 15KHz) lower than the commercial frequency fH described above, and IGBTs Q1 to Q6 reduces switching losses.

Therefore, in the first embodiment, a normal operation mode and a power-saving operation mode are provided. The normal operation mode is one in which the frequency of the triangular wave signal Cu is set to a relatively high frequency fH to reduce the voltage fluctuation rate. In the electric operation mode, the frequency of the triangular wave signal Cu is set to the lower limit value fL in a range where the AC output voltage Vo can be set to the reference AC voltage Vr to reduce the switching loss. When the output current Io of the inverter 8 is larger than the predetermined value lc, the normal operation mode is selected, and when the output current Io of the inverter 8 is smaller than the predetermined value lc, the power-saving operation mode is selected.

The method and operation of using the stabilized power supply device 1 will be described below. First, the self-stabilizing power supply device 1 will be described. A case where AC power should be applied to the load 16 and the output current Io (ie, the load current 1L) is larger than a predetermined value lc. In this case, the electromagnetic contactors 2 and 12 are turned on. The three-phase AC voltage supplied from the commercial AC power source 15 is converted into a DC voltage Vdc by the converter 6.

That is, in the control device 14 (FIG. 3), a reference DC voltage Vr is generated by the reference voltage generating circuit 21, and a signal Vdcf showing a detection value of the DC voltage Vdc is generated by the voltage detector 22. The subtractor 23 generates a deviation ΔVdc between the reference DC voltage Vr and the signal Vdcf, and the current command value lir is generated by the output voltage control circuit 24 based on the deviation ΔVdc. The deviation ΔIi of the current command value lir and the signal Iif from the current detector 3 (FIG. 1 and FIG. 2) is generated by the subtractor 25, and a voltage is generated by the output current control circuit 26 based on the deviation ΔIi. Command value Vir.

In the gate control circuit 27 (FIG. 4), since the output current Io is larger than the predetermined value lc, the output signal of the determiner 31 The 31 series is set to the "L" level and the normal operation mode is selected. When the "L" level is made at 31, a triangle wave signal Cu having a relatively high frequency fH is generated by the frequency adjustment unit 32, the oscillator 33, and the triangle wave generator 34. The voltage command value Vir and the triangular wave signal Cu are compared by the comparator 35, and the gate signals Au and Bu are generated by the buffer 36 and the inverter 37.

In addition, in the gate control circuit 27, the gate signals Av and Bv and the gate signals Aw and Bw are generated in the same manner as the gate signals Au and Bu. In converter 6 (Figure 2), IGBTs Q1 to Q6 are each turned on and off according to the gate signals Au, Bu, Av, Bv, Aw, and Bw. The commercial three-phase AC voltage from the commercial AC power source 15 is converted into a DC voltage Vdc. The DC voltage Vdc is converted into a commercial three-phase AC voltage by the inverter 8 and supplied to the load 16. The load 16 is operated by three-phase AC power supplied from the stabilized power supply device 1.

In this normal operation mode, since IGBTs Q1 to Q6 are turned on and off at a relatively high frequency fH, even when the load current 1L is large, a stable DC voltage Vdc can be generated, and the voltage change rate can be relatively low. Small high-quality AC voltage Vo. Among them, the switching losses generated by the IGBTs Q1 to Q6 become larger, and the efficiency of the stabilized power supply device 1 decreases.

Hereinafter, a case where the load 16 is in a standby state, the self-stabilized power supply device 1 does not supply AC power to the load 16, and the output current Io (that is, the load current 1L) is smaller than a predetermined value lc will be described. In this case, the electromagnetic contactors 2 and 12 are also turned on. The three-phase AC voltage supplied from the commercial AC power source 15 is converted into a DC voltage Vdc by the converter 6.

That is, in the control device 14 (FIG. 3), a reference DC voltage Vr is generated by the reference voltage generating circuit 21, and a signal Vdcf showing a detection value of the DC voltage Vdc is generated by the voltage detector 22. The subtractor 23 generates a deviation ΔVdc between the reference DC voltage Vr and the signal Vdcf, and the current command value lir is generated by the output voltage control circuit 24 based on the deviation ΔVdc. The deviation ΔIi of the current command value lir and the signal Iif from the current detector 3 (FIG. 1 and FIG. 2) is generated by the subtractor 25, and the output current control circuit 26 is used to produce the deviation ΔIi based on the deviation ΔIi. Generate voltage command value Vir.

In the gate control circuit 27 (FIG. 4), since the output current Io is smaller than the predetermined value lc, the output signal of the determiner 31 The 31 series creates the "H" level and selects the power saving operation mode. signal When the “H” level is established at 31, the frequency signal output from the oscillator 33 is output by the frequency adjustment unit 32 The frequency of 33 gradually decreases from the frequency fH.

Clock signal When the frequency of 33 decreases, the response speed of the DC voltage Vdc is set to the reference AC voltage Vr, and the deviation ΔVdc from the subtractor 23 (FIG. 3) becomes negative. When the deviation ΔVo reaches a negative predetermined value VM, the frequency adjustment unit 32 stops the decrease in the oscillation frequency of the oscillator 33. Thereby, the clock signal is made within a range where the AC voltage Vo can be set to the reference AC voltage Vr. The frequency of 33 is set to the lower limit value fL.

Clock signal generated by triangle wave generator 34 33 triangular wave signal Cu of the same frequency fL. The voltage command value Vir and the triangle wave signal Cu are compared by the comparator 35, and the gate signals Au and Bu are generated by the buffer 36 and the inverter 37.

In addition, in the gate control circuit 27, the gate signals Av and Bv and the gate signals Aw and Bw are generated in the same manner as the gate signals Au and Bu. In converter 6 (figure 2), IGBTs Q1 to Q6 are turned on and off according to the gate signals Au, Bu, Av, Bv, Aw, and Bw, respectively, and a three-phase AC voltage of a commercial frequency from a commercial AC power source 15 The system is converted into a DC voltage Vdc. The DC voltage Vdc is converted into a commercial three-phase AC voltage by the inverter 8 and supplied to the load 16. Load 16 series Accepts three-phase AC power and is on standby without consuming current.

In this power-saving operation mode, since the IGBTs Q1 to Q6 are each turned on and off at a relatively low frequency fL, the switching losses generated by the IGBTs Q1 to Q6 are reduced, and the efficiency of the stabilized power supply device 1 is improved.

As described above, in the first embodiment, when the load current 1L is larger than the predetermined value lc, the frequency of the triangular wave signal Cu is set to a relatively high frequency fH, and the load current 1L is smaller than the predetermined value lc. The frequency of the triangular wave signal Cu is set to the lower limit value fL within a range where the DC voltage Vdc can be set to the reference DC voltage Vr. Therefore, when the load 16 is in a standby state that does not consume current, the switching losses generated by the IGBTs Q1 to Q6 of the converter 6 can be reduced, and the efficiency of the stabilized power supply device 1 can be improved.

FIG. 6 is a circuit block diagram showing a modified example of the first embodiment, and is a diagram compared with FIG. 4. In FIG. 6, this modification example is performed by replacing the frequency adjustment unit 32 with the frequency adjustment unit 41. The frequency adjustment unit 41 is based on the output signal of the determiner 31 When the "H" level is established at 31, the output clock signal of the oscillator 33 is monitored while monitoring the deviation ΔVo from the subtractor 23. The frequency of 33 decreases from fH.

Clock signal When the frequency of 33 decreases, the response speed of the DC voltage Vdc is set to the reference DC voltage Vr, and the deviation ΔVdc = Vr-Vdcf from the subtractor 23 becomes a negative value. When the deviation ΔVdc reaches a negative predetermined value Vm, the frequency adjusting section 41 outputs the clock signal of the oscillator 33 The frequency of 33 rises slowly, and when △ Vdc = 0 is formed, the clock signal is stopped. The frequency of 33 rises.

With this, the clock signal The frequency of 33 is set to the lower limit value fL within a range where the DC voltage Vdc can be set to the reference DC voltage Vr. Since other structures and operations are the same as those of the first embodiment, the description thereof will not be repeated. This modification can also obtain the same effect as that of the first embodiment.

FIG. 7 is a circuit block diagram showing another modification of the first embodiment, and is a diagram compared with FIG. 4. In FIG. 7, this modification example is performed by replacing the frequency adjustment unit 32 with the frequency adjustment unit 42. The frequency adjustment section 42 is based on the output signal of the determiner 31 When 31 is falling from the "H" level to the "L" level, the clock signal of the oscillator 33 is output while monitoring the deviation ΔVdc from the subtractor 23. The frequency of 33 rises from fL.

Clock signal When the frequency of 33 is increased, the response speed of the DC voltage Vdc is set to the reference DC voltage Vr, and the deviation ΔVdc = Vr-Vdcf from the subtractor 23 changes from negative to zero. The frequency adjustment unit 41 stops the clock signal when ΔVdc = 0 is formed. The frequency of 33 rises.

With this, the clock signal The frequency of 33 (that is, the frequency of the triangular wave signal Cu) is independent of the magnitude of the load current 1L, and is set to a lower limit value within a range where the DC voltage Vdc can be set to the reference DC voltage Vr. Since other structures and operations are the same as those of the first embodiment, the description thereof will not be repeated. This modification can also obtain the same effect as that of the first embodiment.

FIG. 8 is a circuit block diagram showing still another modification of the first embodiment, and is a diagram compared with FIG. 4. In FIG. 8, this modification is based on the addition of a switch 43 between the determiner 31 and the frequency adjustment unit 32. The first terminal 43a of the switch 43 receives the output signal of the determiner 31 31. The second terminal 43b of the switch 43 receives the signal SE generated by the operation unit 13 (FIG. 1), and the common terminal 43c of the switch 43 is connected to the frequency adjustment unit 32. The user of the stabilized power supply device 1 generates a signal by operating the operation unit 13 43 and signal SE.

The switch 43 is a signal generated by the operation unit 13 43 to control. signal When 43 is at the "H" level, the first terminal 43a and the common terminal 43c of the switch 43 are conducted, and the output signal of the determiner 31 is 31 is applied to the frequency adjustment section 32 via the switch 43. In this case, this modification example is the same as that in the first embodiment.

signal When 43 is at the "L" level, the second terminal 43b and the common terminal 43c of the switch 43 are conducted, and the signal SE from the operation unit 13 is applied to the frequency adjustment unit 32 via the switch 43. When the frequency adjustment unit 32 series signal SE is at the "L" level, the clock signal output from the oscillator 33 is output. The frequency of 33 is set to a relatively high frequency fH.

In addition, when the frequency adjustment unit 32 series signal SE is at the "H" level, the output clock signal of the oscillator 33 is set within a range where the DC voltage Vdc can be set to the reference DC voltage Vr. The frequency of 33 is set to the lower limit value fL.

That is, when the frequency adjustment unit 32 series signal SE is at the "H" level, the load current 1L decreases and the deviation ΔVdc becomes a positive value, while the deviation ΔVdc is being monitored, the frequency of the triangular wave signal Cu is decreased and the deviation Δ When Vdc becomes a negative value VM, the frequency of the triangular wave signal Cu is stopped from decreasing, thereby adjusting the value of the triangular wave signal Cu to a lower limit value.

In addition, when the frequency adjustment unit 32 series signal SE is at the "H" level, the load current 1L increases and the deviation ΔVo becomes a negative value. In the state of the difference ΔVo, the frequency of the triangle wave signal Cu is increased, and when the deviation ΔVdc becomes zero, the frequency of the triangle wave signal Cu is stopped to increase the value of the triangle wave signal Cu to a lower limit value.

This modified example allows the normal operation mode to be selected by operating the operation unit 13 except that the same effect as that of the first embodiment is obtained ( 43 = L, SE = L) and power-saving operation mode ( 43 = L, SE = H), the normal operation mode ( (43 = L, SE = L) means the frequency of the triangular wave signal Cu is set to a relatively high value fH, and the power-saving operation mode ( (43 = L, SE = H) means the frequency of the triangular wave signal Cu is set to the lower limit value fL. Instead of the frequency adjustment section 32, a frequency adjustment section 41 (FIG. 6) or a frequency adjustment section 42 (FIG. 7) may be provided.

Embodiment 2

Fig. 9 is a block diagram showing the structure of a uninterruptible power supply system according to a second embodiment of the present invention. In FIG. 9, the uninterruptible power supply system includes a stabilized power supply device 1, a plurality (two in FIG. 9) of the uninterruptible power supply devices U1, U2, and a plurality (two in this case). B1, B2.

As shown in FIG. 1, the stabilized power supply device 1 includes an AC input terminal T1 and an AC output terminal T2. The AC input terminal T1 receives an AC voltage Vi from a by-pass AC power source 45. The bypass AC power supply 45 is its own generator that outputs AC power, and it can also be a commercial AC power supply.

The stabilized power supply device 1 is the method described in the first embodiment. Once the AC voltage Vi received from the bypass AC power supply 45 is converted into a DC voltage Vdc, the DC voltage Vdc is converted into a commercial frequency. The AC voltage Vo is output to the AC output terminal T2. The voltage change rate (for example, ± 2%) of the AC output voltage Vo is smaller than the voltage change rate (for example, ± 10%) of the AC input voltage Vi.

In addition, the stabilized power supply device 1 is the same as that described in the first embodiment. The output current Io is smaller than the predetermined value lc, and the frequency of the triangular wave signal Cu is adjusted to a range where the DC voltage Vdc can be set to the reference DC voltage Vr. The lower limit value fL reduces the loss caused by the converter 6. In addition, when the output current Io of the stabilized power supply device 1 is larger than the predetermined value lc, the frequency of the triangular wave signal Cu is set to a relatively high value fH, and the DC voltage Vdc is stably maintained at the reference DC voltage Vr.

The uninterruptible power supply devices U1 and U2 each include an AC input terminal T11, a bypass input terminal T12, a battery terminal T13, and an AC output terminal T14. The AC input terminal T11 receives an AC voltage Vi from a commercial AC power source 15 at a commercial frequency. The bypass input terminal T12 is an AC output terminal T2 of the self-stabilizing power supply device 1 and receives an AC voltage Vo.

The battery terminal T13 is connected to the corresponding battery B1 or B2. The batteries B1 and B2 each store DC power. The AC output terminal T14 is connected to the corresponding load LD1 or LD2. The loads LD1 and LD2 are driven by AC power supplied by the uninterruptible power supply devices U1 and U2, respectively.

The uninterruptible power supply unit U1 is normally used to supply AC power from the commercial AC power source 15. Once the AC power from the commercial AC power source 15 is converted into DC power, the DC power is stored in the battery B1 and converted into commercial power. Frequency AC power is supplied to the load LD1.

At this time, once the uninterruptible power supply unit U1 The AC voltage Vi received by the current source 15 is converted into a DC voltage Vdc, and then the DC voltage Vdc is converted into an AC voltage Vo at a commercial frequency and output to the AC output terminal T14. The voltage change rate (for example, ± 2%) of the output AC voltage Vo is smaller than the voltage change rate (for example, ± 10%) of the AC input voltage Vi.

In addition, the uninterruptible power supply device U1 converts the DC power of the battery B1 into AC power of a commercial frequency and supplies it to the load LD1 when the power supply of the AC power from the commercial AC power supply 15 is stopped. Therefore, even when a power failure occurs, the operation of the load LD1 can be continued while the DC power is stored in the battery B1.

In addition, when a failure occurs in the built-in inverter of the uninterruptible power supply device U1, the AC power from the stabilized power supply device 1 is supplied to the load LD1. The uninterruptible power supply unit U2 is also the same as the uninterruptible power supply unit U1.

When the inverters of the uninterruptible power supply devices U1 and U2 are not faulty, since the power supply of the self-stabilizing power supply device 1 to the loads LD1 and LD2 is not performed, the output current Io of the stabilized power supply device 1 is also higher than the predetermined value lc. small. In this case, the converter 6 of the stabilized power supply device 1 is driven by the frequency of the lower limit value fL, and the loss generated by the converter 6 is reduced.

When the inverter of the uninterruptible power supply device U1 (or U2) fails, the AC power is supplied to the load LD1 (or LD2) by the self-stabilizing power supply device 1, so the output current Io of the stabilized power supply device 1 becomes smaller. The predetermined value lc is also large. In this case, the converter 6 of the stabilized power supply device 1 is driven by a higher frequency fH and supplies an AC power with a smaller rate of voltage change. Press Vo to load LD1 (or LD2).

Fig. 10 is a circuit block diagram showing the structure of the uninterruptible power supply unit U1. This uninterruptible power supply device U1 is one that converts three-phase AC power from commercial AC power source 15 to DC power, and then converts this DC power to three-phase AC power and supplies it to load LD1. FIG. 10 shows a circuit corresponding to only one of the three phases (U-phase, V-phase, and W-phase) (for example, U-phase) for simplicity of illustration and description.

In FIG. 10, the uninterruptible power supply device U1 includes an AC input terminal T11, a bypass input terminal T12, a battery terminal T13, and an AC output terminal T14. The AC input terminal T11 receives AC power of a commercial frequency from the commercial AC power source 15. The bypass input terminal T12 is a self-stabilized power supply device 1 that receives AC power at a commercial frequency.

The battery terminal T13 is connected to a battery (power storage device) B1. Battery B1 stores DC power. A capacitor can also be connected instead of battery B1. The AC output terminal T14 is connected to the load LD1. The load LD1 is driven by AC power.

This uninterruptible power supply unit U1 is equipped with electromagnetic contactors 51, 57, 63, 65, current detectors 52, 60, capacitors 53, 58, 62, reactors 54, 61, converters 55, and two-way interceptors 56. , Inverter 59, semiconductor switch 64, operation section 66, and control device 67.

The electromagnetic contactor 51 and the reactor 54 are connected in series between the AC input terminal T11 and the input node of the converter 55. The capacitor 53 is connected to a node N11 between the electromagnetic contactor 51 and the reactor 54. The electromagnetic contactor 51 is turned on when the uninterruptible power supply device U1 is used. For example, it is turned off during maintenance of the uninterruptible power supply unit U1.

The instantaneous value of the AC input voltage Vi appearing at the node N11 is detected by the control device 67. The presence or absence of a power outage is determined based on the instantaneous value of the AC input voltage Vi. The current detector 52 detects an AC input current Ii flowing through the node N11, and applies a signal Iif that displays the detected value to the control device 67.

The capacitor 53 and the reactor 54 constitute a low-pass filter, so that commercial-frequency AC power passes from the commercial AC power source 15 to the converter 55, and prevents signals of a switching frequency generated by the converter 55 from passing through the commercial AC power source 15.

The converter 55 is controlled by the control device 67. When the AC power is normally supplied from the commercial AC power source 15, the AC power is converted into DC power and output to the DC line L11. When the power supply of the AC power from the commercial AC power source 15 is stopped, the operation of the converter 55 is stopped.

Converter 55 has, for example, the same configuration as converter 6 (FIG. 2), and includes six sets of IGBTs and diodes. The output voltage of the converter 55 can be controlled to a desired value. The capacitor 53, the reactor 54, and the converter 55 constitute a forward converter.

The capacitor 58 is connected to the DC line L11 and smoothes the voltage of the DC line L11. The instantaneous value of the DC voltage Vdc appearing on the DC line L11 is detected by the control device 67. The DC line L11 is connected to the high-voltage-side node of the bidirectional clipper 56, and the low-voltage-side node of the bidirectional clipper 56 is connected to the battery terminal T13 via the electromagnetic contactor 57.

The electromagnetic contactor 57 is turned on when the uninterruptible power supply device U1 is in use, and is turned off when the uninterruptible power supply device U1 and the battery B1 are maintained, for example. The instantaneous value of the inter-terminal voltage Vb of the battery B1 appearing at the battery terminal T13 is detected by the control device 67.

The bidirectional interceptor 56 is detected by the control device 67. When the AC power is normally supplied from the commercial AC power source 15, the DC power generated by the converter 55 is stored in the battery B1, and the commercial AC power source is stopped when the When the supply of the AC power of 15 is interrupted, the DC power of the battery B1 is supplied to the inverter 59 via the DC line L11.

When the bidirectional clipper 56 stores DC power in the battery B1, the DC voltage Vdc of the DC line L11 is stepped down and applied to the battery B1. In addition, when the bidirectional clipper 56 supplies the DC power of the battery B1 to the inverter 59, it boosts the voltage Vb between the terminals of the battery B1 and outputs it to the DC line L11. The DC line L11 is connected to an input node of the inverter 59.

The inverter 59 is controlled by the control device 67, and converts DC power supplied from the converter 55 or the bidirectional clipper 56 via the DC line L11 into AC power of a commercial frequency and outputs the AC power. That is, the inverter 59 converts the DC power supplied from the converter 55 via the DC line L11 into AC power at the normal time, and converts the DC power supplied from the battery B1 through the bidirectional chopper 56 during a power failure. Power is converted into AC power. The output voltage of the inverter 59 can be controlled to a desired value. The inverter 59 has the same configuration as the inverter 8 (FIG. 2), and includes six sets of IGBTs and diodes.

The output node of the inverter 59 is connected to one terminal of the reactor 61, and the other terminal (node N12) of the reactor 61 is connected to the AC output terminal T4 via the electromagnetic contactor 63. The capacitor 62 is connected to the node N12.

The current detector 60 detects an instantaneous value of the output current Io of the inverter 59, and applies a signal Iof that displays the detected value to the control device 67. The instantaneous value of the AC output voltage Vo appearing at the node N12 is detected by the control device 67.

The reactor 61 and the capacitor 62 constitute a low-pass filter. The commercial frequency AC power generated by the inverter 59 passes through the AC output terminal T14, and the signal of the switching frequency generated by the inverter 59 is prevented from passing through the AC output terminal T14. . The inverter 59, the reactor 61, and the capacitor 62 constitute an inverse converter.

The electromagnetic contactor 63 is controlled by the control device 67. When the AC power generated by the inverter 59 is supplied to the load LD1, the inverter power supply mode is set to be on, and the AC power from the stabilized power supply device 1 is supplied to the load. LD1 is set to shutdown in bypass power mode.

The semiconductor switch 64 includes a brake fluid and is connected between the bypass input terminal T12 and the AC output terminal T14. The electromagnetic contactor 65 is connected to the semiconductor switch 64 in parallel. The semiconductor switch 64 is controlled by the control device 67, and is normally set to be turned off. When a failure occurs in the inverter 59, it is turned on instantaneously, and the AC power from the stabilized power supply device 1 is supplied to the load LD1. The semiconductor switch 64 is turned off after a predetermined time has elapsed since it was turned on.

The magnetic contactor 65 is turned off when the AC power generated by the inverter 59 is supplied to the load LD1 in the inverter power supply mode, and the AC power from the stabilized power supply device 1 is supplied to the bypass power supply of the load LD1. Set to ON in mode.

In addition, the electromagnetic contactor 65 is turned on when the inverter 59 fails, and supplies AC power from the stabilized power supply device 1 to the load LD1. That is, when the inverter 59 fails, the semiconductor switch 64 is set to be turned on for a predetermined time instantaneously, and the electromagnetic contactor 65 is also set to be turned on. This is to prevent the semiconductor switch 64 from being damaged due to overheating.

The operation unit 66 includes a plurality of buttons operated by a user of the uninterruptible power supply device U1, an image display unit that displays various information, and the like. The user operates the operation unit 66 to set the power source of the uninterruptible power supply device U1 to on and off, or to select one of a bypass power supply mode and an inverter power supply mode.

The control device 67 controls the entire uninterruptible power supply device U1 based on a signal from the operation unit 66, an AC input voltage Vi, an AC input current Ii, a DC voltage Vdc, a battery voltage Vb, an AC output current Io, and an AC output voltage Vo. . That is, the control device 67 detects whether a power failure has occurred based on the detected value of the AC input voltage Vi, and controls the converter 55 and the inverter 59 in synchronization with the phase of the AC input voltage Vi.

In addition, the control device 67 controls the converter 55 such that the DC voltage Vdc becomes the reference DC voltage Vr when the AC power is normally supplied from the commercial AC power source 15, and the supply of the AC power from the commercial AC power source 15 is stopped. When a power failure occurs, the operation of the converter 55 is stopped.

In addition, the control device 67 controls the bidirectional clipper 56 such that the battery voltage Vb becomes the reference battery voltage Vbr at normal time, and controls the bidirectional clipper 56 such that the DC voltage Vdc becomes the reference DC voltage Vr during a power failure. . The control device 67 controls the inverter 59 so that the AC output voltage Vo becomes the reference AC voltage Vor.

The operation of the uninterruptible power supply device U1 will be described below, and the user of the uninterruptible power supply device U1 operates the operation unit 66 to select the inverter power supply mode. When the AC power is normally supplied from the commercial AC power source 15, when the inverter power supply mode is selected, the semiconductor switch 64 and the electromagnetic contactor 65 are turned off, and the electromagnetic contactors 51, 57, 63 are turned on.

The AC power supplied from the commercial AC power source 15 is converted into DC power by a converter 55. The DC power generated by the converter 55 is stored in the battery B1 by the bidirectional clipper 57, and is converted into commercial frequency AC power by the inverter 59 and supplied to the load LD1.

When the supply of AC power from the commercial AC power source 15 is stopped, that is, when a power outage occurs, the operation of the converter 55 is stopped, and the DC power of the battery B1 is supplied to the inverter 59 through the bidirectional chopper 56. . The inverter 59 converts the DC power from the bidirectional clipper 56 into AC power of a commercial frequency and supplies it to the load LD1. Therefore, while the DC power is stored in the battery B1, the operation of the load LD1 can be continued.

In this way, in the inverter power supply mode, when the inverter 59 is not faulty, since the self-stabilizing power supply device 1 does not perform the load to the load LD1. Since the power is supplied, the output current Io of the stabilized power supply device 1 is approximately zero A and is smaller than a predetermined value lc. Therefore, the converter 6 of the stabilized power supply device 1 is driven by the frequency fL having a lower limit value, and the loss generated by the converter 6 is minimized.

In the inverter power supply mode, when the inverter 59 fails, the semiconductor switch 64 is set to be turned on instantaneously, the electromagnetic contactor 63 is set to be turned off, and the electromagnetic contactor 65 is set to be turned on. Accordingly, the AC power from the stabilized power supply device 1 is supplied to the load LD1 via the semiconductor switch 64 and the electromagnetic contactor 65, and the operation of the load LD1 is continued. After a fixed time, the semiconductor switch 64 is set to be turned off to prevent the semiconductor switch 64 from being damaged due to overheating.

In this case, since the stabilized power supply device 1 supplies AC power to the load LD1, the output current Io of the stabilized power supply device 1 becomes larger than a predetermined value lc. Therefore, the converter 6 of the stabilized power supply device 1 borrows It is driven by a relatively high frequency fH and supplies an AC voltage Vo with a small rate of voltage change to the load LD1.

In addition, when the user of the uninterruptible power supply device U1 operates the operation unit 66 to select the bypass power supply mode, it is the same as when the inverter 59 fails in the inverter power supply mode. That is, the electromagnetic contactor 63 and the semiconductor switch 64 are turned off, and the electromagnetic contactor 65 is turned on, and the self-stabilizing power supply device 1 supplies AC power to the load LD1 through the electromagnetic contactor 65. At this time, since the output current Io of the stabilized power supply device 1 becomes larger than the predetermined value lc, the converter 6 of the stabilized power supply device 1 is driven by a relatively high frequency fH and the supply voltage variation rate is small. AC voltage Vo to load LD1.

Since the configuration and operation of the uninterruptible power supply device U2 are the same as those of the uninterruptible power supply device U1, the description thereof will not be repeated. The second embodiment can also obtain the same effects as the first embodiment.

Embodiment 3

FIG. 11 is a block diagram showing the structure of a uninterruptible power supply system according to Embodiment 3 of the present invention, and is a diagram compared with FIG. 9. Referring to FIG. 11, the difference between the uninterruptible power supply system and the uninterruptible power supply system of FIG. 9 is that the stabilized power supply device 1 is replaced with the uninterruptible power supply device U0 and the battery B0.

The uninterruptible power supply device U0 has the functions of both the stabilized power supply device 1 and the uninterruptible power supply device U1. That is, the uninterruptible power supply device U0 includes an AC input terminal T11, a bypass input terminal T12, a battery terminal T13, and an AC output terminal T14. The AC input terminal T11 receives an AC voltage Vi from a commercial AC power source 15 at a commercial frequency. The bypass input terminal T12 receives a commercial frequency AC voltage Vi from the bypass AC power source 45. The battery terminal T13 is connected to the battery B0. Battery B0 stores DC power. The AC output terminal T14 is connected to the bypass input terminal T12 of the uninterruptible power supply devices U1 and U2.

When the uninterruptible power supply unit U0 is supplying AC power from the commercial AC power source 15, once the AC power from the commercial AC power source 15 is converted into DC power, the DC power is stored in the battery B0 and converted into a commercial frequency. The AC power is supplied to the bypass input terminals T12 of the uninterruptible power supply devices U1 and U2.

At this time, once the uninterruptible power supply device U0 converts the AC voltage Vi received from the commercial AC power source 15 into a DC voltage Vdc, the DC voltage Vdc is converted into an AC voltage Vo at a commercial frequency and output to the AC output terminal T14. . The voltage change rate (for example, ± 2%) of the AC output voltage Vo is smaller than the voltage change rate (for example, ± 10%) of the AC input voltage Vi.

In addition, the uninterruptible power supply device U0 converts the DC power of the battery B0 into AC power of a commercial frequency and outputs the AC power to the AC output terminal T14 when the AC power supply from the commercial AC power supply 15 is stopped. Therefore, even when the power failure occurs in the case of the uninterruptible power supply device U1 in the bypass power supply mode, the operation of the load LD1 can be continued while the DC power is stored in the battery B0.

In addition, when the uninterruptible power supply device U0 is a built-in inverter, the AC power from the bypass AC power supply 45 is supplied to the bypass input terminals T12 of the uninterruptible power supply devices U1 and U2.

Furthermore, the uninterruptible power supply device U0 is the same as the stabilized power supply device 1. When the output current Io is smaller than the predetermined value lc, the triangle wave signal Cu is within a range where the DC voltage Vdc can be set to the reference DC voltage Vr. The frequency is adjusted to the lower limit value fL to reduce the loss caused by the converter 55. In addition, when the output current Io is larger than the predetermined value lc, the uninterruptible power supply device U0 sets the frequency of the triangular wave signal Cu to a high value fH, and stably maintains the DC voltage Vdc to the reference DC voltage Vr.

When the inverters 59 of the uninterruptible power supply units U1 and U2 are not faulty, since the uninterruptible power supply units U0 are not applied to the loads LD1 and LD2 The output current Io of the uninterruptible power supply device U0 is smaller than the predetermined value lc. In this case, the converter 55 of the uninterruptible power supply device U0 is driven by the frequency of the lower limit value fL, and the loss generated by the converter 55 is reduced.

When the inverter of the uninterruptible power supply unit U1 (or U2) fails, since the AC power is supplied from the uninterruptible power supply unit U0 to the load LD1 (or LD2), the output current Io of the uninterruptible power supply unit U0 becomes It is larger than the predetermined value lc. In this case, the converter 55 of the uninterruptible power supply device U0 is driven by a relatively high frequency fH, and supplies the AC voltage Vo with a small rate of voltage change to the load LD1 (or LD2).

FIG. 12 is a circuit block diagram showing the structure of the uninterruptible power supply device U0, and is a diagram compared with FIG. 10. Referring to FIG. 12, the difference between the uninterruptible power supply device U0 and the uninterruptible power supply device U1 of FIG. 10 is that the control device 67 is replaced with the control device 70.

The control device 70 performs the same operation as the control device 67. When the output current Io is smaller than the predetermined value lc, the frequency of the triangular wave signal Cu is adjusted to a range where the DC voltage Vdc can be set to the reference DC voltage Vr The lower limit value fL reduces the loss caused by the converter 55. In addition, the control device 70 sets the frequency of the triangular wave signal Cu to a relatively high value fH when the output current Io is larger than the predetermined value lc, and stably maintains the DC voltage Vdc to the reference DC voltage Vr.

Since other structures and operations are the same as those of the second embodiment, the description thereof will not be repeated. The third embodiment can also obtain the same effects as the first embodiment.

In addition, the above-mentioned embodiments 1, 2, 3, and various modification examples may be appropriately combined without dispute.

All aspects of the embodiment disclosed this time are illustrative and not limiting. In addition to the above description, the present invention includes all changes within the meanings and scopes indicated by the scope of the patent application and the scope of the patent application.

Claims (11)

A power supply device includes: a forward converter that includes a plurality of switching elements and converts AC power at a commercial frequency into DC power; a first control unit that uses a reference DC voltage and the output DC voltage of the forward converter to become Output the sine wave signal of the commercial frequency without deviation; the second control unit compares the level of the sine wave signal and the triangle wave signal with a higher frequency than the commercial frequency, and generates a control signal for the complex number based on the comparison result. Control signals of two switching elements; and a frequency adjustment unit that adjusts the frequency of the triangle wave signal to a lower limit value within a range that can eliminate the deviation; the frequency adjustment unit executes the operation selected from the first operation mode and the second operation The first operation mode is one in which the frequency of the triangle wave signal is adjusted to the lower limit value within a range in which the deviation can be eliminated, and the second operation mode is the one in which the triangle wave signal is adjusted. The frequency is set to a predetermined value larger than the lower limit; the power supply device further includes: The converter converts the DC power generated by the forward converter to the AC power of the commercial frequency and supplies it to the load; the current detector detects the load current; and the determiner detects the current of the current detector. When the value is smaller than the predetermined current value, the first operation mode is selected, and when the detection value of the current detector is larger than the predetermined current value, the second operation mode is selected. The power supply device according to item 1 of the scope of patent application, wherein the power supply device further includes an operation portion that selects a desired operation mode among the first and second operation modes. The power supply device according to item 1 of the scope of patent application, wherein the forward converter converts AC power supplied by a commercial AC power source into DC power. When the AC power is normally supplied from the commercial AC power source, The DC power generated by the converter is supplied to the inverse converter and stored in the power storage device. When the power supply of the AC power from the commercial AC power supply is stopped, the DC power of the power storage device is supplied to the foregoing. Inverter. The power supply device according to item 3 of the scope of patent application, wherein the power supply device further includes an electromagnetic contactor that receives the AC power of the aforementioned commercial frequency generated by the aforementioned inverting converter, and a self-bypass AC The AC power of the commercial frequency supplied by the power supply, and when the inverting converter is normal, the AC power from the inverting converter is applied to the load, and when the inverting converter is faulty, the from the bypass The AC power of the AC power source is applied to the aforementioned load. A power supply system is composed of a first power supply device and a second power supply device. The first power supply device includes a first forward converter that converts AC power of a commercial frequency from a commercial AC power source into DC power; and An inverting converter converts DC power into AC power of the aforementioned commercial frequency. When the AC power is normally supplied from the commercial AC power source, the DC power generated by the first forward converter is supplied to the first The inverse converter is stored in the first power storage device. When the power supply of the AC power from the commercial AC power supply is stopped, the DC power of the first power storage device is supplied to the first inverse converter. The second power supply device includes: a second forward converter having a plurality of switching elements and converting the AC power of the commercial frequency into DC power; a second inverting converter that is The generated DC power is converted into AC power of the aforementioned commercial frequency; the first control unit is based on the reference DC voltage and the aforementioned first The output DC voltage of the forward converter outputs the sine wave signal of the aforementioned commercial frequency in a non-deviation manner; the second control unit compares the level of the sine wave signal and the triangle wave signal of a higher frequency than the commercial frequency, and compares them As a result, a control signal for controlling the plurality of switching elements is generated; and a frequency adjusting unit adjusts the frequency of the triangle wave signal to a lower limit value within a range capable of eliminating the deviation, and the first power supply device is normal. When the AC power is supplied from the first inverse converter to the load, and the AC power supply from the second inverse converter to the load is stopped, and when the first power supply device is faulty, the The supply of AC power to the load is stopped, and AC power is supplied to the load from the second inverting converter. The power supply system according to item 5 of the scope of patent application, wherein the frequency adjustment unit executes an operation mode selected from the first operation mode and the second operation mode, and the first operation mode is capable of eliminating the foregoing Within the range of the deviation, the frequency of the triangle wave signal is adjusted to a lower limit value, and the second operation mode is one in which the frequency of the triangle wave signal is set to a predetermined value larger than the lower limit value. The power supply system according to item 6 of the patent application scope, wherein the second power supply device further includes: a current detector that detects an output current of the second inverse converter; and a determiner that is connected to the current detector. The first operation mode is selected when the detection value is smaller than the predetermined current value, and the second operation mode is selected when the detection value of the current detector is larger than the predetermined current value. The power supply system according to item 6 of the scope of patent application, wherein the second power supply device further includes an operation portion that selects a desired operation mode among the first and second operation modes. The power supply system according to item 5 of the scope of patent application, wherein the second forward converter converts AC power of the commercial frequency from a bypass AC power source into DC power. The power supply system according to item 5 of the scope of patent application, wherein the second forward converter converts AC power from the commercial AC power source into DC power. When the AC power is normally supplied from the commercial AC power source, The DC power generated by the second forward converter is supplied to the second inverse converter and stored in a second power storage device. When the power supply of the AC power from the commercial AC power supply is stopped, the second The DC power of the power storage device is supplied to the aforementioned second inverse converter. The power supply system according to item 10 of the patent application scope, wherein the first power supply device further includes a first electromagnetic contactor, and the first electromagnetic contactor includes: a first input node that receives the first inverse converter. The AC power of the aforementioned commercial frequency is generated; the second input node is to receive the AC power of the aforementioned commercial frequency from the aforementioned second power supply device; and the first output node is connected to the aforementioned load; and When it is normal, the first input node is connected to the first output node, and when the first inverting converter is faulty, the second input node is connected to the first output node, and the second power supply device is also Containing a second electromagnetic contactor, the second electromagnetic contactor includes: a third input node that receives the aforementioned commercial frequency AC power generated by the second inverse converter; a fourth input node that receives AC power from a bypass AC power of the aforementioned commercial frequency of the power supply; and a second output node connected to the aforementioned second input node; and When the converter is normal, and the third input node connected to said second output node, while the second inverse transformer to the fault, said fourth input node connected to said second output node.