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TWI651845B - Image sensing module system-in-package and manufacturing method therof - Google Patents

Image sensing module system-in-package and manufacturing method therof Download PDF

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TWI651845B
TWI651845B TW107109369A TW107109369A TWI651845B TW I651845 B TWI651845 B TW I651845B TW 107109369 A TW107109369 A TW 107109369A TW 107109369 A TW107109369 A TW 107109369A TW I651845 B TWI651845 B TW I651845B
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image sensing
redistribution layer
sensing module
metal
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TW201941413A (en
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徐慶銘
張文雄
葉博偉
葉昀鑫
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力成科技股份有限公司
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Abstract

本發明係一種影像感測模組系統級封裝體及其製造方法,該影像感測模組系統級封裝體係包含有一第一重佈線層、複數影像感測器、至少一功能晶片及一封膠體;其中該第一重佈線層的第一、第二表面分別形成有複數的第一及第二接點,以供複數影像感測器分別電性連接於第一接點,而該至少一功能晶片則電性連接於該第二接點,該封膠體則覆蓋於該至少一功能晶片及該第一重佈線層的第二表面;如此,本發明不必使用預先成型的基板來完成影像感測器及其功能晶片的系統級封裝,其尺寸、厚度可更為減縮,而且本發明的該影像感測模組系統級封裝體可包含複數個影像感測器。The invention relates to an image sensing module system-level package body and a manufacturing method thereof. The image sensing module system-level packaging system comprises a first redistribution layer, a plurality of image sensors, at least one functional chip and a colloid The first and second surfaces of the first redistribution layer are respectively formed with a plurality of first and second contacts, wherein the plurality of image sensors are electrically connected to the first contacts, respectively, and the at least one function The wafer is electrically connected to the second contact, and the sealant covers the at least one functional wafer and the second surface of the first redistribution layer; thus, the present invention does not need to use a pre-formed substrate to complete image sensing. The system-level package of the device and its functional chip can be reduced in size and thickness, and the image sensing module system-level package of the present invention can include a plurality of image sensors.

Description

影像感測模組系統級封裝體及其製造方法Image sensing module system-level package and manufacturing method thereof

本發明為一種影像感測模組系統級封裝體及其製造方法,尤指一小型化之影像感測模組系統級封裝體及其製造方法。The invention relates to an image sensing module system-level package and a manufacturing method thereof, in particular to a miniaturized image sensing module system-level package and a manufacturing method thereof.

如圖15所示為現有技術中的一種影像感測模組系統級封裝體70,為使得整體封裝體尺寸縮小,其影像感測器採用晶圓級封裝製程(WLP),使影像感測器71尺寸縮減,再進行另一系統級封裝製程來完影像感測模組系統級封裝體70;於系統級封裝製程中,先準備一影像感測器71、一基板72及一處理器晶片73,再以點膠及迴銲製程分別將該影像感測器71及該處理器晶片73焊接於該基板72的上、下表面,構成一個影像感測模組系統級封裝體70;接著,再於基板72的上表面外側設置有光學鏡片支架80及光學鏡片81,並對準該影像感測器71。FIG. 15 shows an image sensing module system-level package 70 in the prior art. In order to reduce the size of the whole package, the image sensor uses a wafer level packaging process (WLP) to enable the image sensor. 71 is reduced in size, and another system-level packaging process is performed to complete the image sensing module system-level package 70. In the system-level packaging process, an image sensor 71, a substrate 72, and a processor chip 73 are prepared. And soldering the image sensor 71 and the processor chip 73 to the upper and lower surfaces of the substrate 72 to form an image sensing module system-level package 70; and then An optical lens holder 80 and an optical lens 81 are disposed outside the upper surface of the substrate 72, and are aligned with the image sensor 71.

上述影像感測器71雖然以小型化的晶圓級製程製作而縮小尺寸,但在晶圓級封裝製程結束後,尚需準備一預先成型的基板72,進行下一道系統封裝製程,才能將影像感測器71及處理晶片73整合成一影像感測模組系統級封裝體70;因此,目前影像感測模組系統級封裝體70僅包含有單一影像感測器71,對於應用在陣列式相機模組來說,因此一系統級封裝體的整體體積過大,而無法符合日趨小型化的陣列式相機模組中,故有必要進一步改良之。Although the image sensor 71 is reduced in size by a miniaturized wafer level process, after the wafer level packaging process is completed, a pre-formed substrate 72 needs to be prepared for the next system packaging process to image. The sensor 71 and the processing chip 73 are integrated into an image sensing module system-level package 70; therefore, the current image sensing module system-level package 70 only includes a single image sensor 71 for use in an array camera. In terms of modules, the overall size of a system-in-package is too large to meet the increasingly compact array camera module, so further improvements are needed.

有鑑於此,本發明的主要發明目的係提供一種新的影像感測模組系統級封裝體及其製程造方法,以克服目前影像感測模組系統級封裝體的體積過大問題。In view of the above, the main object of the present invention is to provide a new image sensing module system-level package and a manufacturing method thereof, so as to overcome the problem of excessive size of the current image sensing module system-level package.

欲達上述目的所使用的主要技術手段係令該影像感測模組系統級封裝體包含有:The main technical means used to achieve the above purpose is to make the image sensing module system-level package include:

為達到本發明之發明目的,本發明所採用之技術手段為創作一種影像感測模組系統級封裝體,其包含有: 一第一重佈線層,係包含有一本體、複數第一接點、複數金屬連接線及複數第二接點;其中,該些第一接點係外露於該本體之一第一表面,該些第二接點外露於該本體之一第二表面,該些金屬連接線係形成於該本體內,以電性連接該些第一接點及該些第二接點; 複數影像感測器,係分別電性連接所對應的該第一接點; 至少一功能晶片,係電性連接所對應的該複數第二接點;以及 一封膠體,係覆蓋該至少一功能晶片及該第一重佈線層的第二表面。In order to achieve the object of the present invention, the technical means adopted by the present invention is to create an image sensing module system-level package, comprising: a first redistribution layer, comprising a body, a plurality of first contacts, a plurality of metal contacts and a plurality of second contacts; wherein the first contacts are exposed on a first surface of the body, and the second contacts are exposed on a second surface of the body, the metal connections a wire system is formed in the body to electrically connect the first contacts and the second contacts; the plurality of image sensors are respectively electrically connected to the corresponding first contacts; at least one functional chip And the plurality of second contacts corresponding to the electrical connection; and a glue covering the at least one functional wafer and the second surface of the first redistribution layer.

由上述說明可知,本發明的影像感測模組系統級封裝體本不必使用預先成型的基板來完成影像感測器及其功能晶片的系統級封裝,故其尺寸、厚度可更為減縮,加上本發明的該影像感測模組系統級封裝體可包含複數個影像感測器,可符合小型化的陣列式相機模組應用。It can be seen from the above description that the image sensing module system-level package of the present invention does not need to use a pre-formed substrate to complete the system-level packaging of the image sensor and its functional chip, so the size and thickness thereof can be further reduced. The image sensing module system-level package of the present invention can include a plurality of image sensors, which can conform to the miniaturized array camera module application.

為達到本發明之另一發明目的,本發明所採用之技術手段為影像感測模組系統級封裝體的製造方法,其包含有以下步驟: (a) 提供一載板; (b) 於該載板上形成一重佈線層;其中該重覆線層的本體內包含有複數金屬連接線,再於該重佈線層之本體的第二表面形成複數第二接點,該些第二接點係與該些金屬連接線電性連接並外露於該第二表面; (c) 令複數功能晶片與該些第二接點電性連接; (d) 形成一封膠體,以覆蓋該至少一功能晶片及該重佈線層的第二表面; (e) 移除該載板,使部分金屬連接線外露於該重佈線層之本體的第一表面,以形成複數第一接點; (f) 將複數影像感測器分別電性連接至對應的該些第一接點;以及 (g) 切割出複數影像感測模組系統級封裝體;其中各該影像感測模組系統級封裝體係包含多個影像感測晶片及至少一功能晶片。In order to achieve another object of the present invention, the technical means adopted by the present invention is a method for manufacturing an image sensing module system-level package, which comprises the following steps: (a) providing a carrier board; (b) Forming a redistribution layer on the carrier; wherein the body of the repetitive layer includes a plurality of metal connection lines, and forming a plurality of second contacts on the second surface of the body of the rewiring layer, the second contacts Electrically connecting with the metal connecting wires and exposing to the second surface; (c) electrically connecting the plurality of functional wafers to the second contacts; (d) forming a gel to cover the at least one functional wafer And the second surface of the redistribution layer; (e) removing the carrier, exposing a portion of the metal connection line to the first surface of the body of the redistribution layer to form a plurality of first contacts; (f) The image sensor is electrically connected to the corresponding first contacts; and (g) the plurality of image sensing module system-level packages are cut out; wherein the image sensing module system-level packaging system comprises multiple The image sensing chip and the at least one functional wafer.

由上述說明可知,本發明係於同一道晶圓級製程中完成該影像感測模組系統級封裝體的製造,不使用預先成型的基板來完成影像感測器及其功能晶片的系統級封裝,故整體尺寸、厚度可更為減縮,加上本發明的該影像感測模組系統級封裝體可包含複數個影像感測器,可符合小型化的陣列式相機模組應用。It can be seen from the above description that the present invention completes the manufacture of the image sensing module system-level package in the same wafer level process, and does not use the pre-formed substrate to complete the system-level packaging of the image sensor and its functional chip. Therefore, the overall size and thickness can be further reduced. In addition, the image sensing module system-level package of the present invention can include a plurality of image sensors, which can conform to the miniaturized array camera module application.

以下配合圖式及本發明之實施例,進一步闡述本發明為達成預定發明目的所採取的技術手段,其中圖式已被簡化以僅為了說明目的,而通過描述本發明的元件和組件之間的關係來說明本發明的結構或方法 發明,因此,圖中所示的元件不以實際數量、實際形狀、實際尺寸以及實際比例呈現,尺寸或尺寸比例已被放大或簡化,藉此提供更好的說明,已選擇性地設計和配置實際數量、實際形狀或實際尺寸比例,而詳細的元件佈局可能更複雜。The technical means adopted by the present invention for achieving the intended purpose of the invention are further illustrated in the following description of the embodiments of the invention, wherein the drawings have been simplified for illustrative purposes only, and by describing between the elements and components of the invention The relationship is to illustrate the structure or method invention of the present invention, and therefore, the elements shown in the drawings are not presented in actual number, actual shape, actual size, and actual scale, and the size or size ratio has been enlarged or simplified, thereby providing better Note that the actual quantity, actual shape, or actual size ratio has been selectively designed and configured, and the detailed component layout may be more complicated.

請參閱圖1所示,本發明之影像感測模組系統級封裝體1係包含有一第一重佈線層10、複數影像感測器20、至少一功能晶片30及一封膠體40。Referring to FIG. 1 , the image sensing module system package 1 of the present invention includes a first redistribution layer 10 , a plurality of image sensors 20 , at least one functional wafer 30 , and a gel 40 .

上述該第一重佈線層10包含有一本體11、複數第一接點12、複數金屬連接線14及複數第二接點13;其中,該些第一接點12係外露於該本體11之一第一表面101,該些第二接點13外露於該本體11之一第二表面102,該些金屬連接線14係形成於該本體11內,以電性連接該些第一接點12及該些第二接點13;此外,該第一重佈線層10進一步包含有複數第三接點15,該些第三接點15係外露於該本體11的第一表面101,並透過該些金屬連接線14與該些第二接點13電性連接。各該第一接點12可進一步形成有一金屬凸塊121,以凸出於該本體11的第一表面101,各該第三接點15可進一步形成有一金屬凸塊151,以凸出於該本體11的第一表面101,各該第二接點13可進一步形成有一金屬凸塊131,以凸出於該本體11的第二表面102,該些金屬凸塊121、151、131可為銅、鎳、金三層金屬凸塊,但不以此為限;此外,該第一接點12及該第三接點15亦可直接外露於該第一表面101,並與該第一表面101共平面(圖中未示),且該第二接點13亦可直接外露於該第二表面102,並與該第二表面102共平面(圖中未示)。於本實施例中,該本體11材料為聚合物介電材料(Polymer dielectric material)。The first redistribution layer 10 includes a body 11 , a plurality of first contacts 12 , a plurality of metal connection lines 14 , and a plurality of second contacts 13 . The first contacts 12 are exposed to one of the bodies 11 . a first surface 101, the second contacts 13 are exposed on the second surface 102 of the body 11. The metal connecting wires 14 are formed in the body 11 to electrically connect the first contacts 12 and The second contact layer 13 further includes a plurality of third contacts 15 exposed on the first surface 101 of the body 11 and through the plurality of contacts The metal connecting wires 14 are electrically connected to the second contacts 13 . Each of the first contacts 12 may further be formed with a metal bump 121 protruding from the first surface 101 of the body 11. Each of the third contacts 15 may further be formed with a metal bump 151 to protrude therefrom. The first surface 101 of the body 11 and each of the second contacts 13 may further be formed with a metal bump 131 protruding from the second surface 102 of the body 11. The metal bumps 121, 151, and 131 may be copper. And a three-layer metal bump of nickel or gold, but not limited thereto; the first contact 12 and the third contact 15 may also be directly exposed on the first surface 101, and the first surface 101 A common plane (not shown), and the second contact 13 can also be directly exposed on the second surface 102 and coplanar with the second surface 102 (not shown). In this embodiment, the body 11 material is a polymer dielectric material.

上述複數影像感測器20係設於該第一重佈線層10的第一表面101,並分別與位在該第一重佈線層10的第一表面101上所對應的該第一接點12的金屬凸塊121電性連接。於本實施例中,各該影像感測器20係包含有一影像感測晶片21、一透光蓋板22、一第二重佈線層23、多個金屬柱24及一膠框25;其中該影像感測晶片21包含有一主動面210、一背面212及複數矽穿孔213。該主動面210包含有一影像感測區211及複數位在影像感測區211外圍外接墊215,各該矽穿孔213貫穿該背面212直至該外接墊215,以與該外接墊215電性連接。該膠框25係覆蓋該影像感測區211的外圍,並覆蓋該些外接墊215,該透光蓋板22則蓋合於該膠框25之一頂面,並與該影像感測晶片21的該影像感測區211保持一距離,該第二重佈線層23係形成在該影像感測晶片21的背面212,並與各該矽穿孔213電性連接,又該些金屬柱24係透過該第二重佈線層23與對應的該矽穿孔213電性連接,並向下凸出於該第二重佈線層23,並將一膠層26覆蓋於該些金屬柱24上,再令該些金屬柱24與位在該第一重佈線層10的該第一表面101上所對應的該第一接點12的金屬凸塊121電性連接,待該膠層26固化後,即可保護該些金屬柱24及第一接點12的金屬凸塊121,避免外部水氣侵蝕;較佳地,各該金屬柱24為銅柱,但不以此為限。The plurality of image sensors 20 are disposed on the first surface 101 of the first redistribution layer 10 and respectively associated with the first contacts 12 located on the first surface 101 of the first redistribution layer 10. The metal bumps 121 are electrically connected. In this embodiment, each of the image sensors 20 includes an image sensing chip 21, a transparent cover 22, a second redistribution layer 23, a plurality of metal posts 24, and a bezel 25; The image sensing wafer 21 includes an active surface 210, a back surface 212, and a plurality of turns 213. The active surface 210 includes an image sensing area 211 and a plurality of external pads 215 on the periphery of the image sensing area 211 . The through holes 213 extend through the back surface 212 to the external pad 215 to be electrically connected to the external pad 215 . The plastic frame 25 covers the periphery of the image sensing area 211 and covers the external pads 215. The transparent cover 22 covers the top surface of the plastic frame 25 and the image sensing wafer 21 The image sensing area 211 is maintained at a distance. The second redistribution layer 23 is formed on the back surface 212 of the image sensing wafer 21, and is electrically connected to each of the turns 213, and the metal posts 24 are transparent. The second redistribution layer 23 is electrically connected to the corresponding via hole 213, and protrudes downwardly from the second redistribution layer 23, and covers a metal layer 24 on the metal layer 24, and then The metal posts 24 are electrically connected to the metal bumps 121 of the first contacts 12 corresponding to the first surface 101 of the first redistribution layer 10, and are protected after the adhesive layer 26 is cured. The metal posts 24 and the metal bumps 121 of the first contacts 12 are protected from external moisture; preferably, the metal posts 24 are copper posts, but are not limited thereto.

上述至少一功能晶片30係設於該第一重佈線層10的第二表面102,並與該第一重佈線層10的該第二接點13的金屬凸塊131電性連接,以透過該第一重佈線層10之本體11內的金屬連接線14與對應的該些第一接點12及該些第三接點15電性連接。於本實施例中,由於該第一重佈線層10的複數第二接點13的密度高,故可進一步電性連接有多個功能晶片30,例如數位處理晶片、記憶體晶片、自動對焦驅動控制晶片等,以構成功能更強大、完整的影像感測模組。各該功能晶片30係於其底面形成有複數金屬柱31,以電性連接至對應的該些第二接點13的金屬凸塊131,並透過該些金屬連接線14與該些第一接點12及該些第三接點15電性連接;較佳地,各該金屬柱31為銅柱,但不以此為限。The at least one functional chip 30 is disposed on the second surface 102 of the first redistribution layer 10 and electrically connected to the metal bumps 131 of the second contact 13 of the first redistribution layer 10 to transmit the The metal connecting wires 14 in the body 11 of the first redistribution layer 10 are electrically connected to the corresponding first contacts 12 and the third contacts 15 . In this embodiment, since the density of the plurality of second contacts 13 of the first redistribution layer 10 is high, a plurality of functional wafers 30 can be further electrically connected, such as a digital processing chip, a memory chip, and an autofocus drive. Control wafers and the like to form a more powerful and complete image sensing module. Each of the functional chips 30 is formed with a plurality of metal pillars 31 on the bottom surface thereof to be electrically connected to the corresponding metal bumps 131 of the second contacts 13 and through the metal connecting wires 14 and the first interfaces. The point 12 and the third contacts 15 are electrically connected; preferably, each of the metal pillars 31 is a copper pillar, but is not limited thereto.

上述封膠體40將該至少一功能晶片30及該第一重佈線層10之第二表面102予以覆蓋,以保護該至少一功能晶片30的金屬柱31及其相電性連接的該第二接點13的金屬凸塊131不受外部水氣的侵蝕、損壞。The encapsulant 40 covers the at least one functional wafer 30 and the second surface 102 of the first redistribution layer 10 to protect the metal pillar 31 of the at least one functional wafer 30 and the second connection of the electrically connected portions thereof The metal bump 131 of the point 13 is not damaged or damaged by external moisture.

由於影像感測模組系統級封裝體1於製作完成後必須與其它電子元件電性連接使用,故如圖14所示,位在該第一重佈線層10的第一表面101上的該些第三接點15的金屬凸塊151可與如軟性電路板(FPC)50等元件電性連接,並可進一步將光學鏡片組件51對準該影像感測器20後,固定於第一重佈線層10的上表面101,構成完整的影像感測模組。Since the image sensing module system-level package 1 must be electrically connected to other electronic components after being fabricated, as shown in FIG. 14, the first surface 101 of the first redistribution layer 10 is The metal bumps 151 of the third contact 15 can be electrically connected to components such as a flexible circuit board (FPC) 50, and the optical lens assembly 51 can be further aligned with the image sensor 20 and fixed to the first redistribution. The upper surface 101 of the layer 10 constitutes a complete image sensing module.

以上為本發明本發明之影像感測模組系統級封裝體1的結構,以下進一步說明該影像感測模組系統級封裝體1的製造方法,即如圖2至圖16所示,並包含有以下步驟(a)至步驟(k):The above is the structure of the image sensing module system-level package 1 of the present invention. The method for manufacturing the image sensing module system-level package 1 is further described below, as shown in FIG. 2 to FIG. There are the following steps (a) to (k):

如圖2及圖3所示的步驟(a),係提供一載板60,該載板60上係塗佈形成有一脫離層(Release layer)61。As shown in FIG. 2 and FIG. 3, a carrier 60 is provided. The carrier 60 is coated with a release layer 61.

如圖4所示的步驟(b),於該載板60上形成一第一重佈線層10;即以一重佈線層(RDL)製程配合使用聚合物介電材料(Polymer dielectric material),並先形成有複數第一接點12及第三接點15後,再向上形成複數金屬接線14;其中該些第一接點12及第三接點15係與該些金屬接線14電性連接;之後,再將一絕緣層110覆蓋於該些金屬連接線14後,於該絕緣層110形成複數開口111,再請參閱圖5所示,於各該開口111內形成有金屬柱,以形成複數第二接點13;於本實施例中,再進一步於各該第二接點13形成凸出於該絕緣層110,並由銅、鎳、金三層構成的金屬凸塊131。As shown in step (b) of FIG. 4, a first redistribution layer 10 is formed on the carrier 60; that is, a polymer dielectric material is used in combination with a redistribution layer (RDL) process, and After the plurality of first contacts 12 and the third contacts 15 are formed, the plurality of metal wires 14 are formed upward; wherein the first contacts 12 and the third contacts 15 are electrically connected to the metal wires 14; After the insulating layer 110 is covered on the metal connecting lines 14, a plurality of openings 111 are formed in the insulating layer 110. Referring to FIG. 5, metal pillars are formed in each of the openings 111 to form a plurality of openings. In the present embodiment, further, the second bumps 13 are formed with metal bumps 131 protruding from the insulating layer 110 and composed of three layers of copper, nickel and gold.

如圖6所示的步驟(c),令複數功能晶片30底面的金屬柱31對準該些第二接點13的金屬凸塊131後相互連電性連接,即如圖7所示。Step (c) shown in FIG. 6 is such that the metal posts 31 on the bottom surface of the plurality of functional chips 30 are aligned with the metal bumps 131 of the second contacts 13 and electrically connected to each other, as shown in FIG.

如圖8所示的步驟(d),形成一封膠體40,以覆蓋該複數功能晶片30及該第一重佈線層10的第二表面102,如此該些功能晶片30底面的金屬柱31與其所電性連接的第二接點13的金屬凸塊131均被覆蓋於該封膠體40中;於本實施例中,步驟(d)係以灌模(Molding)及固化(Curing)製程形成該封膠體40。As shown in step (d) of FIG. 8, a colloid 40 is formed to cover the plurality of functional wafers 30 and the second surface 102 of the first redistribution layer 10, such that the metal pillars 31 on the bottom surface of the functional wafers 30 are The metal bumps 131 of the electrically connected second contacts 13 are all covered in the sealant 40; in the embodiment, the step (d) is formed by a molding process and a curing process. Sealant 40.

如圖9及圖10所示的步驟(e),於本實施例中,係將該載板60翻轉朝上,再以雷射光L照射該載板60,使其上的脫離層61裂解後與該第一重佈線層10的第一表面101脫離,而可移除該載板60,使該些第二接點12及第三接點15外露於該第一重佈線層10的第一表面101;再如圖11所示,各該第一接點12及各該第三接點15分別形成由銅、鎳、金三層構成的金屬凸塊121、151,但不以此金屬材質為限。此外,如圖10所示外露的第一及第三接點12、15係與第一表面101共平面,故亦可直接作為與元件電性連接的銲接接點用。As shown in FIG. 9 and FIG. 10 (e), in the present embodiment, the carrier 60 is turned upside up, and the carrier 60 is irradiated with the laser light L to cleave the release layer 61 thereon. Disengaging the first surface 101 of the first redistribution layer 10, the carrier 60 can be removed, and the second contacts 12 and the third contacts 15 are exposed to the first of the first redistribution layer 10. The surface 101; further, as shown in FIG. 11, each of the first contact 12 and each of the third contacts 15 respectively form metal bumps 121 and 151 composed of three layers of copper, nickel and gold, but not the metal material. Limited. In addition, as shown in FIG. 10, the exposed first and third contacts 12, 15 are coplanar with the first surface 101, so that they can be directly used as solder joints for electrical connection with the components.

如圖12所示的步驟(f),將複數影像感測器20的該些金屬柱24分別對準並電性連接至對應的金屬凸塊121,如圖13所示;於本實施例中,可先於各影像感測器20的該些金屬柱24塗覆有一軟性膠層26,再與對應的金屬凸塊121接合並電性連接,等待一段時間後,該軟性膠層26即固化。較佳地,該軟性膠層26係為一異向性導電膜(Non Conductive Film;NCF)。As shown in FIG. 12, the metal posts 24 of the plurality of image sensors 20 are respectively aligned and electrically connected to the corresponding metal bumps 121, as shown in FIG. 13; The metal pillars 24 of the image sensors 20 may be coated with a soft adhesive layer 26, and then joined and electrically connected to the corresponding metal bumps 121. After waiting for a period of time, the soft adhesive layer 26 is cured. . Preferably, the soft adhesive layer 26 is an anisotropic conductive film (NCF).

如圖13所示的步驟(g),將步驟(f)的結構暫時固定於一膠帶63上,以便於切割出複數影像感測模組系統級封裝體1;其中各該影像感測模組系統級封裝體1係包含多個影像感測器20及至少一功能晶片30;於本實施例,各該影像感測模組系統級封裝體1包含有多個功能晶片30,例如數位處理晶片、記憶體晶片、自動對焦驅動控制晶片等,但同樣不以此為限。As shown in step (g) of FIG. 13, the structure of the step (f) is temporarily fixed on a tape 63 to cut out the plurality of image sensing module system-level packages 1; wherein the image sensing modules are respectively The system-in-package 1 includes a plurality of image sensors 20 and at least one functional chip 30. In this embodiment, each of the image sensing module system-level packages 1 includes a plurality of functional wafers 30, such as digital processing chips. , memory chip, autofocus drive control chip, etc., but also not limited to this.

綜上所述,由於上述本發明的製造方式係於一道晶圓級封裝製程中完成,減少後續組裝製程中,異物沾黏在影像感測器上而減低良率;再者,可依據如陣列式相機模組需要的影像感測器數量,直接製作出符合要求的影像感測模組,又由於本案的技術不必使用預先成型的基板來完成影像感測器及其功能晶片的系統級封裝,其尺寸、厚度可更為減縮,而且本發明的該影像感測模組系統級封裝體可包含複數個影像感測器,並可進一步將多個影像處理晶片一併整合封裝於單顆封裝體中,以陣列式相機模組為例,即可大大提升對焦和連拍速度。In summary, since the manufacturing method of the present invention is completed in a wafer level packaging process, the foreign matter is adhered to the image sensor to reduce the yield in the subsequent assembly process; The number of image sensors required by the camera module directly produces the image sensing module that meets the requirements, and the technology of the present invention does not require the use of a pre-formed substrate to complete the system-level packaging of the image sensor and its functional chip. The image sensing module system-level package of the present invention can include a plurality of image sensors, and can further integrate a plurality of image processing chips into a single package. In the case of the array camera module, the focus and continuous shooting speed can be greatly improved.

以上所述僅是本發明的實施例而已,並非對本發明做任何形式上的限制,雖然本發明已以實施例揭露如上,然而並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明技術方案的範圍內,當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例,但凡是未脫離本發明技術方案的內容,依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾,均仍屬於本發明技術方案的範圍內。The above is only the embodiment of the present invention, and is not intended to limit the scope of the present invention. The present invention has been disclosed by the embodiments, but is not intended to limit the invention, and any one of ordinary skill in the art, In the scope of the technical solutions of the present invention, equivalent modifications may be made to the equivalents of the embodiments of the present invention without departing from the technical scope of the present invention. Any simple modifications, equivalent changes and modifications made to the above embodiments are still within the scope of the technical solutions of the present invention.

1‧‧‧影像感測模組系統級封裝體1‧‧‧Image Sensing Module System Level Package

10‧‧‧第一重佈線層10‧‧‧First redistribution layer

101‧‧‧第一表面101‧‧‧ first surface

102‧‧‧第二表面102‧‧‧ second surface

11‧‧‧本體11‧‧‧Ontology

12‧‧‧第一接點12‧‧‧ first joint

121‧‧‧金屬凸塊121‧‧‧Metal bumps

13‧‧‧第二接點13‧‧‧second junction

131‧‧‧金屬凸塊131‧‧‧Metal bumps

14‧‧‧金屬連接線14‧‧‧Metal cable

15‧‧‧第三接點15‧‧‧ third joint

151‧‧‧金屬凸塊151‧‧‧Metal bumps

20‧‧‧影像感測器20‧‧‧Image Sensor

21‧‧‧影像感測晶片21‧‧‧Image sensing wafer

210‧‧‧主動面210‧‧‧Active surface

211‧‧‧影像感測區211‧‧‧Image Sensing Area

212‧‧‧背面212‧‧‧Back

213‧‧‧矽穿孔213‧‧‧矽Perforated

215‧‧‧外接墊215‧‧‧External mat

22‧‧‧透光蓋板22‧‧‧Transparent cover

23‧‧‧第二重佈線層23‧‧‧Second redistribution layer

24‧‧‧金屬柱24‧‧‧ metal column

25‧‧‧膠框25‧‧‧ plastic frame

26‧‧‧膠層26‧‧‧ glue layer

30‧‧‧功能晶片30‧‧‧Functional Wafer

31‧‧‧金屬柱31‧‧‧Metal column

40‧‧‧封膠體40‧‧‧ Sealant

50‧‧‧軟性電路板50‧‧‧Soft circuit board

51‧‧‧光學鏡片組件51‧‧‧Optical lens assembly

60‧‧‧載板60‧‧‧ Carrier Board

61‧‧‧脫離層61‧‧‧Separation layer

63‧‧‧膠帶63‧‧‧ Tape

70‧‧‧影像感測模組系統級封裝體70‧‧‧Image Sensing Module System Level Package

71‧‧‧影像感測器71‧‧‧Image sensor

72‧‧‧基板72‧‧‧Substrate

73‧‧‧處理器晶片73‧‧‧Processing chip

80‧‧‧光學鏡片支架80‧‧‧Optical lens holder

81‧‧‧光學鏡片81‧‧‧Optical lenses

圖1:本發明一影像感測模組系統級封裝體之剖面圖。 圖2至圖13:本發明影像感測模組系統級封裝體於各製程步驟中的剖面圖。 圖14:本發明影像感測模組系統級封裝體加上光學鏡片組件的剖面圖。 圖15:一既有影像感測模組系統級封裝體之剖面圖。1 is a cross-sectional view of a system level package of an image sensing module of the present invention. 2 to FIG. 13 are cross-sectional views showing the system level package of the image sensing module of the present invention in each process step. Figure 14 is a cross-sectional view of the image sensing module system package of the present invention plus an optical lens assembly. Figure 15 is a cross-sectional view of a system-in-package of an existing image sensing module.

Claims (9)

一種影像感測模組系統級封裝體,包括:一第一重佈線層,係包含有一本體、複數第一接點、複數金屬連接線、複數第二接點及複數第三接點;其中,該些第一接點係外露於該本體之一第一表面,該些第二接點外露於該本體之一第二表面,該些第三接點係外露於該本體的第一表面,該些金屬連接線係形成於該本體內,以電性連接該些第一接點及該些第二接點,並電性連接該些第二接點及該些第三接點;複數影像感測器,係分別電性連接所對應的該第一接點;至少一功能晶片,係電性連接所對應的該複數第二接點;以及一封膠體,係覆蓋該至少一功能晶片及該第一重佈線層的第二表面。 An image sensing module system-level package includes: a first redistribution layer comprising a body, a plurality of first contacts, a plurality of metal connections, a plurality of second contacts, and a plurality of third contacts; wherein The first contacts are exposed on a first surface of the body, the second contacts are exposed on a second surface of the body, and the third contacts are exposed on the first surface of the body, The metal connection wires are formed in the body to electrically connect the first contacts and the second contacts, and electrically connect the second contacts and the third contacts; The detector is electrically connected to the first contact; the at least one functional chip is electrically connected to the plurality of second contacts; and a gel covering the at least one functional chip and the a second surface of the first redistribution layer. 如請求項1所述之影像感測模組系統級封裝體,其中:各該第一接點係進一步形成有一金屬凸塊,以凸出於該第一重佈線層第一表面;各該第二接點係進一步形成有一金屬凸塊,以凸出於該第一重佈線層第二表面;以及各該第三接點係進一步形成有一金屬凸塊,以凸出於該第一重佈線層第一表面。 The image sensing module system-level package of claim 1, wherein each of the first contacts further comprises a metal bump protruding from the first surface of the first redistribution layer; The second contact is further formed with a metal bump protruding from the second surface of the first redistribution layer; and each of the third contacts is further formed with a metal bump to protrude from the first redistribution layer The first surface. 如請求項2所述之影像感測模組系統級封裝體,各該金屬凸塊為銅、鎳、金三層凸塊。 The image sensing module system-level package according to claim 2, wherein each of the metal bumps is a copper, nickel, and gold three-layer bump. 如請求項1所述之影像感測模組系統級封裝體,各該影像感測器係包含有:一影像感測晶片,係包含有一主動面、一背面及複數矽穿孔;其中該主動面包含有一影像感測區及複數位在影像感測區外圍的外接墊,各該矽穿孔貫穿該背面直至該外接墊,以與該外接墊電性連接; 一膠框,係覆蓋該影像感測區外圍的該些外接墊;一透光蓋板,係蓋合於該膠框之一頂面,並與該影像感測晶片的該影像感測區保持一距離;一第二重佈線層,係分別形成在對應之該影像感測晶片的背面,並與各該矽穿孔電性連接;以及多個金屬柱,係透過該第二重佈線層與對應的該矽穿孔電性連接,並向下凸出於該第二重佈線層,以與所對應的該第一接點電性連接。 The image sensing module system-level package of claim 1, wherein each of the image sensors comprises: an image sensing chip, comprising an active surface, a back surface, and a plurality of perforations; wherein the active bread An external pad having an image sensing area and a plurality of bits on the periphery of the image sensing area, each of the through holes extending through the back surface to the external pad to be electrically connected to the external pad; a plastic frame covering the outer pads of the periphery of the image sensing area; a transparent cover covering the top surface of the frame and maintaining the image sensing area of the image sensing chip a second redistribution layer is formed on the back surface of the corresponding image sensing wafer and electrically connected to each of the turns; and a plurality of metal pillars are transmitted through the second redistribution layer The cymbal is electrically connected to the through hole and protrudes downward from the second redistribution layer to be electrically connected to the corresponding first contact. 如請求項4所述之影像感測模組系統級封裝體,係進一步包含有複數膠層,各該膠層係覆蓋於對應之該影像感應器之複數金屬柱與其所電性連接的該第一接點。 The image sensing module system-level package according to claim 4, further comprising a plurality of adhesive layers, each of the adhesive layers covering the plurality of metal posts corresponding to the image sensor and the electrically connected A contact. 如請求項5所述之影像感測模組系統級封裝體,各該膠層為異方性導電膠。 The image sensing module system-level package according to claim 5, wherein each of the adhesive layers is an anisotropic conductive adhesive. 一種影像感測模組系統級封裝體的製造方法,包括以下步驟:(a)提供一載板;(b)於該載板上形成一重佈線層;其中該重佈線層由下至上依序形成複數第一接點、複數金屬連接線及複數第二接點,該些第一接點及第二接點係與該些金屬連接線電性連接;其中該些第二接點係外露於該重佈線層之第二表面;(c)令複數功能晶片與該些第二接點電性連接;(d)形成一封膠體,以覆蓋該至少一功能晶片及該重佈線層的第二表面;(e)移除該載板,使該些第一接點外露於該重佈線層的第一表面;(f)將複數影像感測器分別電性連接至對應的該些第一接點;以及(g)切割出複數影像感測模組系統級封裝體;其中各該影像感測模組系統級封裝體係包含多個影像感測晶片及至少一功能晶片。 A method for manufacturing an image sensing module system-level package comprises the steps of: (a) providing a carrier; (b) forming a redistribution layer on the carrier; wherein the redistribution layer is formed sequentially from bottom to top a plurality of first contacts, a plurality of metal wires, and a plurality of second contacts, wherein the first contacts and the second contacts are electrically connected to the metal wires; wherein the second contacts are exposed a second surface of the redistribution layer; (c) electrically connecting the plurality of functional wafers to the second contacts; (d) forming a gel to cover the at least one functional wafer and the second surface of the redistribution layer (e) removing the carrier to expose the first contacts to the first surface of the redistribution layer; (f) electrically connecting the plurality of image sensors to the corresponding first contacts And (g) cutting out the plurality of image sensing module system-level packages; wherein each of the image sensing module system-level packaging systems comprises a plurality of image sensing chips and at least one functional wafer. 如請求項7所述之影像感測模組系統級封裝體的製造方法,於上述步驟(f)中,將一異方性導電膠覆蓋各該影像感測器底面的複數金屬柱後,再令金屬柱對準其所對應的第一接點後電性連接。 The method for manufacturing an image sensing module system-level package according to claim 7, wherein in the step (f), an anisotropic conductive paste covers a plurality of metal pillars on the bottom surface of each image sensor, and then The metal post is electrically connected to the corresponding first contact. 如請求項7或8所述之影像感測模組系統級封裝體的製造方法,其中:於步驟(b)中,進一步以凸塊製程步驟於各該第二接點上形成有一金屬凸塊;以及於步驟(e)中,進一步以凸塊製程步驟於各該第一接點上形成有一金屬凸塊。 The method for manufacturing an image sensing module system-level package according to claim 7 or 8, wherein in step (b), a metal bump is further formed on each of the second contacts by a bump process step. And in step (e), a metal bump is further formed on each of the first contacts by a bump process step.
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TWI705547B (en) * 2019-03-12 2020-09-21 力成科技股份有限公司 Chip package structure and manufacturing method thereof
CN112435996A (en) * 2020-10-09 2021-03-02 日月光半导体制造股份有限公司 Semiconductor package device and method of manufacturing the same

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TW201543641A (en) * 2014-05-12 2015-11-16 Xintex Inc Chip package and method for forming the same

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TW201543641A (en) * 2014-05-12 2015-11-16 Xintex Inc Chip package and method for forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI705547B (en) * 2019-03-12 2020-09-21 力成科技股份有限公司 Chip package structure and manufacturing method thereof
CN112435996A (en) * 2020-10-09 2021-03-02 日月光半导体制造股份有限公司 Semiconductor package device and method of manufacturing the same

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