TWI650965B - Channel estimating apparatus and channel estimating method - Google Patents

Abstract

In the channel estimating apparatus provided by the present invention, a candidate delay amount generating circuit finds a plurality of candidate delay amounts based on the channel impulse response of the received signal, and selects a selected candidate delay amount each time. An infinite impulse response filter provides M kinds of delay amounts adjacent to the selected candidate delay amount, and applies a filtering procedure to the received signals according to the M kinds of delay amounts and M weights to generate a filtered signal and a corresponding M Delayed signal. For each candidate delay amount, a weight generating circuit iteratively generates new M weights according to the filtered signal and the M delayed signals. An evaluation generating circuit calculates an evaluation for the selected candidate delay amount based on the latest M weights when an iteration termination condition is established. An echo signal information is generated based on the evaluations.

Description

Channel estimation device and channel estimation method

The invention relates to communication systems and, in particular, to channel estimation techniques at the receiving end of a communication system.

Wireless signals are inevitably affected and interfered with by the transmission environment during transmission. The receiving end must evaluate the channel effect. For example, due to the arrival time of the echo signal generated by the multipath relative to the main signal, the echo signal can be eliminated through the equalization procedure, and the received signal can be correctly interpreted. data.

Orthogonal frequency-division multiplexing (OFDM) technology has been widely used in wireless communication systems in recent years due to its high spectrum utilization and simple hardware architecture. Figure 1 shows a partial circuit of an OFDM receiving end. The analog-to-digital converter 110 is responsible for converting the analog signal received by the front end circuit into a digital signal. The downsampling circuit 120 then downsamples the digital signal to match the symbol rate employed by the transmitting end. Hereinafter, the output signal of the downsampling circuit 120 is a received signal. The fast Fourier transform circuit 130 is responsible for generating the frequency spectrum of the received signal. As is known to those of ordinary skill in the art, the pilot symbols in the OFDM signal are placed on a portion of the subcarriers at specific frequency intervals, and the receiving end must have these leading symbols with known data. Take it out as a basis for evaluating the channel effect. To this end, the spectrum acquisition circuit 140 extracts the energy of the subcarrier carrying the preamble symbol from the spectrum of the received signal and sets the energy of the other frequencies to zero. Subsequently, the fast Fourier inverse conversion circuit 150 is responsible for applying a fast Fourier inverse transform to the spectrum that retains only part of the energy information to produce a channel impulse response. Channel estimation circuit 160 is responsible for The channel impulse response produces echo signal information that is provided to the equalizer 170 for reference. Then, the equalized signal that cancels the channel effect by the equalizer 170 is sent to the demapping circuit 180 and the decoding circuit 190.

Since the spectrum acquisition circuit 140 sets the energy of the subcarrier not carrying the preamble symbol to zero, the image signal appears in the channel impulse response generated by the fast Fourier inverse conversion circuit 150, and the number of the image signal and the frequency interval at which the preamble symbol appears Related. If one of the three subcarriers carries a preamble, in addition to a set of real signals, two sets of image signals will appear in the channel impulse response. Assuming that the actual channel impulse response is as shown in Figure 2(A), including three real signals arriving at the receiving end at different times, the channel impulse response output by the fast Fourier transform circuit 150 will be as shown in Figure 2(B). Nine signals appear. The symbol N in the figure represents the length of time of the signal employed by the fast Fourier inverse conversion circuit 150. An image signal (S1', S1") appears respectively at a distance of N/3 from the real signal S1. Similarly, the front and rear sides of the real signals S2 and S3 also have an image signal (S2', S2", S3', S3"). That is to say, there are three real signals and six image signals in Figure 2(B). On the other hand, one of the three real signals is transmitted through the main path. The main signal, two are the echo signals transmitted through the secondary path. The main signal and the echo signal are usually distinguished by the energy level. In the spectrum presented in Figure 2(B), the signal S1 can be defined as the main signal. Signal, and signals S2, S3 are echo signals.

In fact, when receiving the channel impulse response as shown in FIG. 2(B), the channel estimation circuit 160 cannot directly determine which of them are real signals and which are image signals. Therefore, for convenience of explanation, Figure 2 (B) is redrawn as Figure 3 (A) and the signal name is re-marked. Since the frequency interval at which the preamble symbol appears is a known number, the distance between the real signal and its image signal is known in advance. Assuming that the spacing is known to be N/3, the channel estimation circuit 160 can initially determine that one of the signals S1a, S1b, S1c having similar energy levels and spacing N/3 is a real signal and the other two are image signals. Similarly, there is a real signal in signals S2a, S2b, S2c, and there is a real signal in signals S3a, S3b, S3c.

The information required by the equalizer 170 is mainly the relative time difference between the signal passing through the primary path and the secondary path to the receiving end, rather than the absolute time. Therefore, the channel estimation circuit 160 can select one of the three most powerful signals S1a, S1b, and S1c as the real main signal transmitted through the main path, and find out from the signals S2a, S2b, and S2c. A real echo signal transmitted through the secondary path, from the signals S3a, S3b, and S3c, find another true echo signal transmitted through the secondary path. Taking the channel estimation circuit 160 as the real main signal as an example, FIG. 3(B) to FIG. 3(J) present nine possible combinations of echo signals; the channel estimation circuit 160 must determine which echo signal The combination is correct.

One current technical solution is to have the channel estimation circuit 160 provide nine possible echo signal combinations one by one to subsequent circuits, and the equalizer 170, the demapping circuit 180, and the decoding circuit 190 are combined for each echo signal. A set of decoding results, and finally based on the bit error rate (BER) of these decoding results to determine which echo signal combination is the most correct. The disadvantage of this approach is that each echo signal combination must be tested one by one, and the correctness of the echo signal combination must be determined after the decoding is completed. In addition to being time consuming, a large amount of computing resources are also required.

In order to solve the above problems, the present invention proposes a new channel estimation apparatus and channel estimation method.

According to an embodiment of the present invention, a channel estimating apparatus includes a candidate delay amount generating circuit, an infinite impulse response filter, a weight generating circuit, an evaluation generating circuit, and a selecting circuit. The candidate delay amount generating circuit is configured to find a plurality of candidate delay amounts corresponding to the plurality of candidate echo signals according to one channel impulse response of a received signal, and select a selected candidate from the plurality of candidate delay amounts each time The amount of delay. The infinite impulse response filter is configured to provide M kinds of delay amounts adjacent to the selected candidate delay amount, and apply an infinite impulse response filtering procedure to the received signals according to the M kinds of delay amounts and M weights to generate A filtered signal and the filtered signal correspond to the M delayed signals of the M kinds of delay amounts, wherein M is a positive integer greater than one. The weight generating circuit is configured to iteratively generate a new M weights according to the filtered signal and the M delayed signals for each candidate delay amount, and request the infinite impulse response filter according to the new M weights The infinite impulse response filtering process is performed again. The evaluation generating circuit is configured to calculate an evaluation based on the latest M weights when an iteration termination condition is established for each selected candidate delay amount. The selection circuit is configured to select one or more real echo signals from the plurality of candidate echo signals according to the evaluation, and generate an echo signal information accordingly.

Another embodiment of the present invention is a channel estimating apparatus including a candidate delay amount generating circuit, a delay circuit, a weight generating circuit, an evaluation generating circuit, and a selecting circuit. The candidate delay amount generating circuit is configured to find a plurality of candidate delay amounts corresponding to the plurality of candidate echo signals according to one channel impulse response of a received signal, and select a selected candidate from the plurality of candidate delay amounts each time The amount of delay. The delay circuit is configured to provide M delay amounts adjacent to the selected candidate delay amount, and generate corresponding M delayed signals for the received signal, where M is a positive integer greater than one. The weight generating circuit is configured to iteratively generate a new M weights according to the received signal and the M delayed signals for each selected candidate delay amount. The evaluation generating circuit is configured to calculate an evaluation based on the latest M weights generated by the weight generating circuit when an iterative termination condition is established for each selected candidate delay amount. The selection circuit is configured to select one or more real echo signals from the plurality of candidate echo signals according to the evaluation, and generate an echo signal information accordingly.

Another embodiment of the present invention is a channel estimation method. First, a plurality of candidate delay amounts corresponding to a plurality of candidate echo signals are found based on a channel impulse response of a received signal. One candidate delay amount of each of the plurality of candidate delay amounts is selected as a selected candidate delay amount, and the following steps are performed: (1) providing M kinds of delay amounts adjacent to the selected candidate delay amount (M is greater than a positive integer); (2) applying an infinite impulse response filtering process to the received signal according to the M kinds of delay amounts and M weights to generate a filtered signal and the The filtered signal corresponds to the M delayed signals of the M kinds of delay amounts; (3) iteratively generates new M weights according to the filtered signals and the M delayed signals, and causes steps (2) and steps ( 3) being re-executed according to the new M weights; and (4) calculating an evaluation based on the latest M weights when an iteration termination condition is established. Then, based on the evaluations, one or more true echo signals are selected from the plurality of candidate echo signals, and an echo signal information is generated accordingly.

Another embodiment of the present invention is a channel estimation method. First, a plurality of candidate delay amounts corresponding to a plurality of candidate echo signals are found based on a channel impulse response of a received signal. One of the plurality of candidate delay amounts is selected each time as a selected candidate delay amount, and the following steps are performed: (1) providing M kinds of delay amounts adjacent to the selected candidate delay amount, and Receiving a signal to generate corresponding M delayed signals (M is a positive integer greater than one); (2) iterating to generate new M weights according to the received signal and the M delayed signals; and (3) When the iterative termination condition is established, an evaluation is calculated for the selected candidate delay amount based on the latest M weights. Then, based on the evaluations, one or more true echo signals are selected from the plurality of candidate echo signals, and an echo signal information is generated accordingly.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

110‧‧‧ Analog-Digital Converter

120‧‧‧ down sampling circuit

130‧‧‧fast Fourier transform circuit

140‧‧‧ spectrum acquisition circuit

150‧‧‧fast Fourier transform conversion circuit

160‧‧‧channel estimation circuit

170‧‧‧ Equalizer

180‧‧ § demapping circuit

190‧‧‧Decoding circuit

S1, S2, S3‧‧‧ true signal

S1', S2', S3', S1", S2", S3" ‧ ‧ Mirror signal

S1a, S1b, S1c, S2a, S2b, S2c, S3a, S3b, S3c‧‧‧ signals

400‧‧‧Infinite impulse response filter

410‧‧‧Addition circuit

420‧‧‧Delay circuit

430‧‧‧weighting circuit

440‧‧‧Additional generation circuit

L ₁ , L ₂ , ..., L _M ‧‧‧ delay elements

500‧‧‧channel estimation device

510‧‧‧Candidate delay generation circuit

520‧‧‧weight generating circuit

530‧‧‧Evaluation generating circuit

540‧‧‧Selection circuit

521‧‧‧Relevance calculation circuit

522‧‧‧Multiplication circuit

523‧‧‧Addition circuit

531‧‧‧Counting circuit

532‧‧‧ square sum calculation circuit

524‧‧‧First operational circuit

525‧‧‧second arithmetic circuit

526‧‧‧ Transposed circuit

527‧‧‧ vector multiplication circuit

528‧‧‧Multiplication circuit

529‧‧‧Addition circuit

550‧‧‧Switching circuit

1000‧‧‧channel estimation device

1010‧‧‧Candidate delay generation circuit

1020‧‧‧weight generating circuit

1030‧‧‧Evaluation generating circuit

1040‧‧‧Selection circuit

S1101~S1111‧‧‧ Process steps

S1201~S1210‧‧‧ Process steps

Figure 1 shows a partial circuit of an orthogonal frequency division multiplexing receiver.

Figure 2 (A) presents an example of a channel impulse response that only shows the real signal; Figure 2 (B) presents an example of a channel impulse response that includes the real signal and the image signal.

Figure 3 (A) is a schematic diagram of one channel impulse response; Figure 3 (B) ~ Figure 3 (J) presents a variety of signal combinations corresponding to the same channel impulse response.

Figure 4 presents an infinite impulse response filter that can be applied in an embodiment in accordance with the invention. Functional block diagram of the device.

Figure 5 is a functional block diagram of a channel estimation apparatus in accordance with an embodiment of the present invention.

Figure 6 is an illustration of a weight generating circuit in accordance with an embodiment of the present invention.

Figure 7 is an illustration of an evaluation generation circuit in accordance with an embodiment of the present invention.

Figure 8 is an illustration of a weight generating circuit in accordance with another embodiment of the present invention.

Figure 9 is a schematic diagram of a channel estimation apparatus according to the present invention further including a switching circuit.

Figure 10 is a functional block diagram of a channel estimation apparatus in accordance with another embodiment of the present invention.

11 is a flow chart of a channel estimation method in accordance with an embodiment of the present invention.

Figure 12 is a flow chart of a channel estimation method in accordance with another embodiment of the present invention.

It should be noted that the drawings of the present invention include functional block diagrams that present a plurality of functional modules associated with each other. These figures are not detailed circuit diagrams, and the connecting lines therein are only used to represent the signal flow. Multiple interactions between functional components and/or procedures do not have to be achieved through direct electrical connections. In addition, the functions of the individual components are not necessarily allotted in the manner illustrated in the drawings, and the decentralized blocks are not necessarily implemented in the form of decentralized electronic components.

According to an embodiment of the invention, a channel estimation apparatus including an infinite impulse response (IIR) filter is used, and the authenticity of the echo signal is determined according to a weight coefficient used by the infinite impulse response filter. . The following describes how the infinite impulse response filter in this embodiment operates.

Please refer to Figure 4. The infinite impulse response filter 400 includes an adder circuit 410, a delay circuit 420, a weighting circuit 430, and a summing circuit 440. The symbol k represents a sampling index, and the input signal and the output signal of the infinite impulse response filter 400 are the received signal y [ k ] and the filtered signal z [ k ] generated by the adding circuit 410, respectively.

The delay circuit 420 includes M delay elements L ₁ , L ₂ , ..., L _M (M is an integer greater than one). The schematic delay amount D of the delay circuit 420 receives the delay element _{L 1, L 2, ...,} L M in the delay amount of each of the output terminals provided respectively _{(D + d 1), (} D + d 2), ... ( D + d _M ), where the symbols d ₁ , d ₂ , ... d _M represent different values of M close to or equal to zero. Therefore, the delay elements L ₁ , L ₂ , . . . , L _M generate M delayed signals that are similar in delay but different from each other for the filtered signal z [ k ]: z [ k -( D + d ₁ )], z [ k -( D + d ₂ )], ..., z [ k -( D + d _M )]. For convenience of explanation, FIG. 4 and subsequent embodiments mainly take the case where M is equal to eight, and assume that the values d ₁ , d ₂ , . . . , d ₈ are consecutive eight integers from small to large: -3, -2, ..., 4. The delayed signals are collectively represented as z [ k -( D + m )], where the symbol m represents one of the values d ₁ , d ₂ , ..., d _M , which in this example is a range An integer indicator between -3 and 4. It will be understood by those of ordinary skill in the art that the scope of the invention is not limited thereto.

The weighting circuit 430 applies a weight w _m to the delayed signal z [ k -( D + m )] and produces a total of eight weighted signals. The weighted signals are then supplied to the summing circuit 440 for summing and then passed to the summing circuit 410 as one of its input signals. The summing circuit 410 subtracts the summed result from the received signal y [ k ] to produce a filtered signal z [ k ]. In summary, the relationship between the received signal y [ k ] and the filtered signal z [ k ] can be summarized as:

As can be seen from Equation 1, the infinite impulse response filter 400 functions to filter out the sum of the eight weighted signals from the received signal y [ k ]. Furthermore, by selecting an appropriate rough delay amount D and weight w _m , it is possible to control which signal is to be filtered out. Since the delay amounts provided by the delay elements L ₁ -L ₈ are both close to or equal to the approximate delay amount D , the addition of the eight weighted signals can be considered as interpolation to produce a substantially relative to the filtered signal z [ k ] The signal of the delay amount D to be filtered out.

The following describes how the infinite impulse response filter 400 is applied in the channel estimation apparatus of the present invention.

Figure 5 is a functional block diagram of a channel estimation apparatus in accordance with an embodiment of the present invention. The channel estimation device 500 is configured to generate echo signal information based on a received signal and its channel impulse response for use by a frequency domain equalizer or a time domain equalizer. In practice, the channel estimation device 500 can cooperate with various systems that need to detect the authenticity of the echo signal, such as, but not limited to, an OFDM receiver that generates an image signal by zero-padding the spectrum of the received signal. As shown in FIG. 5, in addition to the infinite impulse response filter 400, the channel estimation apparatus 500 further includes a candidate delay amount generation circuit 510, a weight generation circuit 520, an evaluation generation circuit 530, and a selection circuit 540.

First, the candidate delay amount generation circuit 510 finds a plurality of channel echo responses corresponding to the received signal y [ k ] (for example, generated by the fast Fourier inverse conversion circuit 150 in FIG. 1 ) corresponding to the plurality of candidate echo signals. The amount of candidate delay. Taking the channel impulse response shown in FIG. 3(A) as an example, the candidate delay amount generation circuit 510 can select the signal S1b as the main signal and select the signals S2a, S2b, S2c, S3a, S3b, and S3c as candidate echo signals. . The distance between the six candidate echo signals on the time axis and the signal S1b (ie, the relative time difference from the main signal S1b to the receiving end) is six candidate delay amounts D _2a , D _2b , D _2c , D _3a , D _3b , D _3c . The candidate delay amount generation circuit 510 converts the six candidate delay amounts into units of the sampling index k , each time providing a candidate delay amount to the infinite impulse response filter 400 as its approximate delay amount D.

Figure 5, an infinite impulse response filter 400 used in the right weight w _m is a weight provided by the weight generating circuit 520. For each candidate delay amount, the evaluation generating circuit 530 generates an evaluation E based on the weight w _m supplied from the weight generating circuit 520 to the infinite impulse response filter 400. More specifically, in the case where the infinite impulse response filter 400 adopts the candidate delay amount D _2a as its approximate delay amount D , the weight generation circuit 520 iteratively generates a set of corresponding weights w _m , and the evaluation generating circuit 530 An evaluation E _{2a is} generated based on the set of weights w _m . And so on, the candidate delay amounts D _2a , D _2b , D _2c , D _3a , D _3b , D _3c will each have an evaluation E _2a , E _2b , E _2c , E _3a , E _3b , E _3c (hereinafter referred to as Evaluation E). Subsequently, the selection circuit 540 determines which of the six candidate echo signals are true signals and which four are image signals based on the evaluations E _2a , E _2b , E _2c , E _3a , E _3b , E _3c , Describe the detailed operation of each circuit.

The weight generation circuit 520 operating according to the least mean square (LMS) algorithm may pre-set a target and adjust the weight w _m multiple times through an iterative process to achieve the target. For example, to distinguish which candidate echo signal is a true echo signal, in one embodiment, the weight generation circuit 520 sets the target of the iterative adjustment weight w _m to "minimize the filtered signal z [ k ] The energy" (details are detailed later), and a cost function is defined accordingly as follows: The symbol n represents an iteration number indicator, and the symbol w _n,m represents the weight w _m corresponding to the nth iteration. In the case of the symbol m representing an integer index ranging between -3 and 4, the weight generation circuit 520 performs eight sets of iterative processes, yielding eight weights.

According to the concept of the least mean square algorithm, each weight w _{n,m is used} as the partial derivative versus cost function By applying a partial differential, an arithmetic expression (formula 4) can be derived, which is used to iteratively generate a cost function. Minimized weight w _n,m :

The symbol μ represents a tunable parameter in the least mean square algorithm that can be selected by the circuit designer based on experience.

6 is a functional block diagram of a weight generation circuit 520 implemented in accordance with Equation 4, including a correlation calculation circuit 521, a multiplication circuit 522, an addition circuit 523, and a register (not shown). In the nth iteration operation, the correlation calculation circuit 521 is responsible for respectively calculating the correlation between the filtered signal z [ k ] and each delayed signal z [ k -( D + m )] to generate eight correlation calculation results. r _{n, -3} , r _{n, -2} , ..., r _n,4 . The multiplication circuit 541 is responsible for multiplying the correlation calculation result r _n,m by the parameter 2 μ. Next, the addition circuit 542 is responsible for adding the respective multiplication results to the corresponding previous weights w _n,m (stored in the scratchpad) to generate new weights w _{n + 1 , m} . The new weights w _{n + 1, m} can also be stored in the above registers as the previous weights used in the next iteration.

In practice, the weight generation circuit 520 will iteratively continuously adjust the weights w _u,m , _and the initial values of the weights w _n,m (n=0) are not limited to a specific value. Furthermore, a new weight w _{n + 1, m} can be supplied to the infinite impulse response filter 400 in FIG. 5, again applying a filtering procedure to the same received signal y [ k ] to generate a new filtered signal z [ k ] As the basis for the weight generation circuit 520 to calculate the new weight w _{n + 2 , m} next time.

FIG. 7 presents an example of an internal functional block diagram of the evaluation generation circuit 530 including a counting circuit 531 and a square sum calculation circuit 532. The counting circuit 531 is responsible for calculating the number of iterations that the weight generating circuit 520 has performed, and requests the square sum calculating circuit 532 to calculate the latest eight weights when an iterative termination condition (for example, the iteration number index n reaches a predetermined value N) is established ( The sum of squares of w _{N, -3} , w _{N, -2} , ..., w _{N, 4} ) is taken as the evaluation E of the current candidate delay amount.

As described earlier, the weight generation circuit 520 determines an expression for iteratively generating the weights w _n,m with the goal of "minimizing the energy of the filtered signal z [ k ]". If the approximate delay amount D currently employed by the infinite impulse response filter 400 corresponds to a true echo signal, in theory, the weight generation circuit 520 can find an appropriate eight weights w _n,m after a period of iterative operation _. The infinite impulse response filter 400 filters the real echo signal from the received signal y [ k ]. In contrast, if the approximate delay amount D currently employed by the infinite impulse response filter 400 corresponds to a mirror echo signal, since the time point indicated by the candidate delay amount D does not actually exist in the real signal, the weight generation circuit 520 is iterated. The weight w _n,m found by the operation does not achieve the effect of filtering out the echo signal from the received signal y [ k ].

Compared to the image signal by using the amount of candidate delay contribution as the delay amount D is calculated schematic weights w _{n, m,} by using the delay amount candidate of the real echo signal contribution is calculated as the amount of delay D schematic weights w _{n, m} may have Large absolute value. Therefore, the higher the candidate echo signal of E is, the more likely it is to be a true echo signal, and the lower the candidate echo signal of E is, the more likely it is to be an image signal.

In another embodiment, the sum of squares calculation circuit 532 in FIG. 7 can be replaced with an absolute value sum calculation circuit that calculates the sum of the absolute values of the eight weights as the evaluation E.

A memory (not shown) may be disposed in the selection circuit 540 to temporarily store the evaluation E of each candidate delay amount. The selection circuit 540 selects one or more real echo signals from the plurality of candidate echo signals according to the evaluation E, and generates an echo signal information accordingly. Taking the channel impulse response shown in FIG. 3(A) as an example, assuming that the selected signal S1b is used as the main signal, the selection circuit 540 can select the candidate echo corresponding to the highest evaluation of E _2a , E _2b , and E _2c . The signal is treated as a true echo signal and the other two signals are considered as image signals. Similarly, the selection circuit 540 may select the candidate echo signals corresponding to the highest one of the evaluations E _2a , E _2b , and E _2c to be regarded as true echo signals, and treat the other two signals as image signals.

In practice, the weight generation circuit 520, the evaluation generation circuit 530, and the selection circuit 540 can be implemented as fixed and/or programmable digital logic circuits, including a programmable logic gate array, a specific application integrated circuit, and a microcontroller. , microprocessor, digital signal processor. Moreover, the echo signal information generated by the selection circuit 540 can include, but is not limited to, the channel length, and the difference in arrival time of each of the real echo signals and the primary signal.

As can be seen from the above description, unlike the prior art, the channel estimation apparatus 500 does not need to use the subsequent circuits such as the equalizer, the demapping circuit, and the decoding circuit to determine the authenticity of the echo signal. In addition, the number of tests to be performed by the channel estimation device 500 is the number of possible echo signals. Less than the number of tests that must be performed by the prior art (the number of possible signal combinations). Taking the channel impulse response shown in FIG. 3(A) as an example, the number of tests to be performed in the prior art is nine, and the number of tests to be performed by the channel estimating device 500 is six. Obviously, the channel estimation apparatus 500 can effectively achieve the effect of saving computation time and computing resources.

It should be noted that the weight generating circuit 520 has an alternative possibility to iteratively generate the weight w _n,m , and is not limited to the fourth formula. In another embodiment, the weight generation circuit 520 sets the target of the iterative generating weights w _n,m to "minimize the sum of the energy of the correlation between the echo signals", and defines a cost function as follows: The symbol j represents an integer indicator ranging from -3 to 4, and the symbol e _n,j is defined as: The symbol x [ k ] represents the kth sample of the original signal x sent by the transmitting end, and the symbols a , θ _k and Δ respectively represent the amplitude magnification, phase offset and arrival of an echo signal with respect to the original signal x . Time offset.

Similarly, according to the concept of the least mean square algorithm, each weight w _{n,m is used} as the partial derivative versus cost function. By applying partial differentiation, you can get:

Equation 7 can be simplified as: The vector (The detailed definition of the symbol e _n,j can refer to Equation 6), and the vector Is [Σ _k ( z [ k -( D + m )]* z ^* [ k -( D - 3 )])...Σ _k ( z [ k -( D + m )]* z ^* [ k -( D + 4 )])].

According to the above derivation results, using the following expressions to iteratively update the weights w _n,m , the cost functions defined by Equations 5 and 6 can be gradually implemented. Being minimized:

It is assumed that the front and back signals in the original signal x are not correlated in time and the average value is zero. In addition, it is also assumed that the average value of the noise signal is also zero. After a period of accumulation, the vector The accumulated value of some items in the process will approach zero, the vector It can be further simplified as: [Σ _k z [ k ]* z ^* [ k -( D - 3 )]...Σ _k z [ k ]* z ^* [ k -( D + 4 )]]. (Formula 10)

FIG. 8 is a functional block diagram of a weight generation circuit 520 implemented according to Equations 9 and 10, including a first operation circuit 524, eight second operation circuits 525, a transposition circuit 526, and a vector multiplication circuit 527. A multiplying circuit 528, an adding circuit 529, and a register (not shown). In the nth iterative operation, the first operation circuit 524 is configured to implement a calculation program corresponding to Equation 10, that is, generate a vector. Provided to the vector multiplication circuit 527. Eight second arithmetic circuits 525 are responsible for generating vectors, respectively , ,..., . In order to avoid the picture being too complicated, Figure 8 is only responsible for generating The detailed structure of the second arithmetic circuit 525. Transpose circuit 526 is responsible for the vector , ,..., Transpose separately to produce eight transpose vectors , ,..., . Vector multiplication circuit 527 is used to vector Transpose vector , ,..., Multiply. The multiplication circuit 528 is responsible for multiplying the output signals of the vector multiplication circuit 527 by a particular parameter of 2 μ (the symbol μ represents one of the tunable parameters in the least mean square algorithm, which can be selected empirically by the circuit designer). The summing circuit 529 is responsible for adding the respective multiplication results to the corresponding previous weights w _n,m (stored in the register) to generate new weights w _{n + 1 , m} . As shown in FIG. 5, the filtered signal z [ k ] and the delayed signal z [ k- ( D + m )] required for the operation of the weight generating circuit 520 are provided by the infinite impulse response filter 400.

Compared to the weight generation circuit 520 presented in FIG. 6, the weight generation circuit 520 presented in FIG. 8 employs a more complicated calculation program. Similarly, the weights generated by the two weight generating circuits 520 can be used as the basis for the evaluation generating circuit 530 to generate an evaluation E for each candidate delay amount.

In one embodiment, the channel estimation device 500 further includes a switching circuit 550 for switching the function of the infinite impulse response filter 400 between different modes, as shown in FIG. When channel estimation is required, the switching circuit 550 provides the candidate delay amount generating circuit 510 to the infinite impulse response filter 400 as its approximate delay amount D. As previously introduced, the infinite impulse response filter 400 can be used to assist in generating echo signal information. After the channel estimation apparatus 500 has completed the channel estimation, if it is necessary to apply the time domain equalization procedure to the received signal, the switching circuit 550 can provide the echo signal delay that the selection circuit 540 has confirmed to be correct to the infinite impulse response filtering. The device 400 is used as its rough delay amount D. In this case, the infinite impulse response filter can be used as a time domain equalizer, and the time domain equalization procedure is applied to the received signal y [ k ], and the filtered signal z [ k ] is used for subsequent circuits. After the signal. In other words, the infinite impulse response filter 400 can share the circuit with the time domain equalizer, thereby reducing hardware costs.

It should be noted that the technical details of the time domain equalization procedure using the infinite impulse response filter are known to those of ordinary skill in the art to which the present invention pertains, and will not be described herein. Moreover, in addition to the infinite impulse response filter 400, the time domain equalizer can be designed to further include other circuits such as, but not limited to, a finite impulse response (FIR) filter.

Another embodiment of the present invention is a channel estimation apparatus, and its functional block diagram is shown in FIG. 10, which includes a candidate delay amount generation circuit 1010, a weight generation circuit 1020, an evaluation generation circuit 1030, and a selection circuit. 1040, and a delay circuit 1050. The function of the candidate delay amount generating circuit 1010 is the same as that of the candidate delay amount generating circuit 510 in FIG. 5, that is, it is responsible for finding a plurality of candidate delay amounts corresponding to the plurality of candidate echo signals according to the channel impulse response (for example, the selection signal S1b is made). For the primary signal, six candidate delay quantities D _2a , D _2b , D _2c , D _3a , D _3b , D _3c ) are found. The following describes how other circuits operate.

The delay circuit 1050 is substantially the same as the delay circuit 420 of FIG. 5, with the main difference being that the signal fed to the delay circuit 1050 is the received signal y [ k ]. Based on the received approximate delay amount D , the delay circuit 1050 generates eight delayed but different delayed signals for the received signal y [ k ]: y [ k -( D - 3 )], y [ k - ( D - 2 )],..., y [ k -( D + 4 )].

The weight generating circuit 1020 is substantially the same as the weight generating circuit 520 in FIG. 5, and the main difference is that the signal sent to the weight generating circuit 1020 is the received signal y [ k ] and its delayed signal: y [ k -( D - 3 )], y [ k -( D - 2 )],..., y [ k -( D + 4 )]. More specifically, instead of replacing the filtered signal z [ k ] in FIG. 6 or FIG. 8 with the received signal y [ k ], and replacing each delayed signal z [ k -( D + m )] with a delay The weight generation circuit 1020 can be realized by the signal y [ k -( D + m )]. For each candidate delay amount, the weight generation circuit 1020 iteratively calculates a set of weights w _n,m , which can be summarized into a similar expression of four:

In practice, in order to make the comparison basis consistent, the initial values (n=0) of the weights of each candidate delay amount w _u,m can be set to be the same, but need not be limited to a specific value. It should be noted that, unlike the weight generation circuit 520 which returns the new weight w _{n + 1 , m} to the infinite impulse response filter 400 in FIG. _{5 ,} the new weight w _{n + 1 , m} generated by the weight generation circuit 1020 is not Will be fed back to other circuits. Each time a new iterative calculation is performed, the weight generation circuit 1020 can take the received signal y [ k ] corresponding to the different sampling index k and its delayed signal y [ k -( D + m )] to generate a new weight w _{n + 1 , m} .

When an iterative termination condition (eg, the number of iterations n reaches a predetermined value N) is established, the evaluation generation circuit 1030 calculates an evaluation E based on the latest weight w _n,m for the candidate delay amount currently used by the delay circuit 1050. . Similarly, the internal circuitry of the evaluation generation circuit 1030 can be the same as the evaluation generation circuit 530 presented in FIG. 7, that is _, the sum of squares or absolute values of the set of weights w _n,m is calculated.

Similarly, the higher the evaluation E calculated by the evaluation generating circuit 1030, the more likely the representative echo signal is to be a true echo signal. A memory (not shown) may be disposed in the selection circuit 1040 to temporarily store the evaluation of each candidate delay amount, and according to the evaluation, one or more real echo signals are selected from the plurality of candidate echo signals, according to which Generate an echo signal information.

Like the channel estimation device 400, the channel estimation device 1000 does not need to use subsequent circuits such as an equalizer, a demapping circuit, and a decoding circuit to determine the authenticity of the echo signal, and can effectively achieve the effect of saving computation time and computing resources.

Similarly, the delay circuit 1050 in the channel estimation device 1000 can also be shared by the time domain equalizer if desired to achieve the benefit of saving hardware costs.

Another embodiment of the present invention is a channel estimation method, and a flow chart thereof is shown in FIG. First, step S1101 finds P candidate delay amounts corresponding to P candidate echo signals (P is an integer greater than one) according to one channel impulse response of a received signal. Step S1102 is to set an integer index i equal to 1. In step S1103, the i-th candidate delay amount is set to a rough delay amount. Next, step S1104 is to provide M kinds of delay amounts (M is a positive integer greater than one) adjacent to the approximate delay amount. Step S1105: applying an infinite impulse response filtering process to the received signal according to the M kinds of delay amounts and M weights to generate a filtered signal and the M delayed signals corresponding to the M kinds of delay amounts of the filtered signal. . Step S1106 is to generate a new M weights according to the filtered signal and the M delayed signals. Step S1107 is to determine whether the number of iterations of updating the M weights has reached a preset value. If the result of the determination in step S1107 is NO, steps S1105 to S1107 are executed again. If the result of the determination in step S1107 is YES, then step S1108 is executed, that is, an ith evaluation is calculated based on the current latest M weights. Next, step S1109 is to determine whether the integer index i has been increased to be equal to the value P. If the result of the determination in the step S1109 is NO, the step S1110 is executed, that is, the integer index i is increased, and the steps S1103 to S1109 are executed again. If the result of the determination in step S1109 is YES, then step S1111 is performed, that is, one or more real echo signals are selected from the P candidate echo signals according to the previously generated P evaluations, and a generation is generated accordingly. Wave signal information.

It will be understood by those of ordinary skill in the art that the various operational changes previously described in the introduction of the channel estimation apparatus 500 can also be applied to the channel estimation method of FIG. 11 without further details.

Another embodiment of the present invention is a channel estimation method, and a flow chart thereof is shown in FIG. First, step S1201 finds P candidate delay amounts (P is an integer greater than one) corresponding to P candidate echo signals according to a channel impulse response of a received signal. Step S1202 is to set the integer index i to be equal to 1. In step S1203, the i-th candidate delay amount is set to a rough delay amount. Next, in step S1204, in order to provide M kinds of delay amounts adjacent to the approximate delay amount, corresponding M delayed signals (M is a positive integer greater than one) are generated for the received signals. Subsequently, step S1205 generates new M weights according to the received signal and the M delayed signals. Step S1206 is to determine whether the number of iterations of updating the M weights has reached a preset value. If the result of the determination in step S1206 is NO, steps S1205 to S1206 are executed again. If the result of the determination in step S1206 is YES, then step S1207 is executed, that is, an ith evaluation is calculated based on the current latest M weights. Step S1208 is to determine whether the integer index i has been increased to be equal to the value P. If the result of the determination in the step S1208 is NO, the step S1209 is executed, that is, the integer index i is increased, and the steps S1203 to S1208 are executed again. If the result of the determination in step S1208 is YES, then step S1210 is performed, that is, one or more real echo signals are selected from the P candidate echo signals according to the previously generated P evaluations, and a generation is generated accordingly. Wave signal information.

It will be understood by those of ordinary skill in the art to which the various operational changes previously described in the introduction of the channel estimation apparatus 1000 can also be applied to the channel estimation in FIG. The method, the details of which are not described again.

The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. In addition, the mathematical expressions in the present disclosure are intended to illustrate the principles and logic associated with the embodiments of the present invention, and the scope of the present invention is not limited unless otherwise specified. It will be understood by those of ordinary skill in the art that there are a variety of techniques, various circuit configurations and components that can achieve the physical representations of such mathematical expressions.

Claims (13)

A channel estimation apparatus includes: a candidate delay amount generation circuit for finding a plurality of candidate delay amounts corresponding to a plurality of candidate echo signals according to a channel impulse response of a received signal, and each time from the plurality of candidates Selecting a selected candidate delay amount from the delay amount; receiving an infinite impulse response filter, receiving the selected candidate delay amount and M weights, generating M kinds of delay amounts for the selected candidate delay amount, and according to the M kinds of delay amounts and the M The weights are subjected to an infinite impulse response filtering process to generate a filtered signal and the filtered signals correspond to the M delayed signals of the M kinds of delay amounts, wherein M is a positive integer greater than one; a weight generating circuit for iteratively generating a new M weights according to the filtered signal and the M delayed signals for each selected candidate delay amount, and requesting the infinite impulse response filter according to the new M weights Performing the infinite impulse response filtering process again; an evaluation generating circuit for selecting a candidate delay amount for each one, when a termination condition is established, according to the most The new M weights are calculated as an evaluation; and a selection circuit is configured to select one or more real echo signals from the plurality of candidate echo signals based on the evaluations, and generate an echo signal information accordingly. The channel estimation device of claim 1, wherein the weight generation circuit comprises: a correlation calculation circuit for respectively calculating a correlation between the filtered signal and the M delayed signals to generate M Correlation calculation result; a multiplication circuit for multiplying each of the M correlation calculation results by a specific parameter to generate M multiplication results; a temporary register for storing M previous weights; and a An adding circuit for adding each of the M multiplication results to a corresponding previous weight, To generate M new weights. The channel estimating apparatus according to claim 1, wherein a symbol n represents an iteration number index, k represents a sampling index, z [ k ] represents a kth sample of the filtered signal, and a symbol D represents the infinite impulse response. The selected candidate delay amount is currently used by the filter, and the M delayed signals are z [ k -( D + d ₁ )], z [ k -( D + d ₂ )], ..., z [ k -( D + d _M )], the symbols d ₁ , d ₂ , ..., d _M represent M different values close to or equal to zero, the symbol m represents one of the values d ₁ , d ₂ , ..., d _M , and the symbol μ represents the minimum One of the tunable parameters in the mean square algorithm, the weight generating circuit includes: a first operating circuit for generating a vector according to the filtered signal and the M delayed signals d _M )]]; M second operation circuits for generating M vectors according to the M delayed signals :[Σ _k ( z [ k -( D + m )]* z ^* [ k -( D + d ₁ )])...Σ _k ( z [ k -( D + m )]* z ^* [ k -( D + d _M )])]; a transposed circuit for the M vectors Transpose separately to generate M transpose vectors a vector multiplication circuit for vectoring With the M transpose vectors Multiplying each to generate M vector multiplication results; a multiplication circuit for multiplying the M vector multiplication results by a specific parameter to generate M multiplication results; a temporary register for Storing M previous weights; and an adding circuit for adding the M multiplication results to a corresponding previous weight to generate M new weights. The channel estimation device of claim 1, wherein the evaluation generation circuit comprises: a counting circuit for calculating a number of iterations of the weight generating circuit to update the M weights; And a square sum calculation circuit that controls the square sum calculation circuit to calculate a sum of squares of the latest M weights as the evaluation when the number of iterations reaches a predetermined value. The channel estimation apparatus according to claim 1, further comprising: a switching circuit, configured to provide the infinite impulse response filter according to the echo signal information generated by the selection circuit in a time domain equalization mode The selected candidate delay amount is employed. A channel estimation apparatus includes: a candidate delay amount generation circuit for finding a plurality of candidate delay amounts corresponding to a plurality of candidate echo signals according to a channel impulse response of a received signal, and each time from the plurality of candidates Selecting a selected candidate delay amount from the delay amount; a delay circuit for providing M kinds of delay amounts adjacent to the selected candidate delay amount, and generating corresponding M delayed signals for the received signal, wherein M is greater than one a positive integer; a weight generating circuit for iteratively generating a new M weights according to the received signal and the M delayed signals for each selected candidate delay amount; an evaluation generating circuit for each selected candidate a delay amount, when an iteration termination condition is established, calculating an evaluation based on the latest M weights generated by the weight generation circuit; and a selection circuit for selecting one of the plurality of candidate echo signals according to the evaluation Or a plurality of true echo signals, and accordingly generate an echo signal information. The channel estimation device of claim 6, wherein the weight generation circuit comprises: a correlation calculation circuit for respectively calculating a correlation between the received signal and the M delayed signals to generate M correlations a result of a calculation; a multiplication circuit for multiplying each of the M correlation calculation results by a specific parameter, To generate M multiplication results; a temporary register for storing M previous weights; and an adding circuit for adding the M multiplication results to a corresponding previous weight to generate M New weight. A channel estimation method includes: (a) finding a plurality of candidate delay amounts corresponding to a plurality of candidate echo signals according to a channel impulse response of a received signal; (b) selecting each of the plurality of candidate delay amounts each time Selecting a candidate delay amount, and performing: (b1) providing M kinds of delay amounts adjacent to the selected candidate delay amount, wherein M is a positive integer greater than one; (b2) receiving M weights, according to the M kinds of delay amounts The M weights apply an infinite impulse response filtering process to the received signal to generate a filtered signal and the filtered signals correspond to the M delayed signals of the M delay amounts; (b3) according to the filtered signal And the M delayed signals, iteratively generates new M weights, and re-executes steps (b2) and (b3); and (b4) when an iteration termination condition is established, the selection is based on the latest M weights. The candidate delay amount calculates an evaluation; and (c) selects one or more real echo signals from the plurality of candidate echo signals based on the evaluations, and generates an echo signal information accordingly. The channel estimation method according to claim 8, wherein the step (b3) comprises: respectively calculating a correlation between the filtered signal and the M delayed signals to generate M correlation calculation results; Each of the correlation calculation results are respectively multiplied by a specific parameter to generate M multiplication results; and the M multiplication results are each added to a corresponding previous weight to generate M new weights weight. The channel estimation method according to claim 8, wherein the symbol n represents an iteration number index, k represents a sampling index, z [ k ] represents a kth sample of the filtered signal, and symbol D represents the infinite impulse response. The selected candidate delay amount is currently used by the filter, and the M delayed signals are z [ k -( D + d ₁ )], z [ k -( D + d ₂ )], ..., z [ k -( D + d _M )], the symbols d ₁ , d ₂ , ... d _M represent M different values close to or equal to zero, the symbol m represents one of the values d ₁ , d ₂ , ..., d _M , and the symbol μ represents the minimum mean One of the arbitrarily adjustable parameters; the step (b3) includes: generating a vector according to the filtered signal and the M delayed signals z ^* [ k -( D + d ₁ )]...Σ _k z [ k ]* z ^* [ k -( D + d _M )]]; generating M vectors from the M delayed signals :[Σ _k ( z [ k -( D + m )]* z ^* [ k -( D + d ₁ )])...Σ _k ( z [ k -( D + m )]* z ^* [ k -( D + d _M )])]; the M vectors Transpose separately to generate M transpose vectors ; vector With the M transpose vectors Multiplying each to generate M vector multiplication results; multiplying the M vector multiplication results by a specific parameter to generate M multiplication results; and correspondingly multiplying the M multiplication results by one The previous weights are added to produce M new weights. The channel estimation method according to claim 8, wherein the step (b4) comprises: calculating an iteration number of updating the M weights; and calculating the latest M weights when the number of iterations reaches a preset value The sum of the squares is used as the evaluation. A channel estimation method, comprising: (a) finding a plurality of candidate delay amounts corresponding to the plurality of candidate echo signals based on a channel impulse response of a received signal; (b) selecting a selected candidate delay amount from the plurality of candidate delay amounts each time, and Performing: (b1) providing M kinds of delay amounts adjacent to the selected candidate delay amount, and generating corresponding M delayed signals for the received signal, where M is a positive integer greater than one; (b2) according to the received signal And the M delayed signals, iteratively generating new M weights; and (b3) calculating an evaluation for the selected candidate delay amount according to the latest M weights when an iteration termination condition is established; and (c) And evaluating, one or more real echo signals are selected from the plurality of candidate echo signals, and an echo signal information is generated accordingly. The channel estimation method according to claim 12, wherein the step (b2) comprises: respectively calculating a correlation between the received signal and the M delayed signals to generate M correlation calculation results; The correlation calculation results are each multiplied by a specific parameter to generate M multiplication results; and the M multiplication results are each added to a corresponding previous weight to generate M new weights.