TWI650862B - Folded channel trench mosfet - Google Patents

Abstract

A trench MOSFET device includes a body region and a source region, and the bump portion is along the MOSFET component The channel width direction is set such that the depth variations of the body region and the source region are set along the channel width direction. The bump portion increases the channel width of the MOSFET.

Description

Folding channel trench MOSFET

The present invention relates generally to integrated circuits, and more particularly to integrated circuit components having field effect transistors (FETs).

A field effect transistor (FET) is a semiconductor transistor component in which a voltage applied to an electrically insulating gate controls the flow of current between the source and the drain. An example of a FET is a metal oxide semiconductor FET (MOSFET) in which a gate electrode is insulated from a semiconductor body region by oxidizing an insulator. When the gate is loaded with a voltage, the resulting electric field passes through the oxide, forming an "inversion layer" or "channel" at the semiconductor-insulator junction. The inversion layer provides a channel through which current can pass. Changing the gate voltage modulates the conductivity of the layer, thereby controlling the current between the drain and the source. The MOSFETs can have different structures. In one example, the MOSFET can have a planar structure in which the gate, source, and drain are above the component and current flows in a path parallel to the surface. In another example, the MOSFET can have a vertical structure in which a trench filled with doped polysilicon extends from the source to the drain, and the sidewall and the floor are lined with a layer of thermally grown cerium oxide. Such trench MOSFET transistors allow current that does not contract to flow, thereby providing a smaller specific on-resistance.

FETs are suitable for a variety of power switching applications. In a special structure used in a battery protection circuit module (PCM), two FETs are arranged back to back with their drains connected in a floating structure Start. Fig. 1A shows a schematic view of such a structure. FIG. 1B shows such an element 100 connecting the battery protection circuit module PCM 102, the battery 104, and the load or charger 106. The gates for charging and discharging the FETs 120 and 130 in this example are independently driven by the controller integrated circuit (IC) 110, respectively. This configuration allows control of the current in both directions: charging to the battery and battery to the load. In normal charging and discharging operations, MOSFETs 120 and 130 are both turned "on" (i.e., conductive). When the battery 104 is overcharged or charged with an overcurrent condition, the controller IC 110 turns off the charge FET 120 and turns on the discharge FET 130. In the event of overdischarge or overcurrent, the controller IC 110 turns on the charge FET 120 and turns off the discharge FET 130.

It is against this background that various embodiments of the invention have been presented.

The present invention provides a folded channel trench MOSFET that achieves low channel resistance and reduces source-source resistance.

To achieve the above object, the present invention provides a trench MOSFET device characterized by comprising: a lightly doped epitaxial layer of a first conductivity type on a heavily doped semiconductor substrate of a first conductivity type; filled with a conductive material a gate trench extending in the lightly doped epitaxial layer; a body region of a second conductivity type opposite to the first conductivity type, in a portion of the lightly doped epitaxial layer, wherein the body region has a first relief portion along the channel width a direction setting; and a source region of the first conductivity type, at the top of the body region, wherein the source region has a second concavo-convex portion disposed along the channel width direction above the first concavo-convex portion, wherein the channel width of the MOSFET element is introduced The first and second concave and convex portions are enlarged.

The first conductivity type is an N type, and the second conductivity type is a P type.

The depths of the lightly doped epitaxial layers, the body regions, and the source regions vary along the channel width.

The lightly doped epitaxial layer has a third concavo-convex portion disposed along a channel width direction of the MOSFET element.

The depth of the third concavo-convex portion extends deep into the semiconductor substrate, deeper than other portions of the lightly doped epitaxial layer.

The depth of the first concavo-convex portion extends into the lightly doped epitaxial layer deeper than other portions of the body region.

The depth of the second concavo-convex portion extends into the body region deeper than other portions of the source region.

The tapered edges of the first and second concave and convex portions described above have an angle of between about 25 and 90 degrees.

A method for fabricating a trench MOSFET device, characterized in that it comprises: preparing a lightly doped epitaxial layer of a first conductivity type on a heavily doped semiconductor substrate of a first conductivity type; in a lightly doped epitaxial layer Preparing a gate electrode; in a portion of the lightly doped epitaxial layer, preparing a body region of a second conductivity type opposite to the first conductivity type, wherein the first relief portion of the body region is disposed along the channel width direction; and at the top of the body region A source region of the first conductivity type is prepared, wherein the source region has a second concavo-convex portion disposed along a channel width direction above the first concavo-convex portion.

The first conductivity type is an N type, and the second conductivity type is a P type.

The lightly doped epitaxial layer has a third concavo-convex portion disposed along a channel width direction of the MOSFET element.

The lightly doped epitaxial layer of the first conductivity type is prepared on the heavily doped semiconductor substrate of the first conductivity type, comprising: preparing a first epitaxial layer on the semiconductor substrate; and preparing a buried layer by using the first mask Wherein the first mask defines a third relief portion; and on the buried layer, a second epitaxial layer is prepared.

Wherein in the lightly doped epitaxial layer, preparing a gate electrode comprises: using a second mask, preparing a gate trench in the lightly doped epitaxial layer, wherein the second mask defines a gate trench; The insulating material lines the inner surface of the gate trench; and the gate trench is filled with a conductive material by etch back.

Wherein in a portion of the lightly doped epitaxial layer, a body region of a second conductivity type opposite to the first conductivity type is prepared, including: preparing a first insulating material layer over the lightly doped epitaxial layer; and forming a first insulating material layer Upper, preparing a second insulating material layer, wherein the first insulating material layer is resistant to the diffusion process of etching the second insulating material layer; on the lightly doped epitaxial layer, the third mask is prepared, wherein the third mask has a Opening to define a first concavo-convex portion; and in the lightly doped epitaxial layer, injecting a dopant of a second conductivity type to form a body region, wherein a dopant of the second conductivity type is implanted under the opening to lightly doped epitaxial The deeper part of the layer to form the first concave and convex portion.

The first insulating material is nitride.

The second insulating material is an oxide.

The first insulating material layer has a thickness of about 200 Å to 500 Å.

The second insulating material layer has a thickness of about 500 Å to 1000 Å.

The angle of the first concave and convex portion follows the slope of the opening.

Wherein the source region of the first conductivity type is prepared in the top of the body region, comprising: preparing a body region by using a third mask, wherein the third mask has an opening to define the first concave and convex portion; and in the body region, A dopant of a first conductivity type is implanted to form a source region, wherein a dopant of the first conductivity type is implanted deeper into the body region below the opening to form a second relief portion.

The method further includes: preparing a contact trench by using a contact trench mask; contacting the inner surface of the trench with a first conductive material; filling the contact trench with a second conductive material, wherein the second conductive material is different from the first conductive material a conductive material; and etching the second conductive material.

The advantage of the folded channel trench MOSFET of the present invention over the prior art is that the present invention achieves low channel resistance and reduces source-source resistance by folding the channel region of the trench MOSFET.

100, 200, 500, 700‧‧‧ components

102‧‧‧Circuit module PCM

104‧‧‧Battery

106‧‧‧Load or charger

110‧‧‧Controller IC

120‧‧‧Charge FET

130‧‧‧Discharge FET

220, 230‧‧‧ MOSFET

242‧‧‧Back metal

244, 710, 810‧‧‧ substrates

246, 720, 812‧‧ ‧ epitaxial layer

246‧‧‧Extension drift layer

246‧‧‧Extension area

246, 720‧‧‧Lightly doped epitaxial layer

250, 604‧‧‧ body area

252‧‧‧ trench

254‧‧‧Insulators

256‧‧‧Electrically insulated gate electrode

260, 406‧‧‧ source

260, 406, 606, 750, 850, 660a‧‧‧ source area

265‧‧‧ source metal layer

267‧‧‧Source connector

280, 282‧ ‧ channel end point

284, 286‧‧ ‧ protection ring

400‧‧‧FinFET

400‧‧‧Optoelectronics

400‧‧‧FinFET transistor

402‧‧‧矽Ontology

404‧‧‧汲polar

404‧‧‧Bungee Area

408‧‧‧ channel

410‧‧‧ gate structure

412, 860‧‧‧ dielectric layer

600, 700‧‧‧ trench MOSFET components

600‧‧‧ trench MOSFET

602, 742, 842a‧‧‧ gate electrodes

725, 735, 755‧‧‧ concave part

730, 830‧‧‧ body area

740, 840‧‧ ‧ gate trench

790‧‧‧ angle

812‧‧‧EPI

812, 820‧‧‧EPI layer

814‧‧‧buried layer

819‧‧‧ mask

822, 824‧‧‧ insulation

824‧‧‧ gate oxide layer

826‧‧‧First insulation material

826‧‧ ‧

826‧‧‧nitriding layer

826‧‧‧passivation layer

828‧‧‧Second insulation material

828‧‧‧Insulation materials

828‧‧‧Oxide layer

829‧‧‧ body mask

842‧‧‧Electrical materials

869‧‧‧Photoresist

870‧‧‧Contact groove

872‧‧‧Wall metal

874‧‧‧Electrical plug

880‧‧‧metal layer

824a‧‧‧Oxide

A-A'‧‧‧ Line A-A'

B-B'‧‧‧ Line B-B'

L‧‧‧ channel length

W‧‧‧ channel width

Other features and advantages of the present invention will become apparent after reading the following detailed description, in which <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Schematic diagram of a module (PCM); Figure 2A shows a schematic plan view of a conventional switching element having two back-to-back MOSFETs in a side-by-side configuration; Figure 2B shows a line along the AA' line of Figure 2A, Figure 2A Schematic diagram of a switching circuit; Figure 3 shows a schematic diagram of a conventional planar MOSFET device; Figure 4 shows a schematic diagram of a conventional FinFET device; Figure 5 shows a schematic diagram of a folded channel planar MOSFET device; Figure 6 shows a conventional trench Schematic diagram of a MOSFET device; Figure 7 shows a schematic diagram of a trench MOSFET device in accordance with various aspects of the present invention; and Figure 8AA'-29AA' shows a trench MOSFET process in the A-A' profile shown in FIG. A cross-sectional view; and an 8BB'-29BB' diagram showing a cross-sectional view of a trench MOSFET process in the B-B' profile shown in FIG.

Specific embodiments of the present invention are further described below in conjunction with the drawings.

introduction

Figure 2A shows a conventional layout of an element 200 having two fully insulated vertical MOSFETs 220 and 230, both having respective termination and channel terminations. A large amount of dead space is required between MOSFET 1 and MOSFET 2 to provide respective termination regions and channel terminations.

A cross-sectional view of the element shown in Fig. 2A is shown in Fig. 2B. Each vertical MOSFET 220/230 includes a plurality of active element cells formed in a lightly doped epitaxial layer 246 grown on a heavily doped substrate 244. In this example, the heavily doped (e.g., N+) substrate 244 acts as a drain and the drains of the two MOSFETs 220 and 230 are electrically coupled together by a back metal 242 formed on the back side of the substrate 244. The active elements are formed in a lightly doped epitaxial drift layer 246 having the same conductivity type (eg, N-type) grown on the front side of the substrate 244. The conductivity type of body region 250 is opposite (eg, P-type) to substrate 244 and epitaxial region 246, formed in a portion of epitaxial layer 246. A trench 252 is formed in the epitaxial layer 246 and then lined with an insulator 254 (e.g., an oxide). An electrically insulating gate electrode 256, for example made of polycrystalline germanium (polysilicon), is placed in trench 252. A heavily doped (e.g., N+) source region 260 of the same conductivity type as substrate 244 is formed adjacent trench 252. An external electrical junction to the source region is formed by source metal layer 265 and vertical source junction 267. Channel terminations 280, 282 are prepared using an insulated electrode similar to the gate electrode, with the gate electrode passing through the source-type conductive region in the epitaxial region and shorted to the epitaxial drift region. The termination also includes guard rings 284, 286 formed by the body-type conductive regions.

A key feature of this component is the source-to-source resistance of the two MOSFETs 220 and 230. This resistor must be made as small as possible. The total source-source resistance R _ss is given by:

Where R _ch is the resistance of the conductive path through source 260 and body region 250 when the gate is turned on, R _drift is the resistance of epitaxial layer 246, R _backmetal is the resistance of back metal 242 and R _substrate is the resistance of substrate 244 . Since the channel resistance (R _ch ) is one of the largest components of the total source-source resistance R _ss , the conductive path resistance (R _ch ) must be made as small as possible.

Figure 3 shows a schematic diagram of channel length (L) and channel width (W) in a conventional planar MOSFET. As is well known to those skilled in the art of semiconductor components, the channel resistance (R _ch ) is proportional to the channel length (L) and inversely proportional to the channel width (W). The channel resistance (R _ch ) is also inversely proportional to the channel density for a given wafer size. In order to reduce the channel resistance (R _ch ), the conventional method is to reduce the cell size of the MOSFET, thereby increasing the channel density. However, due to manufacturing levels, there is a limit to the distance between the socket in one unit cell and the other socket in one adjacent unit cell.

FINFET

A fin field effect transistor ("FinFET") is a non-planar transistor built on a germanium substrate on an insulator. Hisamoto et al., "Folding Channel MOSFETs for the Deep Tenth Micron Age", 1032 IEDM (1998), introduces a FinFET structure that includes a vertical ultra-thin fin, two self-aligned to source And the gate of the drain, a raised source and drain to reduce parasitic resistance, and a quasi-planar structure. Figure 4 shows a perspective view of a modified FinFET transistor 400. The transistor 400 is fabricated from a crucible body 402 that includes a drain region 404, a source region 406, and a fin channel region 408 coupled between the drain region 404 and the source region 406. The drain 404, source 406, and fin-channel 408 are covered by a dielectric layer 412. The gate structure 410 passes through the fin channel 408 and is wound thereon such that the gate structure interfaces with the three sides of the channel 408. The FinFET 400's structure provides improved electrical control over channel conduction, helping to reduce leakage current levels and overcome other short channel effects. In addition, it is noted that the FinFET channel is wound around the channel 408 by a width that is approximately twice the height of the channel region fin. Since then, various methods have been proposed to increase the channel width of a planar MOSFET by folding an element such as the element 500 shown in FIG.

Fold the channel trench MOSFET to reduce R _Ss

In accordance with various aspects of the present invention, to clarify the advantages of folded-channel MOSFETs, conventional trench MOSFETs must be understood. Figure 6 shows a portion of a conventional trench MOSFET component 600. Trench MOSFET 600 includes a gate electrode 602, a body region 604, and a source region 606 (not shown) above the substrate. It is to be noted that although FIG. 6 shows only one gate electrode 602, there may be another gate electrode in the vicinity of the edge of the source region 606a. The channel length (L) of the trench MOSFET 600 is between the bottom of the source region 606 and the bottom of the body region 604 (ie, the top of the substrate), and the channel width (W) is the third dimension of the cross-section as shown. In order to improve the total source-source resistance R _ss by reducing the channel resistance (R _ch ) of the trench MOSFET 600, it is necessary to reduce its channel length (L) or increase its channel width (W).

Aspects of the invention achieve low channel resistance by "folding" the channel region of the trench MOSFET. FIG. 7 shows a schematic diagram of trench MOSFET component 700 in accordance with various aspects of the present invention. It is to be noted that although FIG. 7 shows only a part of the active element cells, the element 700 may have a plurality of active element cells. Trench MOSFET element 700 includes a lightly doped epitaxial layer 720 (e.g., N-) of a first conductivity type formed over a heavily doped semiconductor substrate 710 of the same conductivity type (e.g., N+). In contrast to substrate 710 and epitaxial layer 720 (eg, P-type), body region 730 having a second conductivity type is formed in a portion of lightly doped epitaxial layer 720. A gate trench 740 filled with an electrically insulating gate electrode 742 (e.g., polysilicon) extends in the lightly doped epitaxial layer 720. A heavily doped source region 750 of the same conductivity type as the substrate (e.g., N+) is formed adjacent the trench in the body region 730.

As shown in FIG. 7, the epitaxial layer 720 has a concavo-convex portion 725 (or a recessed portion) disposed along the channel width direction of the element 700 such that the depth of the epitaxial layer 720 varies at the interface between the epitaxial layer 720 and the substrate 710. Set along the width of the channel. In addition, the body region 730 has a concavo-convex portion 735 disposed along the channel width direction above the concavo-convex portion 725 such that the depth variation of the body region 730 is disposed along the channel width direction at the interface between the body region 730 and the epitaxial layer 720. The source region 750 has a concavo-convex portion 755 disposed along the channel width direction above the concavo-convex portions 725 and 735 such that the depth variation of the source region 750 is along the channel width direction at the interface between the source region 750 and the body region 730. Settings. As shown, the relief portions 725, 735 and 755 each have a concave bottom surface and a tapered edge. After the introduction of the concavo-convex portions 725, 735, and 755, the channel of the element 700 is "folded" as shown in Fig. 7, thereby reducing the channel width and reducing the channel resistance. In one example, when the tapered edge angle 790 of the relief portions 725, 735, and 755 is about 45 degrees, the channel resistance can be reduced by 16.3%. It is to be noted that the sharper the angle 790, the more significant the reduction in channel resistance (R _ch ). By way of example, but not by way of limitation, the angle of the tapered edges of the relief portions 725, 735, and 755 is between about 25 and 90 degrees.

Figs. 8AA'-29AA' and 8BB'-29BB' show the preparation process of the trench MOSFET in the A-A' and B-B' sections shown in Fig. 7. In the 8AA' and 8BB' drawings, the process uses the semiconductor substrate 810 of the first conductivity type as a starting material. In some examples, substrate 810 can be a heavily doped N-type (N+) germanium wafer. A thin epitaxial layer (EPI) 812 is then deposited over the N+ substrate 810. In some examples, EPI 812 is a lightly doped N-type layer of germanium. In the 9AA' and 9BB' diagrams, a buried layer mask 819 is used on the EPI layer 812, and then a lightly doped N-type impurity (N+) is implanted to form a buried layer 814. As shown in Figure 9AA', a portion of the EPI 812 is covered by a buried layer mask 819 to define the location of the relief portion. In the 10AA' and 10BB diagrams, impurities are driven, for example, by annealing. It is to be noted that, as shown in FIG. 10AA', after the buried layer mask 819 is removed in the annealing process, the portion of the EPI 812 covered by the buried layer mask 819 remains and is exposed. In the next step, a thick EPI layer 820 of the same conductivity type as the substrate 810 is prepared over the substrate 810, as shown above in Figures 11AA' and 11BB'. In some embodiments, the thick EPI layer 820 is a lightly doped N-type layer. In some configurations, the thick EPI layer 820 has a thickness between about 1 [mu]m and 3 [mu]m. As shown in FIG. 11AA', the burying of the buried layer implant in the above steps results in the portion of the EPI layer 820 previously covered by the buried layer mask 819 being thicker and deeper, which was previously not covered by the buried layer mask 819. Some areas are thinner and lighter. The thicker and deeper regions of the EPI layer 820 form a first relief portion.

In the 12A' and 12BB' figures, an insulating layer 822 is prepared over the EPI layer 820. In some embodiments, the insulating layer 822 is an oxide layer. A photoresist (not shown) is used over the insulating layer 822 and patterned to define the gate trenches. The patterned photoresist includes an opening at the location of the gate trench. As shown in Figures 13AA' and 13BB', the portion of the insulating layer 822 exposed to the etchant through the opening in the photoresist is etched away by an etching process. After removing the photoresist, left The remaining portion of insulating layer 822 acts as a mask, and the corresponding portion of the underlying EPI layer 820 is etched down to form gate trenches 840, as shown in Figures 14AA' and 14BB'. Then, the remaining portion of the insulating layer 822 is removed.

A sacrificial oxide layer (not shown) can then be grown and removed to improve the surface of the crucible. An insulating layer (e.g., gate oxide) 824 is formed over the EPI layer 820 over the inner surface of the gate trench 840, as shown in Figures 15AA' and 15BB'. In panels 16AA' and 16BB', conductive material 842 is deposited over gate oxide layer 824. In some embodiments, the electrically conductive material can be an in situ doped or undoped polysilicon. Then, the conductive material 842 is etched back to form the gate electrode 842a as shown in Figs. 17AA' and 17BB'. In the 18AA' and 18BB' diagrams, an annealing process is performed. As shown in Fig. 18BB', a thin layer of oxide 824a can be formed over gate electrode 842a by adding some oxygen to the annealing recipe.

In the 19A' and 19BB' diagrams, a thin layer of a first insulating material 826 is deposited over the gate oxide layer 824. In some embodiments, the first insulating material 826 has a thin layer thickness ranging from 200 Å to 500 Å. In the 20A' and 20BB' views, a second layer of insulating material 828 is deposited over the thin layer of first insulating material 826. In some embodiments, the second insulating material 828 has a layer thickness of about 500 Å to 1000 Å. Thin layer 826 and layer 828 are two different insulating materials, each of which is resistant to etching of another material. That is, the thin layer of the first insulating material 826 can resist the etching process of etching the second insulating material 828 layer, and vice versa. The thin layer of the first insulating material 826 can form an etch end point for subsequent etching on the second insulating material 828 layer. In some embodiments, the thin layer 826 is a nitride layer and the second insulating material 828 layer is an oxide layer. The insulating material 828 is treated such that the edges of the opening are sloped or tapered after etching. For example, the surface can be doped or implanted to increase the etch depth, improve the dicing, and be used for wet etching. If plasma etching is used, oxygen can be added during the etching to etch the photoresist to form a slanted edge. Therefore, the opening slope of the desired angle can be customized.

Then, body injection and bulk diffusion are performed. In the 21A' and 21BB' diagrams, a body mask 829 is used for bulk implantation. It should be noted that the body mask 829 has an opening indicating In the A-A' plane, not in the B-B' plane. As shown in Figures 22AA' and 22BB', dopants are implanted into EPI layer 820 through oxide layer 828 and thin nitride layer 826. The conductivity type of the doped ions is opposite to the doping of the substrate 810. In some embodiments, for an N-channel element, the dopant ion can be a boron ion. In some embodiments, phosphorus or arsenic ions can be used for the P-channel element. Since the oxide layer 828 and the passivation layer 826 under the mask opening are not thick, the dopant can be implanted deeper into the EPI layer 820 below the opening to form a second relief. The angle of the relief portion follows the slope of the oxide opening. As shown in Figures 23AA' and 23BB', the dopant atoms are activated by heat and the dopant is driven to diffuse to form body regions 830.

After the body region 830 is prepared, source implantation and source diffusion are performed. First, as shown in Figs. 24AA' and 24BB', source implantation is performed through the same opening. The conductivity type of the doped ions is the same as the doping of the substrate 810. In some embodiments, arsenic ions can be implanted for the N-channel element. For P-channel components, it is also possible to implant boron ions. Since the oxide layer 828 and the nitride layer 826 under the mask opening are not thick, the dopant can be implanted into a deeper portion of the body region 830 below the opening to form a third concavo-convex portion. In the 25A' and 25BB' diagrams, a source region 850 is formed in the body region 830 using a standard diffusion process. Then, as shown in Figures 26AA' and 26BB', oxide layer 828 and nitride layer 826 are removed in accordance with standard processes.

As shown in Figures 27AA' and 27BB', a dielectric layer 860, such as an oxide, is deposited over the gate oxide layer 824. In some embodiments, the dielectric layer 860 can be formed by a low temperature oxide followed by a layer of barium glass (BPSG) containing boric acid.

On the dielectric layer 860, a contact photoresist 869 is used, the pattern of which has an opening at the location where the trench is contacted. In the 28AA' and 28BB' diagrams, portions of the dielectric layer 860 that are not covered are removed by an etching process, and contact trenches 870 are formed in the body region 830. In the 29AA' and 29BB' drawings, the inner surface of the groove 870 is first lined with the surrounding metal 872. In some embodiments, the perimeter metal 872 can be titanium (Ti) and titanium nitride (TiN). In the contact trench 870, tungsten (W) can be completely deposited The conductive material is then etched back up to the surface of the dielectric layer 860 to form a conductive plug 874. Finally, as shown in Figures 29AA' and 29BB', a metal layer 880 is deposited thereon. In some embodiments, the metal layer 880 can be aluminum (Al) or aluminum copper (AlCu).

Although the invention has been described in detail with respect to certain preferred versions, other versions are possible. Therefore, the scope of the invention should be construed as being limited by the scope of the appended claims. Any socket (whether preferred or not) can be combined with any other socket (whether preferred or not). In the following claims, the indefinite article "a" or "an" The scope of the attached patent application should not be construed as a limitation of meaning and function unless the meaning of the function is clearly indicated by "meaning". Any item in the scope of patent application that does not carry out a specific function and accurately indicates "meaning is" should not be construed as US § 112. "meaning" or "step" as described in 6 of 35.

Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

Claims (20)

A trench MOSFET device comprising: a lightly doped epitaxial layer of a first conductivity type on a heavily doped semiconductor substrate of the first conductivity type; a gate trench filled with a conductive material, Extending in the doped epitaxial layer; a body region of a second conductivity type opposite to the first conductivity type, in a portion of the lightly doped epitaxial layer, wherein the body region has a first concavo-convex portion along a channel width a direction setting; and a source region of the first conductivity type, at the top of the body region, wherein the source region has a second concavo-convex portion disposed along the width direction of the channel above the first concavo-convex portion, wherein the MOSFET The channel width of the component increases as the first relief portion and the second relief portion are introduced; wherein the depth of the first relief portion extends into the lightly doped epitaxial layer to be deeper than other portions of the body region The place. The component of claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type. The component of claim 1, wherein the lightly doped epitaxial layer, the body region, and the source region have a depth that varies along the width of the channel. The device of claim 1, wherein the lightly doped epitaxial layer has a third concavo-convex portion disposed along a width direction of the channel of the MOSFET element. The element of claim 4, wherein a depth of the third uneven portion extends into the semiconductor substrate, more than other portions of the lightly doped epitaxial layer Deep place. The element of claim 1, wherein the depth of the second relief portion extends into the body region deeper than other portions of the source region. The element of claim 1, wherein the first concavo-convex portion and the tapered edge of the second concavo-convex portion have an angle of between about 25 and 90 degrees. A method for fabricating a trench MOSFET device, comprising: preparing a lightly doped epitaxial layer of the first conductivity type on a heavily doped semiconductor substrate of a first conductivity type; in the lightly doped epitaxial layer Preparing a gate electrode; in a portion of the lightly doped epitaxial layer, preparing a body region of a second conductivity type opposite to the first conductivity type, wherein the first relief portion of the body region is along a channel width direction And a source region of the first conductivity type is prepared in the top of the body region, wherein the source region has a second concavo-convex portion disposed along a width direction of the channel above the first concavo-convex portion; The depth of the first relief portion extends into the lightly doped epitaxial layer deeper than other portions of the body region. The method of claim 8, wherein the first conductivity type is an N type and the second conductivity type is a P type. The method of claim 8, wherein the lightly doped epitaxial layer has a third concavo-convex portion disposed along a width direction of the channel of the MOSFET element. The method of claim 8, wherein the first conductivity type Preparing the lightly doped epitaxial layer of the first conductivity type on the heavily doped semiconductor substrate, comprising: preparing a first epitaxial layer on the semiconductor substrate; and preparing a buried layer by using a first mask Wherein the first mask defines a third concavo-convex portion; and on the buried layer, a second epitaxial layer is prepared. The method of claim 8, wherein the gate electrode is prepared in the lightly doped epitaxial layer, comprising: preparing a gate in the lightly doped epitaxial layer by using a second mask a pole trench, wherein the second mask defines the gate trench; an inner surface of the gate trench is lined with an insulating material; and the gate trench is filled with a conductive material by etch back. The method of claim 8, wherein in a portion of the lightly doped epitaxial layer, the body region of the second conductivity type opposite to the first conductivity type is prepared, including: the lightly doped epitaxial a layer of a first insulating material is prepared over the layer; and a second layer of insulating material is formed over the layer of the first insulating material, wherein the layer of the first insulating material is resistant to etching the diffusion process of the second layer of insulating material; Forming a third mask on the lightly doped epitaxial layer, wherein the third mask has an opening to define the first concavo-convex portion; and in the lightly doped epitaxial layer, injecting the second conductivity type A dopant is formed to form the body region, wherein the dopant of the second conductivity type is implanted deeper into the lightly doped epitaxial layer below the opening to form the first relief portion. The method of claim 13, wherein the first insulating material layer is a nitride layer. The method of claim 13, wherein the second layer of insulating material is an oxide layer. The method of claim 13, wherein the first insulating material layer has a thickness of about 200 Å to 500 Å. The method of claim 13, wherein the second layer of insulating material has a thickness of about 500 Å to 1000 Å. The method of claim 13, wherein the angle of the first concave-convex portion follows the slope of the opening. The method of claim 8, wherein the preparing the source region of the first conductivity type in the top of the body region comprises: preparing the body region by using a third mask, wherein the The third mask has an opening to define the first concavo-convex portion; and in the body region, the dopant of the first conductivity type is implanted to form the source region, wherein the dopant of the first conductivity type The deeper portion of the body region below the opening is injected to form the second concave and convex portion. The method of claim 8, further comprising: preparing a contact trench by using a contact trench mask; lining the inner surface of the contact trench with a first conductive material; using a second A conductive material fills the contact trench, wherein the second conductive material is different from the first conductive material; and the second conductive material is etched back.