[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TWI649845B - 半導體封裝結構及其製造方法 - Google Patents

半導體封裝結構及其製造方法 Download PDF

Info

Publication number
TWI649845B
TWI649845B TW106125194A TW106125194A TWI649845B TW I649845 B TWI649845 B TW I649845B TW 106125194 A TW106125194 A TW 106125194A TW 106125194 A TW106125194 A TW 106125194A TW I649845 B TWI649845 B TW I649845B
Authority
TW
Taiwan
Prior art keywords
packaging
layer
redistribution
package structure
semiconductor package
Prior art date
Application number
TW106125194A
Other languages
English (en)
Other versions
TW201826462A (zh
Inventor
徐宏欣
林南君
張簡上煜
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Publication of TW201826462A publication Critical patent/TW201826462A/zh
Application granted granted Critical
Publication of TWI649845B publication Critical patent/TWI649845B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02335—Free-standing redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明提供半導體封裝結構及其製造方法。半導體封裝結構包括重佈線結構、封裝結構以及第二封裝層。重佈線結構具有彼此相對的第一與第二表面。封裝結構位於第一表面上。封裝結構包括晶粒、第一封裝層、重佈線層以及多個第二導電端子。晶粒具有位於其上的多個第一導電端子。第一封裝層包覆晶粒。第一封裝層暴露出至少一部分的第一導電端子。重佈線層位於第一封裝層上。重佈線層電性連接至暴露出的第一導電端子。多個第二導電端子電性連接於重佈線層與重佈線結構之間。第二封裝層包覆封裝結構。第二封裝層暴露出至少一部分的第二導電端子。

Description

半導體封裝結構及其製造方法
本發明是有關於一種半導體封裝結構，且特別是有關於一種扇出（fan-out）型半導體封裝結構。
近年來半導體封裝技術不斷進展，以發展出體積更小、重量更輕、整合度（integration level）更高且製造成本更低的產品。舉例而言，目前已發展出晶圓級扇入（fan-in）封裝。扇入封裝具有在連接於對應的晶粒的區域內的輸入/輸出（input/output）端子。然而，由於輸入/輸出端子被限制在晶粒的表面，此種封裝類型被限制在僅需至多200至300的連接數目的低階元件。
本發明提供一種半導體封裝結構及其製造方法，可相容於更高的輸入/輸出連接數目，且能夠有效地降低製造成本。
本發明的半導體封裝結構包括重佈線結構、至少一封裝結構以及第二封裝層。重佈線結構具有第一表面以及相對於第一表面的第二表面。至少一封裝結構位於重佈線結構的第一表面上。至少一封裝結構包括至少一晶粒、第一封裝層、重佈線層以及多個第二導電端子。至少一晶粒具有位於至少一晶粒上的多個第一導電端子。第一封裝層包覆至少一晶粒。第一封裝層暴露出至少一部分的多個第一導電端子。重佈線層位於第一封裝層上。重佈線層電性連接至被第一封裝層暴露出的第一導電端子。多個第二導電端子電性連接於重佈線層與重佈線結構之間。第二封裝層包覆至少一封裝結構。第二封裝層暴露出至少一部分的多個第二導電端子。
在本發明的一實施例中，重佈線結構包括至少一介電層以及嵌入於至少一介電層中的多個導電單元。多個導電單元包括多個第一接合墊、多個第二接合墊以及多個互聯結構。多個第一接合墊位於重佈線結構的第一表面。多個第二導電端子經設置以對應於多個第一接合墊。多個第二接合墊位於重佈線結構的第二表面。多個互聯結構電性連接至少一部分的多個第一接合墊與至少一部分的多個第二接合墊。
在本發明的一實施例中，重佈線結構包括印刷電路板或有機封裝基板。
本發明的半導體封裝結構的製造方法包括下列步驟。形成至少一封裝結構。至少一封裝結構包括至少一晶粒、第一封裝層、重佈線層以及多個第二導電端子。至少一晶粒具有位於其上的多個第一導電端子。第一封裝層包覆至少一晶粒且暴露出至少一部分的多個第一導電端子。重佈線層位於第一封裝層上且電性連接至被第一封裝層暴露出的第一導電端子。多個第二導電端子位於重佈線層上。將至少一封裝結構耦合至重佈線結構的第一表面。至少一封裝結構的多個第二導電端子電性連接至重佈線結構。以第二封裝層包覆至少一封裝結構。
在本發明的一實施例中，多個第二導電端子中的每一者包括導電柱、導電凸塊或其組合。
在本發明的一實施例中，將重佈線結構與至少一封裝結構耦合的步驟在包覆至少一封裝結構的步驟之前。
在本發明的一實施例中，將重佈線結構與至少一封裝結構耦合的步驟與包覆至少一封裝結構的步驟包括下列子步驟。在載體上形成重佈線結構。重佈線結構包括至少一介電層與嵌入於至少一介電層中的多個導電單元，且至少一介電層暴露出至少一部分的多個導電單元。將至少一封裝結構置於重佈線結構的第一表面上。第二導電端子與被至少一介電層暴露出的導電單元電性連接。於重佈線結構的第一表面上形成第二封裝層。自重佈線結構移除載體。
在本發明的一實施例中，將重佈線結構與至少一封裝結構耦合的步驟與包覆至少一封裝結構的步驟包括下列子步驟。提供重佈線結構。重佈線結構包括至少一介電層以及嵌入於至少一介電層中的多個導電單元，且至少一介電層暴露出至少一部分的多個導電單元。將至少一封裝結構置於重佈線結構的第一表面上。第二導電端子與至少一介電層暴露出的導電單元電性連接。在重佈線結構的第一表面上形成第二封裝層。
在本發明的一實施例中，包覆至少一封裝結構的步驟在將重佈線結構與至少一封裝結構耦合的步驟之前。
在本發明的一實施例中，包覆至少一封裝結構的步驟以及將重佈線結構與至少一封裝結構耦合的步驟包括下列子步驟。提供載體。將至少一封裝結構置於載體上。以第二封裝層包覆至少一封裝結構。移除至少一部分的第二封裝層以暴露出至少一部分的多個第二導電端子。在第二封裝層上形成重佈線結構，以與被第二封裝層暴露出的第二導電端子電性連接。自至少一封裝結構以及第二封裝層移除載體。
基於上述，封裝結構的第一封裝層在每一晶粒的周圍提供額外的空間，以使得在晶粒上的第一導電端子可經由重佈線層而被連接至此額外的空間。基於封裝結構的扇出（fan-out）配置，此封裝結構可相容於更高的輸入/輸出連接數目。此外，可改善封裝結構的電性表現以及散熱表現。相似地，由於將封裝結構嵌入於第二封裝層且將重佈線結構與封裝結構的第二導電端子耦合，半導體封裝結構形成另一扇出封裝結構。因此，可達到更高的輸入/輸出連接數目。此外，重佈線結構可取代習知的矽穿孔（through silicon via，TSV）中介層，以降低製造成本。再者，重佈線層與重佈線結構分別在不同的扇出製程中被形成。因此，可降低封裝結構的翹曲程度（warpage level）。據此，半導體封裝結構可包含具有較複雜設計的重佈線結構。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1G是依照本發明一實施例繪示的封裝結構100的製造方法的剖視示意圖。
請參照圖1A，於載體108上形成多個晶粒106。載體108可由玻璃、塑料或其他適合的材料構成。每一晶粒106具有形成於其上的多個第一導電端子102。可經由以下的步驟製造晶粒106。首先，提供具有多個墊102’的晶圓（未繪示）。多個墊102’形成於晶圓上。隨後，形成覆蓋墊以及晶圓的鈍化層（未繪示）。圖案化鈍化層以產生多個鈍化圖案104。舉例而言，可經由光微影與蝕刻製程以對鈍化層進行圖案化。鈍化圖案104暴露出至少一部分的墊102’。之後，在墊102’上形成第一導電端子102。可經由鍍著製程（plating process）形成第一導電端子102。舉例而言，鍍著製程可為電鍍、無電鍍、浸鍍（immersion plating）或其類似者。接著，由相對於第一導電端子102的背面研磨晶圓，且切割晶圓以得到多個晶粒106。值得注意的是，每一晶粒106的具有第一導電端子102形成於其上的表面稱作晶粒106的主動面（active surface）。
在一些實施例中，附著層110可設置於載體108與晶粒106之間，以暫時地增進晶粒106與載體108之間的附著性。附著層110可為光熱轉換（light to heat conversion，LTHC）附著層或其他適合的附著層。值得注意的是，在圖1A中兩個晶粒106經形成於載體108上，然而本發明並不以此為限。在其他實施例中，單一晶粒106或多於兩個的晶粒106可經設置於載體108上。
請參照圖1B，在載體108上形成第一封裝層112，以包覆晶粒106。在一些實施例中，第一封裝層112可包括經由封膠製程（molding process）形成的封膠材料（molding compound）。在其他實施例中，第一封裝層112可由絕緣材料所形成，絕緣材料例如是環氧樹脂或其他適合的樹脂。
請參照圖1C，薄化第一封裝層112直至第一導電端子102的頂面被暴露出來。如圖1C所示，第一封裝層112暴露出部分的第一導電端子102。在一些實施例中，在第一封裝層112經薄化以暴露出第一導電端子102的頂面之後，更對第一導電端子102進行蝕刻製程。舉例而言，部分移除第一導電端子102以使得第一導電端子102的頂面些微地低於第一封裝層112的頂面。在一些實施例中，第一導電端子102的頂面比第一封裝層112的頂面低1 μm至3 μm。如此一來，第一封裝層112與第一導電端子102的表面粗糙度提高，以使其對於後續形成於其上的膜層可具有較佳的附著性。舉例而言，可藉由機械研磨、化學機械研磨、蝕刻或其他適合的方法以達成薄化製程。對於第一導電端子102進行的蝕刻製程可包括非等向性蝕刻或等向性蝕刻。
請參照圖1D，於第一封裝層112上形成重佈線層114，且將重佈線層114電性連接至第一導電端子102。重佈線路層114可包括至少一介電層116以及嵌入於介電層116的多個導電單元118。如圖1D所示，重佈線層114包括三層介電層116。然而，介電層116的數量可依據電路設計而調整，本發明並不以此為限。導電單元118可包括多個接合墊120、多個接合墊122以及多個互聯結構124。接合墊120經設置以面對第一導電端子102。最底層的介電層116暴露出接合墊120，以使墊120與其他構件電性連接。舉例而言，接合墊120可直接接觸第一導電端子102以使晶粒106與重佈線層114之間形成電性連接。接合墊122經設置於重佈線層114的相對於第一導電端子102的表面。最上層的介電層116暴露出接合墊122，以使接合墊122電性連接於後續製程中所形成的構件。互聯結構124經嵌入於介電層116中，且電性連接於至少一部分的接合墊120與至少一部分的接合墊122之間。可藉由鍍著製程（plating process）形成導電單元118，且導電單元118可包括銅、鋁、金、銀、焊料或其組合。
請參照圖1E，藉由分離製程（debonding process）將載體108自晶粒106與第一封裝層112分離。詳而言之，可對附著層110施加熱能或光能（例如是熱或紫外光照射）。一旦受到熱能或光能的影響，附著層110失去附著性且可輕易地自載體108、晶粒106以及第一封裝層112被剝離。
請參照圖1F，於接合墊122上設置多個第二導電端子126，且使多個第二導電端子126電性連接至接合墊122。第二導電端子122可包括導電柱、導電凸塊或其組合。舉例而言，如圖1F所示，第二導電端子126中的每一者包括導電柱128以及設置於導電柱128上的導電凸塊130。
請參照圖1G，進行單體化製程（singulation process）。相鄰的晶粒106之間的第一封裝層112經切開以形成多個封裝結構100。舉例而言，單體化製程包括以旋切刀（rotating blade）或雷射光束切割。
基於將晶粒106嵌入於第一封裝層112中且將重佈線層114設置於第一封裝層112上，兩相鄰的第一導電端子102之間的第一間距P1小於兩相鄰的第二導電端子126之間的第二間距P2。換言之，每一封裝結構100形成扇出封裝結構（fan-out package structure）。在扇出封裝結構中，第一封裝層112在晶粒106的周圍提供額外的空間，以使得第一導電端子102可經由重佈線層114而被連接至此額外的空間。因此，可在封裝結構100中達到更高的輸入/輸出連接數目（I/O connection number）。此外，可改善封裝結構100的電性表現以及散熱表現。
圖2A至圖2F是依照本發明一實施例繪示的半導體封裝結構200的製造方法的剖視示意圖。
請參照圖2A，在載體202上形成重佈線結構204。載體202可由玻璃、塑料或其他適合的材料構成。在一些實施例中，可預先在載體202上沉積附著層203，以暫時地提高重佈線結構204與載體202之間的附著性。附著層203可為光熱轉換附著層或其他適合的附著層。重佈線結構204可包括至少一介電層206以及嵌入於介電層206中的多個導電單元208。導電單元208包括多個第一接合墊210、多個第二接合墊212以及多個互聯結構214。第一接合墊210經設置於重佈線結構204的相對於載體202的第一表面S1。最上層的介電層206暴露出第一接合墊210。第二接合墊212設置於重佈線結構204的面對載體202的第二表面S2。最底層的介電層206暴露出第二接合墊212。互聯結構214經嵌入於介電層206中且電性連接於至少一部分的第一接合墊210與至少一部分的第二接合墊212之間。
請參照圖2B，藉由覆晶接合（flip-chip bonding）將圖1G所示的封裝結構100耦合至或置於重佈線結構204的第一表面S1上。封裝結構100的第二導電端子126電性連接至重佈線結構204的第一接合墊210。換言之，第二導電端子126電性連接於重佈線層114與重佈線結構204之間。値得注意的是，在圖2B中有六個封裝結構100被形成於載體202上。然而，本發明並不以此為限。在其他實施例中，可將單一封裝結構100或多於/少於六個的封裝結構100形成於載體202上。
請參照圖2C，在重佈線結構204的第一表面S1上形成第二封裝層216，以包覆封裝結構100。在一些實施例中，第二封裝層216可包括由封膠製程形成的封膠材料。在其他實施例中，第二封裝層216可由絕緣材料所形成，絕緣材料例如是環氧樹脂或其他適合的樹脂。此外，在其他實施例中，第二封裝層216可自頂表面被薄化以減低半導體封裝結構200的整體厚度。舉例而言，可藉由機械研磨、化學機械研磨、蝕刻或其他適合的方法以達成薄化製程。在其他實施例中，由於每一晶粒106的主動面朝向下方，因此亦可將晶粒106薄化至所需的厚度而不影響其電性。在本實施例中，將重佈線結構204與封裝結構100耦合的步驟在以第二封裝層216包覆封裝結構100的步驟之前。
請參照圖2D，將載體202與附著層203自重佈線結構204移除或分離。舉例而言，可對附著層203施加熱能或光能（例如是熱或紫外光照射）。一旦受到熱能或光能的影響，附著層203失去附著性且可輕易地自載體202與重佈線結構204被剝離。
請參照圖2E，於重佈線結構204的第二表面S2上形成多個焊球218。焊球218電性連接至重佈線結構204的第二接合墊212。舉例而言，可藉由植球製程（ball placement process）以形成焊球218。
請參照圖2F，進行單體化製程。相鄰的封裝結構100之間的第二封裝層216經切開以形成多個半導體封裝結構200。舉例而言，單體化製程包括以旋切刀或雷射光束切割。
請同時參照圖1G與圖2F，基於將封裝結構100嵌入於第二封裝層216中，且將重佈線結構204設置於第二封裝層216上，第二間距P2小於兩相鄰的焊球218之間的第三間距P3。換言之，每一半導體封裝結構200形成具有另一封裝結構（封裝結構100）嵌入於其中的一封裝結構。半導體封裝結構200的第二封裝層216更在每一封裝結構100的周圍提供額外的空間以作為佈線（trace routing）用。因此，可達成更高的輸入/輸出連接數目。此外，重佈線結構204可取代習知的矽穿孔（through silicon via，TSV）中介層，以降低製造成本。再者，在封裝結構100中，重佈線層114經形成於晶粒106上。另一方面，重佈線結構204經形成於載體202上。換言之，重佈線層114與重佈線結構204分別在不同的扇出製程中被形成。因此，可降低封裝結構100的翹曲程度（warpage level）。如此一來，半導體封裝結構200的翹曲程度可小於兩個重佈線結構均直接形成於晶粒/封裝結構（非分別形成）的半導體封裝結構的翹曲程度。據此，半導體封裝結構200可包含具有較複雜設計的重佈線結構204。
半導體封裝結構200可相容於具有高階元件的應用以及前端技術節點。上述高階元件的應用與前端技術節點具有更高的輸入/輸出連接數，且每一晶粒具有更窄的接墊間距。
圖3A至圖3D是依照本發明一些實施例繪示的半導體封裝結構300a、半導體封裝結構300b、半導體封裝結構300c以及半導體封裝結構300d的剖視示意圖。
請參照圖3A，半導體封裝結構300a相似於圖2F所示的半導體封裝結構200，故在此省略詳細的說明。半導體封裝結構300a與半導體封裝結構200的差異在於半導體封裝結構300a更包括封裝結構100a。封裝結構100a相似於圖1G所示的封裝結構100，惟封裝結構100a包括兩個晶粒106。換言之，可將多個晶粒整合於封裝結構100a中。
請參照圖3B，半導體封裝結構300b相似於圖2F所示的半導體封裝結構200，故在此省略詳細的說明。半導體封裝結構300b與半導體封裝結構200的差異在於半導體封裝結構300b更包括至少一附加封裝結構302。舉例而言，附加封裝結構302為晶圓級晶片尺寸封裝（wafer level chip scale package，WLCSP）。換言之，附加封裝結構302為扇入封裝結構。相較於繪示於圖1G的封裝結構100（扇出封裝結構），附加封裝結構302中的晶粒106並未被封裝層包覆。相似於封裝結構100，附加封裝結構302亦藉由覆晶接合而被耦合至重佈線結構204的第一表面S1。隨後，進行如圖2C至圖2F所繪示的步驟以得到半導體封裝結構300b。如此一來，可輕易地整合不同類型的封裝結構，以符合多晶片封裝（multi-chip package，MCP）或系統封裝（system in package，SIP）的應用。
請參照圖3C，半導體封裝結構300c相似於圖2F所示的半導體封裝結構200，故在此省略詳細的說明。半導體封裝結構300c與半導體封裝結構200的差異在於半導體封裝結構300c更包括至少一被動元件304。舉例而言，被動元件304為電阻、電容、電感、二極體或天線。相似於封裝結構100，被動元件304亦被置於重佈線結構204的第一表面S1上。隨後，可進行圖2C至圖2F所示的步驟以得到半導體封裝結構300c。如此一來，可輕易地整合封裝結構與被動元件。
請參照圖3D，半導體封裝結構300d相似於圖3B所示的半導體封裝結構300b，故在此省略詳細的說明。半導體封裝結構300d與半導體封裝結構300b的差異在於半導體封裝結構300d的附加封裝結構302a藉由打線接合（wire bonding）而被耦合至重佈線結構204的第一表面S1。因此，在形成附加封裝結構302a的期間，可省略圖1A至圖1G所示的有關於第一封裝層112、重佈線層114以及第二導電端子126的步驟。依據半導體封裝結構300d的配置，可輕易地整合不同類型的封裝結構。
圖4A至圖4D是依照本發明另一實施例繪示的半導體封裝結構400的製造方法的剖視示意圖。
請參照圖4A，提供重佈線結構402。在一些實施例中，重佈線結構402可包括印刷電路板（printed circuit board，PCB）或有機封裝基板。舉例而言，有機封裝基板可包括用以組裝的習知有機基板，其例如是核心有機封裝基板（舉例而言，雙馬來醯亞胺-三氮雜苯樹脂（Bismaleimide triazine resin）基板）或無核心有機封裝基板。舉例而言，可藉由委外封測（outsourced semiconductor assembly and test，OSAT）與用於扇出封裝的機台/製程形成重佈線結構402。在其他實施例中，重佈線結構402可為基板供應商所提供的有機基板。重佈線結構402包括多個導電單元404以及聚合物基板406。由於聚合物為介電材料，聚合物基板406可作為介電層。導電單元404嵌入於聚合物基板406中。導電單元404包括多個第一接合墊408、多個第二接合墊410以及多個互聯結構（未繪示）。第一接合墊408設置於重佈線結構402的第一表面S1，且被聚合物基板406暴露出。第二接合墊410設置於重佈線結構402的相對於第一表面S1的第二表面S2，且被聚合物基板406暴露出。互聯結構（未繪示）嵌入於聚合物基板406中，且電性連接於至少一部分的第一接合墊408與至少一部分的第二接合墊410之間。
之後，藉由覆晶接合而將圖1G所示的封裝結構100耦合於或置於重佈線結構402的第一表面S1上。封裝結構100的第二導電端子126電性連接至重佈線結構402的第一接合墊408。換言之，第二導電端子126電性連接於重佈線層114與重佈線結構402之間。
請參照圖4B至圖4D，圖4B至圖4D所示的步驟相似於圖2C以及圖2E至圖2F所示的步驟，故在此省略詳細的說明。於重佈線結構402的第一表面S1上形成第二封裝層412，以包覆封裝結構100。在本實施例中，將重佈線結構402與封裝結構100耦合的步驟在以第二封裝層412包覆封裝結構100的步驟之前。於重佈線結構402的第二表面S2上形成多個焊球414，以與重佈線結構402的第二接合墊410電性連接。相鄰的封裝結構100之間的第二封裝層412經切開以形成多個半導體封裝結構400。
在本實施例中，扇出封裝結構（封裝結構100）耦合至用以組裝的習知有機基板（重佈線結構402），以形成半導體封裝結構400。因此，每一半導體封裝結構400可視為包含扇出結構的類晶片尺寸覆晶封裝（flip chip chip scale package，FCCSP）或類覆晶球格陣列（flip chip ball grid array，FCBGA）的封裝結構。由於封裝結構100耦合至用以組裝的習知有機基板，扇出技術被應用於將具有較精細的積體電路接墊間距（例如是晶粒106的接墊及走線的精細間距）的封裝結構100電性連接至具有較大的焊球間距的有機基板（例如是重佈線結構402）。因此，可降低每一封裝結構100中的晶粒106的積體電路接墊間距（精細間距），且仍可相容於習知可用的有機基板（例如是重佈線結構402）。此外，重佈線層114形成於封裝基板100中，而重佈線結構402為另一預先製造的結構。換言之，重佈線層114與重佈線結構402在不同的扇出製程中形成。因此，可降低半導體封裝結構400的翹曲程度。如此一來，半導體封裝結構400可包含具有較複雜設計的重佈線結構402。
圖5A至圖5C是依照本發明一些實施例繪示的半導體封裝結構500a、半導體封裝結構500b以及半導體封裝結構500c的剖視示意圖。
請參照圖5A，半導體封裝結構500a相似於圖4D所示的半導體封裝結構400，故在此省略詳細的說明。半導體封裝結構500a與半導體封裝結構400的差異在於半導體封裝結構500a更包括至少一附加封裝結構302。本實施例的附加封裝結構302相似於圖3B的相關說明所討論的附加封裝結構302，故在此省略詳細的說明。相似於封裝結構100，附加封裝結構302亦藉由覆晶結合而耦合至重佈線結構402的第一表面S1。隨後，可進行圖4B至圖4D的步驟以得到半導體封裝結構500a。如此一來，可輕易地整合不同類型的封裝結構。
請參照圖5B，半導體封裝結構500b相似於圖4D所示的半導體封裝結構400，故在此省略詳細的說明。半導體封裝結構500b與半導體封裝結構400的差異在於半導體封裝結構500b更包括至少一被動元件304。本實施例的被動元件304相似於圖3C的相關說明所討論的被動元件304，故在此省略詳細的說明。相似於封裝結構100，被動元件304置於或設置於重佈線結構402的第一表面S1上。隨後，進行圖4B至圖4D所示的步驟以得到半導體封裝結構500b。如此一來，可輕易地整合封裝結構與被動元件。
請參照圖5C，半導體封裝結構500c相似於圖5A所示的半導體封裝結構500a，故在此省略詳細的說明。半導體封裝結構500c對於半導體封裝結構500a的差異在於附加封裝結構302a藉由打線接合而耦合至重佈線結構402的第一表面S1。因此，省略圖1A至圖1G所示的關於第一封裝層112、重佈線層114以及第二導電端子126的步驟。基於半導體封裝結構500c的配置，可輕易地整合不同類型的封裝結構。
圖6A至圖6F是依照本發明又一實施例繪示的半導體封裝結構600的製造方法的剖視示意圖。
請參照圖6A，圖1G所示的封裝結構100置於載體602上，以使得晶粒106的主動面朝向上方。在一些實施例中，附著層604可設置於載體602與封裝結構100之間以暫時地提高封裝結構100與載體602之間的附著性。如圖6A所示，第二導電端子126可為導電柱的形式。
請參照圖6B，於載體602上形成第二封裝層606，以包覆封裝結構100。在一些實施例中，第二封裝層606可包括經由封膠製程形成的封膠材料。在其他實施例中，第二封裝層606可由例如是環氧樹脂或其他適合的樹脂的絕緣材料形成。
請參照圖6C，移除一部分的第二封裝層606。詳而言之，薄化第二封裝層606直到暴露出封裝結構100的第二導電端子126的頂面。在一些實施例中，在薄化第二封裝層606以暴露出第二導電端子126的頂面之後，更可對第二導電端子126進行蝕刻製程。舉例而言，可部分地移除第二導電端子126以使第二導電端子126的頂面稍微低於第二封裝層606的頂面。在一些實施例中，第二導電端子126的頂面低於第二封裝層606的頂面1 μm至3 μm。如此一來，可提高第二封裝層606與第二導電端子126的表面粗糙度，以提高其對於後續形成在上方的膜層的附著性。舉例而言，可經由機械研磨、化學機械研磨、蝕刻或其他適合的方法達成薄化製程。對於第二導電端子126的蝕刻製程可包括非等向性蝕刻或等向性蝕刻。
請參照圖6D，於封裝結構100與第二封裝層606上設置重佈線結構608。重佈線結構608包括至少一介電層610與嵌入於介電層610的多個導電單元612。導電單元612包括多個第一接合墊614、多個第二接合墊616以及多個互聯結構618。第一接合墊614設置於重佈線結構608的面對封裝結構100的第一表面S1。最下方的介電層610暴露出第一接合墊614，使得第一接合墊614電性連接至第二導電端子126。換言之，重佈線結構608的性連接至封裝結構100的第二導電端子126。第二接合墊616設置於重佈線結構608的相對於第一表面S1的第二表面S2。最上方的介電層610暴露出第二接合墊616以使其與在後續製程中形成的構件電性連接。互聯結構618電性連接於至少一部分的第一接合墊614與至少一部分的第二接合墊616之間。由於重佈線結構608形成於封裝結構100與第二封裝層606兩者上，而非整個形成於封裝結構100上。因此，可降低封裝結構100的翹曲程度。在本實施例中，包覆封裝結構100的步驟在將重佈線結構608與封裝結構100耦合的步驟之前。
請參照圖6E，於重佈線結構608的第二表面S2上形成多個焊球620。焊球620電性連接至重佈線結構608的第二接合墊616。舉例而言，可藉由植球製程形成焊球620。
請參照圖6F，將載體602與附著層604自封裝結構100與第二封裝層606移除或分離。舉例而言，可對附著層604施加熱能或光能（例如是熱或紫外光照射）。一旦受到熱能或光能的影響，附著層604失去附著性且可輕易地自載體602、封裝結構100以及第二封裝層606被剝離。値得注意的是，如圖6E與圖6F繪示的內容，焊球620是在分離製程之前形成。然而，本發明並不以此為限。在其他實施例中，可在形成焊球620於重佈線結構608的第二表面S2上之前進行分離製程。切開相鄰的封裝結構100之間的第二封裝層606，以形成多個半導體封裝結構600。舉例而言，單體化製程包括以旋切刀或雷射光束切割。
每一半導體封裝結構600形成具有另一封裝結構（封裝結構100）嵌入於其中的一封裝結構。半導體封裝結構600的第二封裝層606更在每一封裝結構100的周圍提供額外的空間以作為佈線用。因此，可達成更高的輸入/輸出連接數。此外，重佈線結構608可取代習知的矽穿孔中介層，以降低製造成本。再者，由於重佈線結構608形成於封裝結構100與第二封裝層606兩者上，而非整個形成於封裝結構100上。因此，可降低封裝結構100的翹曲程度。據此，半導體封裝結構600可包含具有較複雜設計的重佈線結構608。
圖7A至圖7C是依照本發明一些實施例繪示的半導體封裝結構700a、半導體封裝結構700b以及半導體封裝結構700c的剖視示意圖。
請參照圖7A，半導體封裝結構700a相似於圖6F所示的半導體封裝結構600，故在此省略詳細的說明。半導體封裝結構700a對於半導體封裝結構600的差異在於半導體封裝結構700a包括封裝結構100a。本實施例的封裝結構100a相似於圖3A的相關說明所討論的封裝結構100a，故在此省略詳細的說明。在本實施例中，可將多個晶粒整合在封裝結構100a中。
請參照圖7B，半導體封裝結構700b相似於圖6F所示的半導體封裝結構600，故在此省略詳細的說明。半導體封裝結構700b對於半導體封裝結構600的差異在於半導體封裝結構700b更包括至少一附加封裝結構302。本實施例的附加封裝結構302相似於圖3B的相關說明所討論的附加封裝結構302，故在此省略詳細的說明。相似於封裝結構100，附加封裝結構302置於載體602上。隨後，可進行圖6B至圖6F所示的步驟以得到半導體封裝結構700b。如此一來，可輕易地整合不同類型的封裝結構，以符合多晶片封裝或系統封裝的應用。
請參照圖7C，半導體封裝結構700c相似於圖7B所示的半導體封裝結構700b，故在此省略詳細的說明。半導體封裝結構700c對於半導體封裝結構700b的差異在於半導體封裝結構700c更包括設置於重佈線結構608的第二表面S2上的至少一被動元件702。本實施例的被動元件702相似於圖3C所示的被動元件304。被動元件702電性連接至重佈線結構608的第二接合墊616。如此一來，可輕易地整合封裝結構與被動元件。
綜上所述，封裝結構的第一封裝層在每一晶粒的周圍提供額外的空間，以使得在晶粒上的第一導電端子可經由重佈線層而被連接至此額外的空間。基於封裝結構的扇出配置，此封裝結構可相容於更高的輸入/輸出連接數目。此外，可改善封裝結構的電性表現以及散熱表現。相似地，由於將封裝結構嵌入於第二封裝層且將重佈線結構與封裝結構的第二導電端子耦合，半導體封裝結構形成另一扇出封裝結構。因此，可達到更高的輸入/輸出連接數目。此外，重佈線結構可取代習知的矽穿孔中介層，以降低製造成本。再者，重佈線層與重佈線結構分別在不同的扇出製程中被形成。因此，可降低封裝結構的翹曲程度。據此，半導體封裝結構可包含具有較複雜設計的重佈線結構。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、100a‧‧‧封裝結構
102‧‧‧第一導電端子
102’‧‧‧墊
104‧‧‧鈍化圖案
106‧‧‧晶粒
108、202、602‧‧‧載體
110、203、604‧‧‧附著層
112‧‧‧第一封裝層
114‧‧‧重佈線層
116‧‧‧第一介電層
118‧‧‧導電單元
120、122‧‧‧接合墊
124、214、618‧‧‧互聯結構
126‧‧‧第二導電端子
128‧‧‧導電柱
130‧‧‧導電凸塊
200、300a、300b、300c、300d、400、500a、500b、500c、600、700a、700b、700c‧‧‧半導體封裝結構
204、402、608‧‧‧重佈線結構
206、610‧‧‧介電層
208、404、612‧‧‧導電單元
210、408、614‧‧‧第一接合墊
212、410、616‧‧‧第二接合墊
216、412、606‧‧‧第二封裝層
218、414、620‧‧‧焊球
302、302a‧‧‧附加封裝結構
304、702‧‧‧被動元件
406‧‧‧聚合物基板
P1‧‧‧第一間距
P2‧‧‧第二間距
P3‧‧‧第三間距
S1‧‧‧第一表面
S2‧‧‧第二表面
圖1A至圖1G是依照本發明一實施例繪示的封裝結構的製造方法的剖視示意圖。 圖2A至圖2F是依照本發明一實施例繪示的半導體封裝結構的製造方法的剖視示意圖。 圖3A至圖3D是依照本發明一些實施例繪示的半導體封裝結構的剖視示意圖。 圖4A至圖4D是依照本發明另一實施例繪示的半導體封裝結構的製造方法的剖視示意圖。 圖5A至圖5C是依照本發明一些實施例繪示的半導體封裝結構的剖視示意圖。 圖6A至圖6F是依照本發明又一實施例繪示的半導體封裝結構的製造方法的剖視示意圖。 圖7A至圖7C是依照本發明一些實施例繪示的半導體封裝結構的剖視示意圖。

Claims (10)

  1. 一種半導體封裝結構，包括：重佈線結構，具有第一表面以及相對於所述第一表面的第二表面；至少一封裝結構，位於所述重佈線結構的所述第一表面上，其中所述至少一封裝結構包括：至少一晶粒，具有位於所述至少一晶粒上的多個第一導電端子；第一封裝層，包覆所述至少一晶粒，其中所述第一封裝層暴露出至少一部分的所述多個第一導電端子；重佈線層，位於所述第一封裝層上，其中所述重佈線層電性連接至被所述第一封裝層暴露出的第一導電端子；以及多個第二導電端子，電性連接於所述重佈線層與所述重佈線結構之間；以及第二封裝層，包覆所述至少一封裝結構，其中所述第二封裝層暴露出至少一部分的所述多個第二導電端子，其中所述第一封裝層實體接觸於所述至少一晶粒的側壁以及所述多個第一導電端子的側壁，其中所述第二封裝層實體接觸於所述第一封裝層的側壁、所述重佈線層的側邊以及所述多個第二導電端子的側邊，且其中所述第一封裝層夾置於所述至少一晶粒與所述第二封裝層之間。
  2. 如申請專利範圍第1項所述的半導體封裝結構，更包括位於所述重佈線結構的所述第二表面上的多個焊球。
  3. 如申請專利範圍第2項所述的半導體封裝結構，其中兩相鄰的第一導電端子之間的第一間距小於兩相鄰的第二導電端子之間的第二間距，且所述第二間距小於兩相鄰的焊球之間的第三間距。
  4. 如申請專利範圍第1項所述的半導體封裝結構，其中所述多個第二導電端子中的每一者包括導電柱、導電凸塊或其組合。
  5. 如申請專利範圍第1項所述的半導體封裝結構，更包括至少一被動元件及/或至少一附加封裝結構，設置於所述重佈線結構的所述第一表面上。
  6. 如申請專利範圍第1項所述的半導體封裝結構，更包括至少一被動元件，設置於所述重佈線結構的所述第二表面上。
  7. 一種半導體封裝結構的製造方法，包括：形成至少一封裝結構，其中所述至少一封裝結構包括至少一晶粒、第一封裝層、重佈線層以及多個第二導電端子，所述至少一晶粒具有位於其上的多個第一導電端子，所述第一封裝層包覆所述至少一晶粒且暴露出至少一部分的所述多個第一導電端子，所述重佈線層位於所述第一封裝層上且電性連接至被所述第一封裝層暴露出的第一導電端子，所述多個第二導電端子位於所述重佈線層上；將所述至少一封裝結構耦合至重佈線結構的第一表面，其中所述至少一封裝結構的所述多個第二導電端子電性連接至所述重佈線結構；以及以第二封裝層包覆所述至少一封裝結構，其中所述第一封裝層實體接觸於所述至少一晶粒的側壁以及所述多個第一導電端子的側壁，其中所述第二封裝層實體接觸於所述第一封裝層的側壁、所述重佈線層的側邊以及所述多個第二導電端子的側邊，且其中所述第一封裝層夾置於所述至少一晶粒與所述第二封裝層之間。
  8. 如申請專利範圍第7項所述的半導體封裝結構的製造方法，更包括在所述重佈線結構的相對於所述第一表面的第二表面上形成多個焊球，其中兩相鄰的第一導電端子之間的第一間距小於兩相鄰的第二導電端子之間的第二間距，且所述第二間距小於兩相鄰的焊球之間的第三間距。
  9. 如申請專利範圍第7項所述的半導體封裝結構的製造方法，更包括在所述重佈線結構的相對於所述第一表面的第二表面上形成至少一被動元件。
  10. 如申請專利範圍第7項所述的半導體封裝結構的製造方法，更包括：將至少一附加封裝結構或至少一被動元件耦合至所述重佈線結構的所述第一表面；以及以所述第二封裝層包覆所述至少一附加封裝結構或所述至少一被動元件。
TW106125194A 2016-09-09 2017-07-27 半導體封裝結構及其製造方法 TWI649845B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662385259P 2016-09-09 2016-09-09
US62/385,259 2016-09-09
US15/599,481 2017-05-19
US15/599,481 US10141276B2 (en) 2016-09-09 2017-05-19 Semiconductor package structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW201826462A TW201826462A (zh) 2018-07-16
TWI649845B true TWI649845B (zh) 2019-02-01

Family

ID=61560424

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106125194A TWI649845B (zh) 2016-09-09 2017-07-27 半導體封裝結構及其製造方法

Country Status (3)

Country Link
US (2) US10141276B2 (zh)
CN (1) CN107808856B (zh)
TW (1) TWI649845B (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201911508A (zh) * 2017-08-02 2019-03-16 矽品精密工業股份有限公司 電子封裝件
US10361158B2 (en) * 2017-08-29 2019-07-23 Micron Technology, Inc. Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch
US10665522B2 (en) 2017-12-22 2020-05-26 Intel IP Corporation Package including an integrated routing layer and a molded routing layer
US10699980B2 (en) 2018-03-28 2020-06-30 Intel IP Corporation Fan out package with integrated peripheral devices and methods
US10916492B2 (en) * 2018-05-11 2021-02-09 Advanced Semiconductor Engineering, Inc. Semiconductor substrate and method of manufacturing the same
KR102570270B1 (ko) * 2018-10-30 2023-08-24 삼성전자주식회사 반도체 패키지
US11133282B2 (en) 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
CN211150513U (zh) * 2019-08-30 2020-07-31 无锡天芯互联科技有限公司 封装体
TWI734455B (zh) 2019-10-09 2021-07-21 財團法人工業技術研究院 多晶片封裝件及其製造方法
TWI785371B (zh) * 2020-08-25 2022-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
WO2022041159A1 (zh) * 2020-08-28 2022-03-03 华为技术有限公司 一种芯片封装结构、电子设备及芯片封装结构的制备方法
TWI800977B (zh) * 2020-11-11 2023-05-01 南韓商Ｎｅｐｅｓ股份有限公司 半導體封裝以及其製造方法
TWI751052B (zh) * 2021-03-16 2021-12-21 力成科技股份有限公司 半導體封裝結構及其製法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201519404A (zh) * 2013-11-14 2015-05-16 Taiwan Semiconductor Mfg Co Ltd 三維積體電路結構及其製造方法
TW201608653A (zh) * 2013-12-30 2016-03-01 台灣積體電路製造股份有限公司 製造半導體封裝體的方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3798597B2 (ja) * 1999-11-30 2006-07-19 富士通株式会社 半導体装置
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US8421244B2 (en) * 2007-05-08 2013-04-16 Samsung Electronics Co., Ltd. Semiconductor package and method of forming the same
KR101486420B1 (ko) * 2008-07-25 2015-01-26 삼성전자주식회사 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법
US9082806B2 (en) * 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US9064936B2 (en) * 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US9087832B2 (en) 2013-03-08 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage reduction and adhesion improvement of semiconductor die package
US10418298B2 (en) * 2013-09-24 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual fan-out semiconductor package
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
JP2015135869A (ja) * 2014-01-16 2015-07-27 株式会社テラプローブ 半導体装置、及び半導体装置の製造方法
KR20150104467A (ko) * 2014-03-05 2015-09-15 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9373604B2 (en) 2014-08-20 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same
TWI548043B (zh) * 2014-11-17 2016-09-01 矽品精密工業股份有限公司 封裝結構及其製法
US10068853B2 (en) * 2016-05-05 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201519404A (zh) * 2013-11-14 2015-05-16 Taiwan Semiconductor Mfg Co Ltd 三維積體電路結構及其製造方法
TW201608653A (zh) * 2013-12-30 2016-03-01 台灣積體電路製造股份有限公司 製造半導體封裝體的方法

Also Published As

Publication number Publication date
TW201826462A (zh) 2018-07-16
CN107808856B (zh) 2019-12-10
US10141276B2 (en) 2018-11-27
US20190051625A1 (en) 2019-02-14
US20180076157A1 (en) 2018-03-15
CN107808856A (zh) 2018-03-16
US10276526B2 (en) 2019-04-30

Similar Documents

Publication Publication Date Title
TWI649845B (zh) 半導體封裝結構及其製造方法
US11189603B2 (en) Semiconductor packages and methods of forming same
US11018088B2 (en) Dummy features in redistribution layers (RDLS) and methods of forming same
TWI683378B (zh) 半導體封裝及其製造方法
KR102193505B1 (ko) 반도체 패키지 및 그 형성 방법
TWI713129B (zh) 半導體元件及其形成方法
US11177201B2 (en) Semiconductor packages including routing dies and methods of forming same
CN108122861B (zh) 具有虚设管芯的封装结构、半导体装置及其形成方法
TWI610412B (zh) 封裝結構及其形成方法
KR102069256B1 (ko) 패키지 구조물 및 그 형성 방법
TWI714913B (zh) 封裝結構及其製造方法
TWI717813B (zh) 半導體封裝及其製造方法
TWI697085B (zh) 半導體元件及其形成方法
TW202002190A (zh) 半導體裝置封裝體及其製造方法
TW201824486A (zh) 封裝結構
TWI754839B (zh) 封裝結構及其形成方法
KR20190055692A (ko) 반도체 패키지들 내의 금속화 패턴들 및 그 형성 방법들
US20180301418A1 (en) Package structure and manufacturing method thereof
TW201806101A (zh) 封裝結構及其製造方法
TW202008481A (zh) 形成半導體封裝體的方法
TW202134713A (zh) 積體電路封裝及其形成方法
TW202143406A (zh) 半導體封裝體及其製造方法
CN109786274B (zh) 半导体器件及其制造方法
JP2022023830A (ja) 半導体パッケージにおける放熱及びその形成方法
KR102379087B1 (ko) 반도체 디바이스 및 제조 방법