TWI644520B - Merge and split sar analog-digital converter with tri-level switch - Google Patents

Abstract

A split-combined gradual approximation analog-to-digital converter with a three-stage switch includes a split merge capacitor array, a plurality of three-stage switch, a comparator and a SAR logic circuit, the split merge capacitor array has a plurality of positive terminal capacitors and a plurality of negative terminal capacitors, each of the positive terminal capacitors being electrically connected to a positive terminal potential line and each of the three stages of switching switches, wherein each of the negative terminal capacitors is electrically connected to a negative terminal potential line and each The three-stage switching switch, wherein each of the three-stage switching switches selectively couples the positive terminal capacitance to the negative terminal capacitance or the positive terminal capacitance to a reference voltage, a ground terminal or a half reference voltage, Or coupling the negative terminal capacitor to the reference voltage, the ground terminal or the half reference voltage.

Description

Split-combined gradual approximation analog-to-digital converter with three-stage switch

The present invention relates to a gradual approximation analog-to-digital converter, and more particularly to a split-combined gradual approximation analog-to-digital converter with a three-stage switch.

Please refer to FIG. 1 , which is a circuit diagram of a 3-bit gradual approximation analog-to-digital converter 200 having a positive-end capacitor array 210, a plurality of positive-side switching switches 220, and a negative The terminal capacitor array 230, the plurality of negative terminal switching switches 240, a comparator 250 and a SAR logic circuit 260. Each of the positive terminal capacitors 210 is connected to the reference voltage V _ref or the ground terminal Gnd via the positive terminal switch 220, and the other end of each positive terminal capacitor is connected to the positive terminal of the comparator 250. . Each of the negative terminal capacitors 230 is connected to the reference voltage V _ref or the ground terminal Gnd via the negative terminal switch 240, and the other end of each negative terminal capacitor is connected to the negative terminal of the comparator 250. . The comparator 250 is configured to compare the potentials of the positive-end capacitor array 210 and the negative-end electrical array 230, and output a comparison signal to the SAR logic circuit 260, so that the SAR logic circuit 260 outputs a plurality of signals according to the comparison signal. The control signal controls each of the positive terminal changeover switches 220 and each of the negative terminal changeover switches 240.

Referring to FIG. 2, the SAR logic circuit 260 of the 3-bit gradual approximation analog-to-digital converter 200 controls the switching between the positive-side switching switch 220 and the negative-side switching switches 240, and the closest is seen. The positive terminal capacitance and the negative terminal capacitance of the comparator 250 are connected to the reference voltage V _ref in all the alignment bits without switching to the ground terminal Gnd, and the two capacitors are intended to make the gradual approximation The voltage received by the comparator 250 of the analog to digital converter 200 can conform to the binary search method, but this also results in the required layout area for the additional capacitance.

The three-stage switch can connect the positive terminal capacitor and the negative terminal capacitor to the half reference voltage, and the N-bit gradually approximating analog digital converter can be derived according to the binary search method. The N+1 bit gradually approximates the analog-to-digital converter, which greatly reduces the layout area of the capacitor and reduces the overall power consumption.

The split-combined gradual approximation analog-to-digital converter with a three-stage switch includes a split merge capacitor array, a plurality of three-stage switch, a comparator and a SAR logic circuit, and the split merge The capacitor array has a plurality of positive terminal capacitors and a plurality of negative terminal capacitors. One of the first terminals of the positive terminal capacitors is electrically connected to a positive terminal potential line, and the first end of each of the negative terminal capacitors is electrically connected to the first end. a negative terminal potential line, each of the three-stage switching switch electrically connecting one of the second terminal of each of the positive terminal capacitors and one of the second terminals of each of the negative terminal capacitors, wherein each of the three-stage switching switches selectively positively The second end of the terminal capacitor is coupled to the second end of the negative terminal capacitor, or the second end of the positive terminal capacitor is coupled to a reference voltage, a ground terminal or a half reference voltage, or the negative The second end of the terminal capacitor is coupled to the reference voltage, the ground terminal or the half reference voltage, the comparator is electrically connected to the positive terminal potential line and the negative terminal potential line, and the comparator outputs a comparison signal. The SAR logic circuit receives the comparison signal and the SAR Series circuit switch based on the comparison signal to control the plurality of three.

According to the present invention, the capacitors are selectively coupled to each other, connected to the ground terminal, connected to the half reference voltage or connected to the reference voltage by the three-stage switching switches, so that the capacitors are originally N bits. Gradually approximating the analog-to-digital converter derived from the N+1-bit gradual approximation analog-to-digital converter, therefore, the three-stage switch of the present invention is compared with the gradual approximation analog-to-digital converter with the same bit in the prior art. The split-merging approach gradually approximates the analog-to-digital converter to reduce the maximum size of the capacitor bit, which can significantly reduce the overall layout area and power consumption.

Please refer to FIG. 3 , which is a circuit structural diagram of a split-combined gradually approximating analog-to-digital converter 100 with a three-stage switch, which is a split-merging and gradually approximating analog-to-digital converter with a three-stage switch. 100 includes a split merged capacitor array 110, a plurality of first three-stage switch 120s, a plurality of second three-stage switches 130, a comparator 140, and a SAR logic circuit 150. In this embodiment, the split-combined gradual approximation analog-to-digital converter 100 with a three-level switch of 4+1 bits can be constructed with a larger size capacitor and a three-stage switch. The analogous digital converter of the high bit is not limited to this invention.

In this embodiment, the split combined capacitor array 110 has a plurality of first positive terminal capacitors 111, a plurality of second positive terminal capacitors 112, a plurality of first negative terminal capacitors 113, and a plurality of second negative terminal capacitors 114. The first positive terminal capacitors 111 are connected in parallel with the second positive terminal capacitors 112. The first negative terminal capacitors 113 and the second negative terminal capacitors 114 are connected in parallel, wherein the first positive terminal capacitors are connected in parallel. 111 includes three first positive terminal capacitors 111 having unit capacitance values of 2C, 1C, and 1C, and the second positive terminal capacitors 112 include three second positive terminals having unit capacitance values of 2C, 1C, and 1C, respectively. Capacitor 112, the first negative-end capacitors 113 include three first-capacitance capacitors 113 having unit capacitance values of 2C, 1C, and 1C, respectively, and the second negative-end capacitors 114 include three unit capacitance values of 2C. The second negative terminal capacitor 114 of 1C and 1C, in the embodiment, the unit capacitance value C is 1 fF.

The first end 111a of each of the first positive terminal capacitors 111 and the first end 112a of each of the second positive terminal capacitors 112 are electrically connected to a positive terminal potential line PL, and one of the first negative terminal capacitors 113 The first end 113a and the first end 114a of each of the second negative terminal capacitors 114 are electrically connected to a negative end potential line NL, and the second end 111b of each of the first positive terminal capacitors 111 and each of the second positive ends The second end 112b of the first end capacitor 112, the second end 113b of each of the first negative terminal capacitors 113, and the second end 114b of each of the second negative terminal capacitors 114 are electrically connected to the three-stage switch 120. The positive terminal potential line PL and the negative terminal potential line NL are respectively electrically connected to one of the positive input terminal 141 and the negative input terminal 142 of the comparator 140, and the comparator 140 compares the potential of the positive terminal potential line PL. And the potential of the negative terminal potential line NL outputs a comparison signal S _com . The positive terminal potential line PL is coupled to a positive terminal switch PS via a positive terminal switch PS to a positive terminal input voltage V _inp with respect to the other end connected to the comparator 140. The negative terminal potential line NL is connected to the other end of the comparator 140. A negative terminal input voltage V _{inn is} coupled via a negative terminal switch NS, wherein V _inp -V _inn = the sampling voltage.

Referring to FIG. 3 , each of the first three-stage switch 120 has a first coupling switch 121 , a first positive switch 122 , and a first negative switch 123 , wherein each of the first switch The second end 111b of the first positive-end capacitor 111 and the second end 113b of the first negative-end capacitor 113 are coupled to the first positive-side switch 111 and the first negative-side switch 123, respectively. The second end 111b of the first positive-side capacitor 111 can be coupled to the first through the first coupling switch 121, the first positive-side switch 122, and the first negative-side switch 123. The second end 113b of the negative terminal capacitor 113 is connected in series.

In addition, the first positive-side switch 122 of each of the first three-stage switch 120 selectively couples the second end 11b of the first positive-side capacitor 111 to a reference voltage V _ref and a ground terminal Gnd Or a half reference voltage 1/2V _ref , the first negative terminal switch 123 selectively coupling the second terminal 113b of the first negative terminal capacitor 113 to the reference voltage V _ref , the ground terminal Gnd or the half Reference voltage 1/2V _ref .

Referring to FIG. 3 , each of the second three-stage switch 130 has a second coupling switch 131 , a second positive switch 132 , and a second negative switch 133 , wherein each of the second switches The second end switch 112 and the second negative end switch 133 are coupled to the second end 112b of the second positive terminal 112 and the second end 114b of the second negative terminal 114, respectively. The second end 112b of the second positive-side capacitor 112 can be coupled to the second through the second coupling switch 131, the second positive-side switch 132, and the second negative-side switch 133. The second end 114b of the negative terminal capacitor 114 is connected in series.

In addition, the second positive-side switch 132 of each of the second-stage switches 130 selectively couples the second terminal 112b of the second positive-side capacitor 112 to the reference voltage V _ref , the ground terminal Gnd Or the second reference voltage 1/2V _ref , the second negative terminal switch 133 selectively coupling the second terminal 114b of the second negative terminal capacitor 114 to the reference voltage V _ref , the ground terminal Gnd or the Half reference voltage 1/2V _ref .

The SAR logic circuit 150 receives the comparison signal S _com output by the comparator 140. The SAR logic circuit 150 outputs a plurality of first positive terminal control signals S _1p and a plurality of second positive terminal control signals S according to the comparison signal S _{com . 2p} , a plurality of first negative-end control signals S _1n , a plurality of second negative-end control signals S _2n and a plurality of split-merging control signals MS1 - MS6, wherein each of the first positive-end control signals S _{1p is} used to control each The first positive end switch 122, each of the second positive control signals S _{2p is} used to control each of the second positive switch 132, and each of the first negative control numbers S _{1n is} used to control the first negative end. The switch 123 is used by each of the first negative terminal control signals S _{1n for} each of the first negative terminal switching switches 123, and each of the split combining control signals MS1 to MS6 is used to control each of the coupling switches 121.

Please refer to FIG. 4 to FIG. 14 , which are schematic diagrams showing the switching process of the three-stage switching switch 120 of the split-combined gradual approximation analog-to-digital converter 100 with the three-stage switching switch according to the present invention. The split-merging combination with the three-stage switch is gradually approaching a sampling step of the analog-to-digital converter 100. At this time, the positive-side switch PS and the negative-side switch NS are closed to allow the positive terminal potential line PL and the negative terminal potential The line NL receives the positive terminal input voltage V _inp and the negative terminal input voltage V _{inn respectively} , and the second terminal 111b of the first positive terminal capacitor 111 and the second terminal 114b of the second negative terminal capacitors 114 receive The reference voltage V _ref , the second end 112 _b of the second positive terminal capacitor 112 and the second end 113 b of the first negative terminal capacitor 113 are connected to the ground terminal Gnd to cause the capacitors to accumulate charges. At this time, the potential of the positive terminal potential line PL is the positive terminal input voltage V _inp , and the potential of the negative terminal potential line NL is the negative terminal input voltage V _inn .

Referring to FIG. 5, the positive terminal switch PS and the negative terminal switch NS are turned off, and the comparator 140 compares the potential of the positive terminal potential line PL and the potential of the negative terminal potential line NL by a first bit. The potential of the positive terminal potential line PL is greater than the potential of the negative terminal potential line NL to output 1 and vice versa. Next, referring to FIG. 6, when the potential of the positive terminal potential line PL is greater than the potential of the negative terminal potential line NL, the first positive terminal capacitor 111 and each of the first negative terminal capacitors 113 are switched to be mutually coupled. The second positive terminal capacitor 112 and the second negative terminal capacitors 114 are respectively coupled to the ground terminal Gnd and the reference voltage V _ref , and the charges of the capacitors are redistributed according to the law of conservation of charge. The potential of the positive terminal potential line PL is changed to V _inp -V _ref /4, and the potential of the negative terminal potential line NL is changed to V _inn +V _ref /4, and therefore, the ratio of the comparator 140 to the second bit The pair can judge V _inp -V _inn >V _ref /2 or V _inp -V _inn <V _ref /2, and conforms to the binary search method. In contrast, referring to FIG. 7 , if the potential of the positive terminal potential line PL is less than the potential of the negative terminal potential line NL, the second positive terminal capacitor 112 and the second negative terminal capacitor 114 are switched to be mutually coupled. The first positive terminal capacitor 111 and the first negative terminal capacitors 113 are respectively coupled to the reference voltage V _ref and the ground terminal Gnd, and the charges of the capacitors are redistributed according to the conservation of the charge. In the law, the potential of the positive terminal potential line PL is changed to V _inp +V _ref /4, and the potential of the negative terminal potential line NL is changed to V _inn -V _ref /4, and therefore, the comparator 140 is in the second bit The comparison can judge V _inp -V _inn >-V _ref /2 or V _inp -V _inn <-V _ref /2, and conform to the binary search method.

Referring to FIG. 8, when the first bit alignment is 1 and the second bit alignment result is V _inp -V _inn >V _ref /2, the first positive terminal capacitor 111 having a size of 2C is switched to The grounding terminal Gnd is coupled to the first negative terminal capacitor 113 of the size 2C to be coupled to the reference voltage V _ref , and the remaining first positive terminal capacitor 111 , the second positive terminal capacitor 112 , the first A negative terminal capacitor 113 and the second negative terminal capacitor 114 are maintained without switching. At this time, the charges of the capacitors are redistributed, and the potential of the positive terminal potential line PL is changed to V _inp -3V _ref /8 according to the law of conservation of charge. The potential of the negative terminal potential line NL is changed to V _inn +3V _ref /8. Therefore, the comparison of the comparator 140 to the third bit can determine V _inp -V _inn >3V _ref /4 or V _inp -V _Inn <3V _ref /4, and can exactly match the binary search method. In contrast, referring to Figure 9, when the first bit is aligned to 1 and the second bit is compared to V _inp -V _inn <V _ref /2, the second positive terminal of size 2C is used. 112 is switched to the second negative terminal capacitor 114 having a size of 2C, and the remaining first positive terminal capacitor 111, the second positive terminal capacitor 112, the first negative terminal capacitor 113, and the second negative terminal capacitor 114 Then, the switch does not switch. At this time, the charge of the capacitors is redistributed. According to the law of conservation of charge, the potential of the positive terminal potential line PL changes to V _inp -V _ref /8, and the potential of the negative terminal potential line NL changes to V _inn. +V _ref /8, therefore, the comparison of the comparator 140 at the third bit can determine V _inp -V _inn >1V _ref /4 or V _inp -V _inn <1V _ref /4, and conform to the binary search method.

Referring to FIG. 10, when the first bit is aligned, the second bit is aligned, and the third bit is V _inp -V _inn >3V _ref /4, the size is 1C. The capacitor of the first positive terminal capacitor 111 is switched to the ground terminal Gnd, and the first negative terminal capacitor 113 of the size 1C is switched to be coupled to the reference voltage V _ref , and the remaining first positive terminal The capacitor 111, the second positive terminal capacitor 112, the first negative terminal capacitor 113 and the second negative terminal capacitor 114 are maintained without switching. At this time, the charges of the capacitors are redistributed, and the positive terminal potential is according to the law of conservation of charge. The potential of the line PL is changed to V _inp -7V _ref /16, and the potential of the negative terminal potential line NL is changed to V _inn +7V _ref /16, so that the comparison of the comparator 140 at the 4th bit can determine V _inp -V _inn >7V _ref /8 or V _inp -V _inn <7V _ref /8, and can surely conform to the binary search method. In contrast, referring to Fig. 11, when the first bit is aligned, the second bit is aligned, and the third bit is V _inp -V _inn <3V _ref /4, the size is The second positive terminal capacitor 111 of the 1C is switched to the second negative terminal capacitor 114 of the size 1C, and the remaining first positive terminal capacitor 111, the second positive terminal capacitor 112, and the first negative terminal capacitor 113 are And the second negative terminal capacitor 114 remains unswitched. At this time, the charge of the capacitors is redistributed. According to the law of conservation of charge, the potential of the positive terminal potential line PL changes to V _inp -5V _ref /16, and the negative terminal potential The potential of the line NL is changed to V _inn +5V _ref /16, therefore, the comparison of the comparator 140 at the 4th bit can determine V _inp -V _inn >5V _ref /8 or V _inp -V _inn <5V _ref / 8, and meet the binary search method.

Please refer to Fig. 12, when the 1-bit alignment is 1, the second-order alignment is 1, the third-bit alignment is 1 and the fourth-bit alignment is V _inp -V _inn >7V _ref / At 8 o'clock, the first positive-end capacitor 111 having the remaining size of 1 C is switched to be coupled to the ground terminal Gnd, and the remaining first-side capacitor 113 having a size of 1 C is switched to be coupled to the half-reference voltage 1 /2V _ref , the remaining first positive terminal capacitor 111 , the second positive terminal capacitor 112 , the first negative terminal capacitor 113 and the second negative terminal capacitor 114 remain unswitched, and the charge of the capacitors is re-energized Distribution, according to the law of conservation of charge, the potential of the positive terminal potential line PL is changed to V _inp -15V _ref /32, and the potential of the negative terminal potential line NL is changed to V _inn +15V _ref /32, therefore, the comparator 140 is The comparison of the 5th bit can judge V _inp -V _inn >15V _ref /16 or V _inp -V _inn <15V _ref /16, and can surely conform to the binary search method.

Please refer to Fig. 13, when the 1-bit alignment is 1, the second-order alignment is 1, the third-bit alignment is 0, and the fourth-bit alignment is V _inp -V _inn >5V _ref / 8, a size of the first negative terminal of the capacitor 113 is switched to 1C coupled to the reference voltage half 1 / 2V _ref, allowing the potential of the positive terminal of the voltage line PL is changed to V _inp -11V _ref / 32, the negative The potential of the terminal potential line NL is changed to V _inn +11V _ref /32. Therefore, the comparison of the comparator 140 at the 5th bit can determine V _inp -V _inn >11V _ref /16 or V _inp -V _inn <11V _Ref /16, and can be consistent with the binary search method.

Please refer to Fig. 14, when the 1-bit alignment is 1, the second-bit alignment is 0, the third-bit alignment is 1 and the fourth-bit alignment is V _inp -V _inn >3V _ref / At 8 o'clock, the first negative terminal capacitor 113 of size 1C is switched to be coupled to the half reference voltage 1/2V _ref , so that the potential of the positive terminal potential line PL can be changed to V _inp -7V _ref /32, the negative The potential of the terminal potential line NL is changed to V _inn +7V _ref /32, and therefore, the comparison of the comparator 140 at the 5th bit can determine V _inp -V _inn >7V _ref /16 or V _inp -V _inn <7V _Ref /16, and can be consistent with the binary search method.

According to the present invention, the capacitors are selectively coupled to each other, connected to the ground terminal Gnd, connected to the half reference voltage 1/2V _ref or connected to the reference voltage V _ref by the three-stage switching switches. Let the N-bit gradually approximating the analog-to-digital converter be derived as a gradually approximating analog-to-digital converter of N+1 bits, thus, the present invention is relatively close to the analog-to-digital converter with the same bit in the prior art. The split-merging and gradual approximation of the analog-to-digital converter 100 with the three-stage switch can reduce the maximum size of the capacitor bit, and can greatly reduce the overall layout area and power consumption.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧Split merged gradual approximation analog-to-digital converter with three-stage switch

110‧‧‧ Split merged capacitor array

111‧‧‧First positive terminal capacitor

111a‧‧‧ first end

111b‧‧‧second end

112‧‧‧second positive terminal capacitor

112a‧‧‧ first end

112b‧‧‧ second end

113‧‧‧First negative terminal capacitor

113a‧‧‧ first end

113b‧‧‧ second end

114‧‧‧Second negative terminal capacitor

114a‧‧‧ first end

114b‧‧‧second end

120‧‧‧First three-level switch

121‧‧‧First coupling switch

122‧‧‧First positive end switch

123‧‧‧First negative switch

130‧‧‧Second and third level switch

131‧‧‧Second coupling switch

132‧‧‧Second positive terminal switch

133‧‧‧Second negative switch

140‧‧‧ Comparator

141‧‧‧ positive input

142‧‧‧negative input

150‧‧‧SAR logic circuit

PL‧‧‧ positive terminal potential line

NL‧‧‧negative potential line

Gnd‧‧‧ Grounding

V _ref ‧‧‧reference voltage

1/2V _ref ‧‧‧ half reference voltage

S _com ‧‧‧ comparison signal

PS‧‧‧ positive terminal switch

NS‧‧ negative switch

V _inp ‧‧‧ Positive input voltage

V _inn ‧‧‧n negative input voltage

200‧‧‧Approaching analog-to-digital converters

210‧‧‧ Positive Capacitor Array

220‧‧‧ positive end switch

230‧‧‧Negative Capacitor Array

240‧‧‧Negative switch

250‧‧‧ comparator

Figure 1: A circuit diagram of a conventional analog approximation of an analog-to-digital converter. Figure 2: A schematic diagram of the switching process of the analog digital converter that is gradually approaching. FIG. 3 is a circuit diagram of a split-merging gradually approximating analog-to-digital converter with a three-stage switch according to an embodiment of the invention. 4 to 14 are diagrams showing the switching process of the split-merging type gradually approaching the analog-to-digital converter with the three-stage switching switch according to an embodiment of the present invention.

Claims (7)

A split-combined gradual approximation analog-to-digital converter with a three-stage switch includes: a split-merged capacitor array having a plurality of positive-end capacitors and a plurality of negative-end capacitors, one of the positive-side capacitors One end is electrically connected to a positive end potential line, and the first end of each of the negative terminal capacitors is electrically connected to a negative end potential line; a plurality of three-stage switching switches, each of the three-stage switching switches being electrically connected a second end of the positive terminal capacitor and a second end of each of the negative terminal capacitors, wherein each of the three-stage switching switches selectively couples the second end of the positive terminal capacitor to the negative terminal capacitor The second end, or the second end of the positive terminal capacitor is coupled to a reference voltage, a ground terminal or a half reference voltage, or the second end of the negative terminal capacitor is coupled to the reference voltage, the ground a comparator or a comparator, electrically connecting the positive terminal potential line and the negative terminal potential line, and the comparator outputs a comparison signal; and a SAR logic circuit receiving the comparison signal, and the SAR logic The circuit controls the three-stage cut according to the comparison signal Change the switch. The split-combined gradual approximation analog-to-digital converter with a three-stage switch as described in claim 1, wherein each of the three-stage switch has a coupling switch, and the coupling switch is coupled to the positive terminal capacitor The second end and the second end of the negative terminal capacitor. The split-combined gradual approximation analog-to-digital converter with a three-stage switch as described in claim 2, wherein each of the three-stage switch has a positive switch and a negative switch, the positive terminal The switch is configured to selectively connect the second end of the positive terminal capacitor directly to the reference voltage, the ground terminal, the half reference voltage or the coupling switch, and the negative terminal switch is configured to selectively The second end of the first negative terminal capacitor is directly connected to the reference voltage, the ground terminal, the half reference voltage or the coupling switch. The split-merging type gradual approximation analog-to-digital converter with a three-stage switch as described in claim 1, wherein the positive terminal potential line is coupled to a positive terminal input voltage via a positive terminal switch, the negative terminal potential The line is coupled to a negative input voltage via a negative terminal switch. The split-combined gradual approximation analog-to-digital converter with a three-stage switch as described in claim 4, wherein the comparator has a positive input terminal and a negative input terminal, and the positive input terminal is electrically connected to the positive The terminal potential line is electrically connected to the negative terminal potential line. The split-combined gradual approximation analog-to-digital converter with a three-stage switch as described in claim 3, wherein the SAR logic circuit outputs a plurality of positive-end control signals and a plurality of negative-end control signals according to the comparison signal Each of the positive terminal control signals is used to control each of the positive terminal switching switches, and each of the negative terminal control numbers is used for each of the negative terminal switching switches. The split-combined gradual approximation analog-to-digital converter with a three-stage switch as described in claim 2, wherein the SAR logic circuit outputs a plurality of split merge control signals according to the comparison signal, and the split merges Control signals are used to control each of the coupling switches.