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TWI642915B - Pyrometer system, fully-differential amplification circuit for amplifying an optical signal in a pyrometer, and method of operating a fully-differential dual amplification circuit - Google Patents

Pyrometer system, fully-differential amplification circuit for amplifying an optical signal in a pyrometer, and method of operating a fully-differential dual amplification circuit Download PDF

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TWI642915B
TWI642915B TW104143541A TW104143541A TWI642915B TW I642915 B TWI642915 B TW I642915B TW 104143541 A TW104143541 A TW 104143541A TW 104143541 A TW104143541 A TW 104143541A TW I642915 B TWI642915 B TW I642915B
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differential
voltage
output
primary
bias
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TW201723444A (en
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F 多納德 穆瑞
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美商先驅能源工業公司
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Abstract

此揭露內容係描述用於改良的高溫量測放大之系統、方法及設備。尤其一放大級係被揭示,其係使用具有一對平行配置的跨阻抗放大器之一雙差分跨阻抗放大級,其係致能較快的取樣以及高的信號對雜訊。 This disclosure describes systems, methods and apparatus for improved high temperature measurement amplification. In particular, an amplification stage is disclosed which uses a dual differential transimpedance amplifier stage with a pair of parallel configuration transimpedance amplifiers that enables faster sampling and high signal-to-noise.

Description

高溫計系統、用於在一高溫計中放大一光學信號之全差分放大電路和操作一全差分雙放大電路之方法 Pyrometer system, fully differential amplifying circuit for amplifying an optical signal in a pyrometer, and method for operating a fully differential dual amplifying circuit

本揭露內容係大致有關於光學高溫量測。尤其(但非限制性的),本揭露內容係有關用於光學高溫量測的改良的放大器之系統、方法及設備。 The disclosure is generally related to optical high temperature measurement. In particular, but not limiting, the present disclosure is directed to systems, methods and apparatus for improved amplifiers for optical high temperature metrology.

根據第35號美國法典第119條的優先權的主張 Claims based on the priority of Article 119 of the US Code 35

本專利申請案係主張2014年12月23日申請的名稱為"具有逆向偏壓及盲(blind)偵測支援之全差分前端的使用以達成高速、低雜訊、低偏移、高增益的高溫計介面"的臨時申請案號62096090的優先權,並且該臨時申請案係被讓與給本案的受讓人而且藉此明確地被納入在此作為參考。 This patent application claims the use of a fully differential front end with the name "reverse bias and blind detection support" on December 23, 2014 to achieve high speed, low noise, low offset, high gain. The priority of the present application is hereby incorporated by reference.

在製造環境中,在不接觸下量測一物體的溫度已經被證實是一項複雜且艱鉅的工作。在運動中的物體通常是難以觸碰的(例如,熔融的藍寶石),而且過熱的物體會損壞溫度感測器。所關注的物體亦可能會因為接觸而輕易地受損,因此妨礙其溫度的量測。用於測量高溫的可靠的手段 已經演進幾個世紀,從鐵匠在鍛造鋼時所用的原始的視覺方法,到今日高度精確的工業溫度量測的手段(例如,光學高溫量測)。 In a manufacturing environment, measuring the temperature of an object without contact has proven to be a complex and arduous task. Objects in motion are often difficult to touch (eg, molten sapphire), and overheated objects can damage the temperature sensor. Objects of interest may also be easily damaged by contact, thus impeding the measurement of their temperature. A reliable means of measuring high temperatures It has evolved for centuries, from the original visual methods used by blacksmiths to forging steel to today's highly accurate means of industrial temperature measurement (eg, optical high temperature measurements).

熱物體發光是一項眾所周知的現象。越熱的話,則越亮。事實上,此現象是許多現代技術的更重要的基石中之一。在該些技術中的是輻射測量的溫度量測,或者是以光學高溫量測著稱者。 The glow of hot objects is a well-known phenomenon. The hotter it is, the brighter it is. In fact, this phenomenon is one of the more important cornerstones of many modern technologies. Among these techniques is the temperature measurement of the radiation measurement, or the optical high temperature measurement.

該系統的本質是一所關注的物體或目標係利用某種類型的光學來檢視。該物體係在某種類型的電子偵測器上成像,該電子偵測器已經被精確地校準來產生在輸入(光強度)與輸出(溫度讀數)之間的一已知的關係。該輸出通常是被指定路由到一控制系統中,並且使用作為回授以即時地調整製程。 The essence of the system is that an object or target of interest is viewed using some type of optics. The system is imaged on a type of electronic detector that has been accurately calibrated to produce a known relationship between input (light intensity) and output (temperature reading). This output is typically routed to a control system and used as a feedback to adjust the process on the fly.

光學高溫計通常使用一放大器以增高一代表所量測的目標之偵測到的光學特徵的電壓。這些放大器係對於光學高溫量測帶來各種尚未充分被解決的挑戰。因此,在此項技術中對於一種用於光學高溫計之改良的放大級係有所需求。 Optical pyrometers typically use an amplifier to increase the voltage of a detected optical characteristic representative of the measured target. These amplifiers present a variety of challenges that have not been fully addressed for optical high temperature measurements. Accordingly, there is a need in the art for an improved amplification stage for an optical pyrometer.

本發明的一個特色為一種用於在一高溫計中放大一光學信號之高速、高信號對雜訊、高增益、並且高動態範圍的全差分放大電路,該全差分放大電路係包括:一第一系統輸入(304),其係被配置以用於耦接至一主要光偵測器(302)的一陽極;一第二系統輸入(306),其係被配置以用於耦接至該主要光偵測器(302)的一陰極,其中,當該第一及第二系統輸入(304、306)耦接至該主要光偵測器(302)時,一光電流ip係在該第二及第一系統輸入(306、304)之間通過;一跨阻抗差分放大器級,其係包括:一主要偏 壓電路(308),其係被配置以將該主要光偵測器(302)偏壓在0V到一逆向偏壓之間,並且具有第一及第二輸出(328、330);一第一跨阻抗放大電路(312),其係具有一第一電流輸入(316)以及一第一跨阻抗電壓輸出(314),其中:該第一電流輸入(316)係耦接至該第一系統輸入(304),一第一偏壓電壓輸入(318)係耦接至該主要偏壓電路(308)的該第一輸出(328),以及在該第一電壓跨阻抗輸出(314)處的一第一電壓係與該光電流ip成比例;以及一第二跨阻抗放大電路(320),其係具有一第二電流輸入(324)以及一第二跨阻抗電壓輸出(322),其中:該第二電流輸入(324)係耦接至該第二系統輸入(306),一第二偏壓電壓輸入(326)係耦接至該主要偏壓電路(308)的該第二輸出(330),以及在該第二電壓跨阻抗輸出(322)處的一第二電壓係與在該第二及第一系統輸入(306、304)之間通過的該光電流ip成比例;其中該主要偏壓電路(308)係耦接至該第一及第二跨阻抗放大電路(312、320),以使得一0V到一逆向偏壓存在於橫跨該主要光偵測器(302);以及一主要差分輸出v1係被配置以用於在一處理器中轉換成為一溫度或反射係數值。 A feature of the present invention is a high-speed, high-signal-to-noise, high-gain, and high-dynamic range fully differential amplifying circuit for amplifying an optical signal in a pyrometer, the fully differential amplifying circuit comprising: a system input (304) configured to be coupled to an anode of a primary photodetector (302); a second system input (306) configured to couple to the the main photodetector (302) is a cathode, wherein, when the first and second system input (304, 306) coupled to the main photodetector (302), the current i p an optical system in the Passing between the second and first system inputs (306, 304); a transimpedance differential amplifier stage comprising: a primary bias circuit (308) configured to the primary photodetector ( 302) biasing between 0V and a reverse bias and having first and second outputs (328, 330); a first transimpedance amplifying circuit (312) having a first current input (316) And a first transimpedance voltage output (314), wherein: the first current input (316) is coupled to the first system input (304), a first The voltage input (318) is coupled to the first output (328) of the primary bias circuit (308), and a first voltage system and the light at the first voltage transimpedance output (314) The current i p is proportional; and a second transimpedance amplifier circuit (320) having a second current input (324) and a second transimpedance voltage output (322), wherein: the second current input (324) Is coupled to the second system input (306), a second bias voltage input (326) is coupled to the second output (330) of the primary bias circuit (308), and a second voltage proportional to the system and the photocurrent p i between the first and the second system input (306, 304) at the second voltage through a trans-impedance output (322); wherein the primary bias circuit ( 308) coupled to the first and second transimpedance amplifying circuits (312, 320) such that a 0V to a reverse bias exists across the primary photodetector (302); and a primary differential output The v 1 system is configured for conversion to a temperature or reflection coefficient value in a processor.

本發明的另一個特色為一種高溫計系統,其係包括:一主要光偵測器(201);一雙差分放大電路(202),其係包括一對跨阻抗放大器,該對跨阻抗放大器係耦接至該主要光偵測器(201),並且具有與該主要光偵測器(201)所產生的光電流ip成比例之兩個差分電壓輸出(212、214),但是具有不同的增益;一第一類比至數位轉換器(204),其係耦接至該兩個差分電壓輸出(212)的一第一差分電壓輸出,並且被配置以轉換一第一差分電壓輸出(212)成為一對應的數位值,並且具有提供該對應的數位值至一處理器(210)的一第一數位輸出(216);一第二類比至數位轉換器(206),其係耦接至該兩 個差分電壓輸出(204)的一第二差分電壓輸出,並且被配置以轉換一第二差分電壓輸出(214)成為一對應的數位值,並且具有提供該對應的數位值至該處理器(210)的一第二數位輸出(218);以及該處理器(210),其係耦接至該第一及第二數位輸出(216、218),且具有一選擇器(208),該選擇器(208)係耦接至該第一及第二數位輸出(216、218)並且被配置以選擇該第一及第二數位輸出(216、218)中的哪一個將藉由該處理器加以處理,該處理器(210)係被配置以轉換該第一及第二數位輸出(216、218)的一所選者成為一溫度或是反射係數值,並且具有提供該溫度或是反射係數值的一輸出(220)。 Another feature of the present invention is a pyrometer system comprising: a primary photodetector (201); a dual differential amplifying circuit (202) comprising a pair of transimpedance amplifiers, the pair of transimpedance amplifiers coupled to the main photodetector (201), and having a photocurrent i proportional to the differential voltage of the two p outputs (212, 214) generated by the main photodetector (201), but with different Gain; a first analog to digital converter (204) coupled to a first differential voltage output of the two differential voltage outputs (212) and configured to convert a first differential voltage output (212) Forming a corresponding digital value and having a first digital output (216) providing the corresponding digital value to a processor (210); a second analog to digital converter (206) coupled to the a second differential voltage output of the two differential voltage outputs (204) and configured to convert a second differential voltage output (214) to a corresponding digital value and having the corresponding digital value provided to the processor ( 210) a second digit output (218); and the processor (210) The system is coupled to the first and second digital outputs (216, 218) and has a selector (208) coupled to the first and second digital outputs (216, 218) And configured to select which of the first and second digit outputs (216, 218) will be processed by the processor, the processor (210) configured to convert the first and second digits A selected one of the outputs (216, 218) becomes a temperature or reflection coefficient value and has an output (220) that provides the temperature or reflection coefficient value.

本發明的另一個特色為一種操作一全差分雙放大電路之方法,該方法係包括:接收一光電流ip,該光電流ip通過一主要光偵測器至一差分跨阻抗差分放大器級(350),其係包括並聯配置的一第一對跨阻抗放大電路(312、320);經由該差分跨阻抗差分放大器級(350)以轉換該光電流ip成為一差分輸出電壓v1;提供該第一差分輸出電壓v1至一對並聯配置的差分電壓放大器級(430、432),藉此轉換該第一差分輸出電壓v1成為一對具有不同增益的第二及第三差分輸出電壓v2及v3;經由一對類比至數位轉換器(204、206)以提供該第二及第三對差分輸出電壓v2及v3至一處理器;選擇該第二及第三差分輸出電壓v2及v3中之一,以用於在無機械式開關下進行處理;轉換該第二及第三差分輸出電壓v2及v3中之一所選者成為一溫度或是反射係數值。 Another feature of the present invention is a method of operating a fully differential amplification circuits double, the method comprising the Department of: receiving a photocurrent i p, i p of the photocurrent to a differential transimpedance differential amplifier stage via a main photodetector (350), comprising a first pair of transimpedance amplifying circuits (312, 320) arranged in parallel; via the differential transimpedance differential amplifier stage (350) to convert the photocurrent i p into a differential output voltage v 1 ; Providing the first differential output voltage v 1 to a pair of differential voltage amplifier stages (430, 432) arranged in parallel, thereby converting the first differential output voltage v 1 into a pair of second and third differential outputs having different gains Voltages v 2 and v 3 ; providing the second and third pairs of differential output voltages v 2 and v 3 to a processor via a pair of analog to digital converters (204, 206); selecting the second and third differentials Outputting one of voltages v 2 and v 3 for processing without a mechanical switch; converting one of the second and third differential output voltages v 2 and v 3 to a temperature or reflection Coefficient value.

102‧‧‧光偵測器 102‧‧‧Photodetector

104‧‧‧跨阻抗放大器 104‧‧‧Transimpedance amplifier

106‧‧‧放大級 106‧‧‧Amplification level

107‧‧‧高增益的輸出 107‧‧‧High gain output

108‧‧‧選擇器 108‧‧‧Selector

109‧‧‧低增益的輸出 109‧‧‧Low gain output

110‧‧‧類比至數位轉換器(ADC) 110‧‧‧ analog to digital converter (ADC)

200‧‧‧高溫計系統 200‧‧‧ pyrometer system

201‧‧‧主要光偵測器 201‧‧‧Main light detector

202‧‧‧全差分放大電路(雙差分放大電路) 202‧‧‧ Fully Differential Amplifier Circuit (Double Differential Amplifier Circuit)

204‧‧‧第一ADC 204‧‧‧First ADC

206‧‧‧第二ADC 206‧‧‧Second ADC

208‧‧‧選擇器 208‧‧‧Selector

210‧‧‧處理器 210‧‧‧ processor

212‧‧‧第一差分電壓輸出 212‧‧‧First differential voltage output

214‧‧‧第二差分電壓輸出 214‧‧‧Second differential voltage output

216‧‧‧第一數位輸出 216‧‧‧first digital output

218‧‧‧第二數位輸出 218‧‧‧second digital output

220‧‧‧輸出 220‧‧‧ output

300‧‧‧全差分放大電路 300‧‧‧ Fully Differential Amplifier Circuit

302‧‧‧主要光偵測器 302‧‧‧Main light detector

304‧‧‧第一系統輸入 304‧‧‧First system input

306‧‧‧第二系統輸入 306‧‧‧Second system input

308‧‧‧主要偏壓電路 308‧‧‧main bias circuit

312‧‧‧第一跨阻抗放大電路 312‧‧‧First transimpedance amplifier circuit

314‧‧‧第一跨阻抗電壓輸出 314‧‧‧First transimpedance voltage output

316‧‧‧第一電流輸入 316‧‧‧First current input

318‧‧‧第一偏壓電壓輸入 318‧‧‧First bias voltage input

320‧‧‧第二跨阻抗放大電路 320‧‧‧Second transimpedance amplifier circuit

322‧‧‧第二跨阻抗電壓輸出 322‧‧‧Second transimpedance voltage output

324‧‧‧第二電流輸入 324‧‧‧second current input

326‧‧‧第二偏壓電壓輸入 326‧‧‧Second bias voltage input

328‧‧‧第一輸出 328‧‧‧ first output

330‧‧‧第二輸出(第二開關) 330‧‧‧second output (second switch)

350‧‧‧差分跨阻抗放大級(盲級) 350‧‧‧Differential transimpedance amplification stage (blind level)

360‧‧‧導電的迴路 360‧‧‧Electrical circuit

430、432‧‧‧差分電壓放大器級 430, 432‧‧‧Differential voltage amplifier stage

434、436‧‧‧放大級 434, 436‧‧‧Amplification

438、440‧‧‧放大級 438, 440‧‧‧Amplification

502‧‧‧盲光偵測器 502‧‧‧Blind light detector

512‧‧‧第三跨阻抗放大器電路 512‧‧‧ third transimpedance amplifier circuit

518‧‧‧電壓輸入 518‧‧‧Voltage input

520‧‧‧第四跨阻抗放大器電路 520‧‧‧fourth transimpedance amplifier circuit

526‧‧‧電壓輸入 526‧‧‧Voltage input

554、556‧‧‧比較器 554, 556‧‧‧ comparator

1100‧‧‧電腦系統 1100‧‧‧ computer system

1101‧‧‧處理器 1101‧‧‧ Processor

1102‧‧‧快取記憶體單元 1102‧‧‧Cache memory unit

1103‧‧‧記憶體 1103‧‧‧ memory

1104‧‧‧RAM 1104‧‧‧RAM

1105‧‧‧ROM 1105‧‧‧ROM

1106‧‧‧基本輸入/輸出系統(BIOS) 1106‧‧‧Basic Input/Output System (BIOS)

1107‧‧‧儲存體控制單元 1107‧‧‧Storage Control Unit

1108‧‧‧儲存體 1108‧‧‧ Storage

1109‧‧‧作業系統 1109‧‧‧Operating system

1110‧‧‧執行檔 1110‧‧‧Execution file

1111‧‧‧資料 1111‧‧‧Information

1112‧‧‧API應用程式 1112‧‧‧API application

1120‧‧‧網路介面 1120‧‧‧Network interface

1121‧‧‧繪圖控制 1121‧‧‧ Drawing Control

1122‧‧‧視訊介面 1122‧‧‧Video interface

1123‧‧‧輸入介面 1123‧‧‧Input interface

1124‧‧‧輸出介面 1124‧‧‧Output interface

1125‧‧‧儲存裝置介面 1125‧‧‧Storage device interface

1126‧‧‧儲存媒體介面 1126‧‧‧Storage media interface

1130‧‧‧網路(網路區段) 1130‧‧‧Network (network section)

1132‧‧‧顯示器 1132‧‧‧ display

1133‧‧‧輸入裝置 1133‧‧‧ Input device

1134‧‧‧輸出裝置 1134‧‧‧ Output device

1135‧‧‧儲存裝置 1135‧‧‧Storage device

1136‧‧‧儲存媒體 1136‧‧‧Storage media

1140‧‧‧匯流排 1140‧‧ ‧ busbar

id‧‧‧暗偏移電流 i d ‧‧‧dark offset current

ip‧‧‧光電流 i p ‧‧‧Photocurrent

Rf‧‧‧回授電阻 R f ‧‧‧Responsive resistance

v1‧‧‧差分電壓(主要差分輸出) v 1 ‧‧‧Differential voltage (main differential output)

v2、v3‧‧‧差分電壓輸出 v 2 , v 3 ‧‧ ‧Differential voltage output

v4‧‧‧盲差分輸出 v 4 ‧‧ ‧blind differential output

v5‧‧‧差分輸出 v 5 ‧‧‧Differential output

vt‧‧‧差分電壓 v t ‧‧‧Differential voltage

本發明之各種的目的及優點以及更完整的理解透過結合所附的圖式來參照以下的詳細說明以及所附的申請專利範圍時將會是明顯且 更容易體會的。 The various objects and advantages of the present invention, as well as the more complete understanding of the invention. It's easier to understand.

圖1是展示一種傳統的高溫計系統,其係具有一光偵測器以及一具有一回授電阻Rf的跨阻抗放大器,其中增益係成比例於該回授電阻Rf;圖2是描繪一種高溫計系統的一實施例;圖3是描繪一用於在高溫計中放大一光學信號的全差分放大電路的一實施例;圖4是描繪具有額外增益級的一全差分放大電路的另一實施例,該額外的增益級針對在圖3所討論之差分跨阻抗放大級的差分輸出提供二增益位準;圖5是描繪一全差分放大電路的另一實施例;圖6是描繪一全差分放大電路的又一實施例;圖7是描繪一全差分放大電路的一詳細視圖;圖8是描繪一全差分放大電路的一詳細視圖,但具有逆向的開關狀態;圖9是描繪一差分前端的再一實施例,該差分前端提供兩個差分電壓訊號至一對類比至數位轉換器;圖10是描繪一種高溫計系統的一實施例;及圖11是展示一種設備的一實施例之概略的表示。 1 is a conventional pyrometer system having a photodetector and a transimpedance amplifier having a feedback resistor Rf , wherein the gain is proportional to the feedback resistor Rf ; An embodiment of a pyrometer system; FIG. 3 depicts an embodiment of a fully differential amplifier circuit for amplifying an optical signal in a pyrometer; FIG. 4 is a diagram depicting a fully differential amplifier circuit having an additional gain stage. In one embodiment, the additional gain stage provides a second gain level for the differential output of the differential transimpedance amplification stage discussed in FIG. 3; FIG. 5 is another embodiment depicting a fully differential amplification circuit; FIG. Yet another embodiment of a fully differential amplifying circuit; FIG. 7 is a detailed view depicting a fully differential amplifying circuit; FIG. 8 is a detailed view depicting a fully differential amplifying circuit, but with a reverse switching state; FIG. In still another embodiment of the differential front end, the differential front end provides two differential voltage signals to a pair of analog to digital converters; FIG. 10 depicts an embodiment of a pyrometer system; and FIG. 11 shows an apparatus Example schematic representation of an embodiment.

本揭露內容係大致有關於光學高溫量測。尤其(但非限制性的),本揭露內容係有關用於光學高溫量測的改良的放大器之系統、方法及 設備。 The disclosure is generally related to optical high temperature measurement. In particular, but not limiting, the disclosure is directed to systems, methods, and methods for improved amplifiers for optical high temperature measurements device.

該字詞"範例的"係在此被使用來表示"當作為一個例子、實例、或是例証"。任何在此敘述為"範例的"實施例並不一定欲被解釋為比其它實施例較佳或是有利的。 The word "example" is used herein to mean "as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

該術語"差分放大電路"係在此被使用來表示一具有兩個驅動的輸入的放大器。 The term "differential amplifying circuit" is used herein to mean an amplifier having two driven inputs.

該術語"放大級"係在此被使用來指稱一電路或系統,其係具有一或多個輸入以及成比例於(但是被放大)該一或多個輸入的一或多個輸出。一放大級可包含一或多個放大器,例如是運算放大器、BJT、MOSFET、以及其它。 The term "amplification stage" is used herein to refer to a circuit or system having one or more inputs and one or more outputs proportional to (but amplified) the one or more inputs. An amplifier stage can include one or more amplifiers, such as operational amplifiers, BJTs, MOSFETs, and others.

該術語"偏壓電路"係在此被使用來指稱一被建構以施加一偏壓至一較大的電路或系統的另一部分的電路。 The term "biasing circuit" is used herein to refer to a circuit that is configured to apply a bias voltage to a larger portion of a larger circuit or system.

該術語"差分電壓放大器級"係在此被使用來指稱一具有兩個驅動的電壓輸入以及一差分電壓輸出的電路。 The term "differential voltage amplifier stage" is used herein to refer to a circuit having two driven voltage inputs and a differential voltage output.

該等術語"差分輸入"以及"差分輸出"係在此被使用來指出一具有兩個接腳以及一在該兩個接腳之間的電壓之輸入或輸出。 The terms "differential input" and "differential output" are used herein to indicate an input or output having two pins and a voltage between the two pins.

該術語"盲光偵測器"、"盲光電流"、"盲偏壓"、以及"盲級"都是指稱一放大電路的用來考量或從一主要光偵測器的量測減去一漏電流之特點。 The terms "blind photodetector", "blind photocurrent", "blind bias", and "blind" are all referred to as an amplifier circuit for consideration or subtraction from the measurement of a primary photodetector. A characteristic of leakage current.

該術語"耦接至"可以指稱在構件之間例如是經由一不中斷的導線或引線之直接的連接、或是可以指稱在構件之間例如是經由另一構件或電路之間接的連接。譬如,兩個電容器可以透過一個二極體或電感器 來彼此耦接。 The term "coupled to" may refer to a direct connection between components, such as via an uninterrupted wire or lead, or a connection between components, such as via another component or circuit. For example, two capacitors can pass through a diode or inductor To couple with each other.

傳統的光學高溫計是受到低的信號對雜訊比、由光偵測器中的漏電流引起的誤差所困擾,而且並不能夠處理廣範圍的見於高溫量測中的放射振幅。譬如,因為光電流可能是低到10-13安培,因此顯著的放大是所需的。在目前用於高溫量測的單級放大器下,偵測此種小信號所需的增益是需要一非常大的回授電阻Rf(見於圖1的一種傳統的單級放大系統)。圖1是展示一種傳統的高溫計系統,其係具有一光偵測器102以及一具有一回授電阻Rf的跨阻抗放大器104,其中增益係成比例於該回授電阻Rf。吾人可以看出在需要大的增益之情形中,例如是在高溫量測的情況中,Rf通常必須是非常大的,以便於能夠看到此種小信號。然而,一大的Rf亦對應於高的雜訊。因此,例如是104的單級跨阻抗放大器的使用係固有地受限於高的雜訊或是不足的增益。 Conventional optical pyrometers suffer from low signal-to-noise ratios, errors caused by leakage currents in photodetectors, and are not capable of handling a wide range of radiation amplitudes found in high temperature measurements. For example, because the photocurrent may be as low as 10 -13 amps, significant amplification is required. In the current single-stage amplifiers used for high temperature measurements, the gain required to detect such small signals requires a very large feedback resistor Rf (see a conventional single stage amplification system of Figure 1). 1 is a conventional pyrometer system having a photodetector 102 and a transimpedance amplifier 104 having a feedback resistor Rf , wherein the gain is proportional to the feedback resistor Rf . It can be seen that in situations where a large gain is required, such as in the case of high temperature measurements, Rf must typically be very large in order to be able to see such small signals. However, a large R f also corresponds to high noise. Thus, the use of a single stage transimpedance amplifier, such as 104, is inherently limited by high noise or insufficient gain.

該跨阻抗放大器104的輸出係被傳遞在兩個方向上:(1)至另一放大級106;或是(2)至一不具有另外的增益之機械式選擇器108。並且注意到的是,增益係成比例於該回授電阻器Rf的大小,此於是在放大後的信號中造成大的雜訊。 The output of the transimpedance amplifier 104 is transmitted in two directions: (1) to another amplification stage 106; or (2) to a mechanical selector 108 without additional gain. It is also noted that the gain is proportional to the magnitude of the feedback resistor Rf , which then causes large noise in the amplified signal.

在辛苦嘗試對於例如是描繪在圖1中的傳統的放大方案的各種修改之後,本案發明人體認到這些問題可能是在此項技術傳統所使用的單級非差分的放大器(例如,104)所固有的。儘管高溫計的設計者一直總是使用單級非差分的放大器,但是本案發明人思索一種完全不同的放大結構是否可以克服本案發明人所認為是在高溫計中的單級非差分的放大所固有的限制者。 After painstaking attempts to various modifications, such as the conventional magnification scheme depicted in FIG. 1, the present invention recognizes that these problems may be a single-stage non-differential amplifier (eg, 104) used in the art tradition. inherent. Although the designer of the pyrometer always uses a single-stage non-differential amplifier, the inventor of the present invention wondered whether a completely different amplification structure could overcome the single-stage non-differential amplification that the inventors believe to be in the pyrometer. Limiter.

差分放大器先前並未被用在高溫計中,因為差分放大器是普遍使用在其中量測範圍是相當窄的情形中(亦即,一個小的動態範圍的量測是所需的)。在高溫量測中,光電流可能變化在10-13安培到10-6安培之間(七個數量級),並且因此差分放大器並未被認為是適合用於此類型的偵測。此外,差分放大裝置係對於放大系統帶來增加的構件以及增大的成本與複雜度。 Differential amplifiers have not previously been used in pyrometers because differential amplifiers are commonly used in situations where the measurement range is quite narrow (i.e., a small dynamic range measurement is required). In high temperature measurements, the photocurrent may vary between 10-13 amps to 10 -6 amps (seven orders of magnitude), and thus differential amplifiers are not considered suitable for this type of detection. In addition, the differential amplification device introduces increased components and increased cost and complexity for the amplification system.

儘管有這些缺點,本案發明人仍然塑造一差分放大電路以用於在一高溫計中量測光電流,並且出乎意料地看到有希望的結果(亦即,相較於在數十年的單級非差分放大級中所達成者為較低的雜訊、一較寬的動態範圍、以及一較快的取樣速率)。 Despite these shortcomings, the inventors of the present invention still model a differential amplifier circuit for measuring photocurrent in a pyrometer and unexpectedly see promising results (i.e., compared to decades). The one achieved in the single-stage non-differential amplification stage is lower noise, a wider dynamic range, and a faster sampling rate).

本案發明人亦體認到偵測器電流可以藉由在該光偵測器上增加一逆向偏壓而被增大(因此,其係需要較小的放大,並且因此造成較小的雜訊)。此種調整的不利處是該光偵測器會見到以增大的逆向偏壓的一函數而增大的漏電流。漏電流是溫度相依的,並且因此在高溫計運作所在的高溫下(由於它們經常是被黏貼到熱處理室或是在其附近),單獨利用軟體為基礎的校正是難以析出漏電流的因數。為了考量漏電流,一"盲"偏壓係被施加至一與盡可能多的光學及IR放射隔離的"盲"光偵測器。以此種方式,來自該盲光偵測器的電流係被預期是僅代表漏電流,並且若被施加至該盲光偵測器的偏壓是和被施加至該主要光偵測器的偏壓相同,則來自該盲光偵測器的電流應該是在該主要光偵測器中的漏電流之一值得的估計。來自該被偏壓的盲光偵測器的量測可以從該主要光偵測器的量測中減去,以考量或移除漏電流在量測的溫度上的影響。該盲偏壓係以和被施加至該主要光 偵測器的偏壓相同的大小來偏壓該盲偵測器,但是該盲光偵測器係與幾乎所有的放射源隔離,使得其輸出幾乎完全是由於產生自在該盲光偵測器上的逆向偏壓的漏電流所造成的。以此種方式,該盲光偵測器的輸出係代表來自該主要光偵測器之信號由於來自該主要光偵測器的漏電流所造成的部分。藉由從該主要偵測器的輸出中減去該盲光偵測器的輸出,漏電流可以從該量測加以打消,而不論該放大系統的偏壓及溫度為何。 The inventor of the present invention also recognizes that the detector current can be increased by adding a reverse bias to the photodetector (hence, it requires less amplification and therefore less noise). . The disadvantage of such an adjustment is that the photodetector will see an increase in leakage current as a function of increased reverse bias. Leakage currents are temperature dependent, and therefore, software-based calibration alone is a factor that makes it difficult to precipitate leakage currents at the high temperatures at which the pyrometers operate (since they are often stuck to or in the vicinity of the thermal processing chamber). To account for leakage current, a "blind" bias is applied to a "blind" photodetector that is isolated from as much optical and IR radiation as possible. In this manner, the current from the blind photodetector is expected to represent only the leakage current, and if the bias applied to the blind photodetector is the bias applied to the primary photodetector If the voltage is the same, the current from the blind photodetector should be an estimate of the value of the leakage current in the primary photodetector. The measurement from the biased blind light detector can be subtracted from the measurement of the primary photodetector to account for or remove the effect of the leakage current on the measured temperature. The blind bias is applied to and applied to the primary light The detector is biased the same size to bias the blind detector, but the blind detector is isolated from almost all sources so that its output is almost entirely due to the generation of the blind detector. Caused by the reverse biased leakage current. In this manner, the output of the blind photodetector represents the portion of the signal from the primary photodetector due to leakage current from the primary photodetector. By subtracting the output of the blind photodetector from the output of the primary detector, leakage current can be cancelled from the measurement regardless of the bias voltage and temperature of the amplification system.

傳統的高溫量測放大方案的另一問題亦可以見於圖1中,其中在不同的可選的增益是所要的情形中,為了處理在信號強度上的寬的擺幅,一第二增益級106可被實施成使得高增益107以及低增益109的輸出是存在的。一通常是機械式開關的選擇器108係選擇該些輸出107、109中的哪一個被傳遞至一類比至數位轉換器110(ADC)。在一處理行程期間,被量測的目標的溫度可能會激烈地改變而使得該選擇器108必須切換在該高增益的輸出107以及該低增益的輸出109之間,因而此可能會在該資料中造成一接縫(stitch)。 Another problem with conventional high temperature measurement amplification schemes can also be seen in Figure 1, where a second gain stage 106 is used to handle a wide swing in signal strength in the case where different selectable gains are desired. It can be implemented such that the outputs of the high gain 107 and the low gain 109 are present. A selector 108, typically a mechanical switch, selects which of the outputs 107, 109 is passed to an analog to digital converter 110 (ADC). During a processing pass, the temperature of the measured target may change drastically such that the selector 108 must switch between the high gain output 107 and the low gain output 109, and thus this may be in the data Create a seam in the middle.

為了解決此種在資料中的接縫,本案發明人已經實施一對ADC 204、206(參見圖2),每一個ADC是從一全差分放大電路202接收一差分輸出,並且每一個ADC是提供一數位輸出216、218至一處理器210的一選擇器208。不同於其中只有一經放大的信號會到達該處理器之傳統的方法,本案發明人的解決方案是使得兩個數位輸出216、218都能夠到達該處理器,因此使得在增益級之間的選擇能夠用軟體來加以執行,而且能夠在任何時點來加以執行。以此種方式,接縫並未發生在該選擇器208切換在該些輸出216、218之間時。 To address this seam in the data, the inventors have implemented a pair of ADCs 204, 206 (see Figure 2), each of which receives a differential output from a fully differential amplifier circuit 202, and each ADC is provided A digital output 216, 218 to a selector 208 of a processor 210. Unlike the conventional method in which only one amplified signal would reach the processor, the inventor's solution is to enable both digital output 216, 218 to reach the processor, thus enabling selection between gain stages. It is executed in software and can be executed at any point in time. In this manner, the seam does not occur when the selector 208 switches between the outputs 216, 218.

現在將轉而討論在圖2-9中所描繪的系統、方法及設備之更詳細的說明。 A more detailed description of the systems, methods and apparatus depicted in Figures 2-9 will now be discussed.

圖2是描繪一種高溫計系統200。該系統200可包含一可能被偏壓或是可能未被偏壓之主要光偵測器201,並且若被偏壓的話,其可被偏壓在0V至一逆向偏壓之間,其中在該逆向偏壓的大小上並沒有給予限制。該系統200亦可包含一雙差分放大電路202,該雙差分放大電路202可包含一對例如是跨阻抗運算放大器的跨阻抗放大器。該對跨阻抗放大器可被配置以用於耦接至該主要光偵測器201,使得該跨阻抗放大器係轉換一通過該主要光偵測器201的光電流ip成為一在該些跨阻抗放大器的每一個的一輸出處之電壓。由於該些跨阻抗放大器係被平行的配置,其輸出可以是一差分電壓,其係提供比具有等同的增益之單級非差分的放大器較小的雜訊(或是根據相同的雜訊位準之較大的增益、或是一較佳的信號對雜訊比)。該雙差分放大電路202可以具有兩個成比例於藉由該主要光偵測器201產生的光電流ip之差分電壓輸出212、214。然而,該兩個差分電壓輸出212、214可以具有不同的增益。 FIG. 2 is a diagram of a pyrometer system 200. The system 200 can include a primary photodetector 201 that may or may not be biased, and if biased, may be biased between 0V and a reverse bias, where There is no limit to the magnitude of the reverse bias. The system 200 can also include a dual differential amplification circuit 202 that can include a pair of transimpedance amplifiers, such as transimpedance operational amplifiers. The pair of transimpedance amplifiers can be configured to be coupled to the primary photodetector 201 such that the transimpedance amplifier converts a photocurrent i p through the primary photodetector 201 into a plurality of transimpedances The voltage at an output of each of the amplifiers. Since the transimpedance amplifiers are arranged in parallel, the output can be a differential voltage that provides less noise than a single-stage non-differential amplifier with equivalent gain (or according to the same noise level). A larger gain, or a better signal-to-noise ratio). The double differential amplifier circuit 202 may have two outputs 212, 214 is proportional to the differential voltage current i p of the light by the photodetector 201 is mainly generated. However, the two differential voltage outputs 212, 214 can have different gains.

該兩個差分電壓輸出212、214的每一個可耦接至一個別的類比至數位轉換器(ADC),例如該第一ADC 204以及第二ADC 206。該第一ADC 204可被配置以轉換該第一差分電壓輸出212成為一對應的數位值。該第一ADC 204亦可以具有一第一數位輸出216,其係提供該對應的數位值至該處理器210。 Each of the two differential voltage outputs 212, 214 can be coupled to a different analog to digital converter (ADC), such as the first ADC 204 and the second ADC 206. The first ADC 204 can be configured to convert the first differential voltage output 212 to a corresponding digital value. The first ADC 204 can also have a first digital output 216 that provides the corresponding digital value to the processor 210.

該第二ADC 206可被配置以轉換該第二差分電壓輸出214成為一對應的數位值。該第二ADC 206亦可以具有一第二數位輸出218,其 係提供該對應的數位值至該處理器210。 The second ADC 206 can be configured to convert the second differential voltage output 214 to a corresponding digital value. The second ADC 206 can also have a second digital output 218, The corresponding digit value is provided to the processor 210.

該處理器210可耦接至該第一及第二數位輸出216、218。該處理器210可以具有一耦接至該第一及第二數位輸出216、218的選擇器208(例如,一開關)。該選擇器208可被配置以選擇該第一及第二數位輸出216、218中的哪一個,以藉由該處理器210來加以處理。再者,該處理器210可被配置以轉換該第一及第二數位輸出216、218中之一所選者成為一溫度或反射係數值,並且可以具有一提供該溫度或反射係數值的輸出220。通常,反射係數值係被用來藉由指出一目標的表面的一反射度以校準溫度量測。此校準接著可被用來改善溫度量測的精確性。因此,針對於溫度及反射係數兩者的量測可以藉由該系統200來加以完成。 The processor 210 can be coupled to the first and second digital outputs 216, 218. The processor 210 can have a selector 208 (eg, a switch) coupled to the first and second digital outputs 216, 218. The selector 208 can be configured to select which of the first and second digit outputs 216, 218 to be processed by the processor 210. Moreover, the processor 210 can be configured to convert one of the first and second digit outputs 216, 218 to a temperature or reflection coefficient value and can have an output that provides the temperature or reflection coefficient value. 220. Typically, the reflection coefficient value is used to calibrate the temperature measurement by indicating a reflectance of the surface of a target. This calibration can then be used to improve the accuracy of the temperature measurement. Therefore, measurements for both temperature and reflection coefficient can be accomplished by the system 200.

該雙差分放大電路202可包含一主要偏壓電路,該主要偏壓電路係被配置以在該主要光偵測器201上造成一偏壓。此偏壓範圍可以從0V到一逆向偏壓,該逆向偏壓的振幅並無限制。一較大的逆向偏壓係降低一橫跨該主要光偵測器201的電容,並且致能一較高的取樣速率。然而,較低的電容亦表示大的漏電流,因而在增大的速度下有必要處理並且析出增大的漏電流的因數。此種電流在此應用中尤其是麻煩的,因為它們隨著溫度而增加,並且該系統200的溫度通常是在35℃到45℃之間(其顯著高於環境)。 The dual differential amplifier circuit 202 can include a primary bias circuit configured to cause a bias on the primary photodetector 201. This bias range can range from 0V to a reverse bias, and the amplitude of the reverse bias is not limited. A larger reverse bias reduces the capacitance across the primary photodetector 201 and enables a higher sampling rate. However, the lower capacitance also represents a large leakage current, so it is necessary to process and precipitate an increased leakage current factor at an increased speed. Such currents are particularly troublesome in this application because they increase with temperature, and the temperature of the system 200 is typically between 35 °C and 45 °C (which is significantly higher than the environment).

圖3是描繪一用於在高溫計中放大一光學信號的全差分放大電路300的一實施例。此電路300可以是高速的、高增益的,並且具有一高的動態範圍,亦即已經證明是在習知技術的高溫量測放大方案中不可能達成的屬性的一組合。該系統300係經由在以下描述的一些結構特點來達 成此。其中之一是,該系統300可包含一第一系統輸入304以及一第二系統輸入306,其係被配置以分別耦接至一主要光偵測器302的一陽極以及陰極。換言之,該放大電路300在製造及銷售時可以和該偵測硬體結合成一體、或是可以未結合成一體。譬如,一LED驅動器、LED、耦接至處理室的光纖、以及一偵測器可被銷售為一與該放大電路300分開之結合成一體的包裝。當該第一及第二系統輸入304、306耦接至該主要光偵測器302時,一光電流ip係通過在該第二及第一系統輸入306、304之間。換言之,如同在圖3中可見的,光電流ip係和該光偵測器302的極性相反的流動。 3 is an illustration of an embodiment of a fully differential amplification circuit 300 for amplifying an optical signal in a pyrometer. This circuit 300 can be high speed, high gain, and has a high dynamic range, i.e., a combination of attributes that have proven to be impossible in conventional high temperature metrology amplification schemes. The system 300 achieves this via some of the structural features described below. One of the systems 300 can include a first system input 304 and a second system input 306 that are configured to be coupled to an anode and a cathode of a primary photodetector 302, respectively. In other words, the amplifying circuit 300 may be integrated with the detecting hardware during manufacture and sale, or may not be integrated. For example, an LED driver, an LED, an optical fiber coupled to the processing chamber, and a detector can be sold as a package that is separate from the amplifying circuit 300. When the first and second system inputs 304, 306 coupled to the primary photodetector 302, an optical system through an input current i p 306, 304 between the first and second systems. In other words, as seen in FIG. 3, the polarity of the current i p optical system and the photodetector 302 opposite to the flow.

該電路300亦可包含一差分跨阻抗放大級350。此第一放大級350係具有被配置以接收該光電流ip的輸入,並且在某個跨阻抗增益下(亦牽涉到從電流至電壓的轉變之增益)轉換該光電流ip成為一差分電壓vt。假設兩個放大器級是產生相同的雜訊位準,相較於單一放大器電路,一差分跨阻抗放大級350的使用係容許至少一2×增益因數。譬如,在單一跨阻抗放大器電路係轉換一10-10Amp的光電流ip成為一個1V輸出的情形中,該舉例說明的差分設置係在該第一跨阻抗放大電路312的輸出314產生+1V,並且在該第二跨阻抗放大電路320的輸出322產生-1V的輸出。因此,該差分電壓v1是2V、或是單一放大器可能達成的增益的兩倍。然而,針對於此增大的增益之雜訊懲罰並未比見於單一放大器中的雜訊差。於是,該差分跨阻抗放大級350係產生一比習知技術的高溫量測放大級更高的信號雜訊比。 The circuit 300 can also include a differential transimpedance amplification stage 350. The first amplification stage 350 has an input configured to receive the photocurrent i p and convert the photo current i p into a differential under a certain transimpedance gain (also involving a gain from a current to voltage transition) Voltage v t . Assuming that the two amplifier stages produce the same noise level, the use of a differential transimpedance amplifier stage 350 allows for at least a 2 x gain factor compared to a single amplifier circuit. For example, the transimpedance amplifier circuit on a single line 10 -10 Amp converting a photocurrent i p 1V be a case where the output of the differential system is provided that illustrates the generation 314 of a first transimpedance amplifying circuit 312 outputs + 1V And at the output 322 of the second transimpedance amplifying circuit 320 produces an output of -1V. Therefore, the differential voltage v 1 is 2V, or twice the gain that a single amplifier can achieve. However, the noise penalty for this increased gain is not better than the noise difference seen in a single amplifier. Thus, the differential transimpedance amplification stage 350 produces a higher signal to noise ratio than the high temperature measurement amplification stage of the prior art.

該差分跨阻抗放大級350可包含一主要偏壓電路308,其係被配置以經由第一及第二跨阻抗放大電路312、320來偏壓該主要光偵測器302。該主要偏壓電路308並非必須的,並且在某些實施例中可被一連線至 接地所取代。在一偏壓被施加的情形中,其範圍可以是在0V到某個逆向偏壓之間。該主要偏壓電路308的一極性係被展示成使得一逆向偏壓存在於橫跨該主要光偵測器302處。該主要偏壓電路308可以具有一第一及第二輸出328、330。 The differential transimpedance amplifier stage 350 can include a primary bias circuit 308 that is configured to bias the primary photodetector 302 via the first and second transimpedance amplifying circuits 312, 320. The primary bias circuit 308 is not required and, in some embodiments, can be connected to Replaced by grounding. In the case where a bias voltage is applied, it may range from 0V to some reverse bias. A polarity of the primary bias circuit 308 is shown such that a reverse bias exists across the primary photodetector 302. The primary bias circuit 308 can have a first and second output 328, 330.

該差分跨阻抗放大級350亦可包含一第一跨阻抗放大電路312,其係具有一第一電流輸入316以及一第一跨阻抗電壓輸出314。該些跨阻抗放大電路312、320的一實施例的細節可以見於圖7及8中。該第一電流輸入316可以接收該光電流ip,並且該第一跨阻抗放大電路312可以轉換此電流成為一見於該第一跨阻抗電壓輸出314處的第一輸出電壓。 The differential transimpedance amplifier stage 350 can also include a first transimpedance amplifier circuit 312 having a first current input 316 and a first transimpedance voltage output 314. Details of an embodiment of the transimpedance amplifying circuits 312, 320 can be seen in Figures 7 and 8. The first current input 316 can receive the photocurrent i p , and the first transimpedance amplifying circuit 312 can convert the current into a first output voltage that is seen at the first transimpedance voltage output 314 .

該第一電流輸入316可耦接至該第一系統輸入304,並且該第一偏壓電壓輸入318可耦接至該主要偏壓電路308的第一輸出328。換言之,該第一跨阻抗放大電路312可以具有兩個輸入-一個是針對於來自該主要光偵測器302的電流、以及一個是針對於一等於在該主要偏壓電路308的第一輸出328處的一偏壓之參考電壓。 The first current input 316 can be coupled to the first system input 304 and the first bias voltage input 318 can be coupled to the first output 328 of the primary bias circuit 308 . In other words, the first transimpedance amplifying circuit 312 can have two inputs - one for the current from the primary photodetector 302 and one for a first output equal to the primary bias circuit 308 A bias voltage reference voltage at 328.

一第一輸出電壓可以見於該第一跨阻抗電壓輸出314處,並且此第一輸出電壓可以是成比例於該光電流ipA first output voltage can be seen at the first transimpedance voltage output 314, and the first output voltage can be proportional to the photocurrent ip .

該差分跨阻抗放大級350亦可包含一第二跨阻抗放大電路320,其係具有一第二電流輸入324以及一第二跨阻抗電壓輸出322。該第二電流輸入324可以接收該光電流ip,並且該第二跨阻抗放大電路320可以轉換此電流成為一見於該第二跨阻抗電壓輸出322處的第二輸出電壓。 The differential transimpedance amplifier stage 350 can also include a second transimpedance amplifier circuit 320 having a second current input 324 and a second transimpedance voltage output 322. The second current input 324 can receive the photocurrent i p , and the second transimpedance amplifying circuit 320 can convert the current into a second output voltage seen at the second transimpedance voltage output 322 .

該第二電流輸入324可耦接至該第二系統輸入306,並且該第二偏壓電壓輸入326可耦接至該主要偏壓電路308的第二輸出330。換言 之,該第二跨阻抗放大電路320可以具有兩個輸入-一個是針對源自於該第二跨阻抗放大電路320至該主要光偵測器302的電流、以及一個是針對於一等於在該主要偏壓電路308的第二輸出330處的一偏壓之參考電壓。 The second current input 324 can be coupled to the second system input 306 , and the second bias voltage input 326 can be coupled to the second output 330 of the primary bias circuit 308 . In other words The second transimpedance amplifying circuit 320 can have two inputs - one for the current from the second transimpedance amplifying circuit 320 to the main photodetector 302, and one for one equal to A reference voltage of a bias voltage at the second output 330 of the primary bias circuit 308.

一第二輸出電壓可以見於該第二跨阻抗電壓輸出322處,並且此第二輸出電壓可以是成比例於該光電流ip,但是具有一和在該第一跨阻抗電壓輸出314處的第一輸出電壓相反的極性。因此,一差分電壓v1係具有一大小是該第一或第二輸出電壓的兩倍,並且因此具有比任一個跨阻抗放大電路單獨所可能提供者更大的增益。 A second output voltage can be found in the second trans-impedance voltage output 322, and this second output voltage may be proportional to the photocurrent i p, but having a second and the first output 314 of the voltage across the impedance An opposite polarity of the output voltage. Thus, a differential voltage v 1 has a magnitude that is twice the first or second output voltage and therefore has a greater gain than would be provided by any of the transimpedance amplification circuits alone.

參考圖4,圖4是描繪一全差分放大電路的另一實施例。圖4和圖3的差異在於圖4包括額外的增益級(即第一差分電壓放大器級430和第二差分電壓放大器級432)。該等增益級針對在圖3所討論之差分跨阻抗放大級的差分輸出提供二個增益位準,以產生第二差分電壓輸出v2和第三差分電壓輸出v3,其中第二差分電壓輸出v2和第三差分電壓輸出v3係對應至圖2之第一差分電壓輸出212和第二差分電壓輸出214。 Referring to Figure 4, Figure 4 is another embodiment depicting a fully differential amplifier circuit. The difference between FIG. 4 and FIG. 3 is that FIG. 4 includes additional gain stages (ie, first differential voltage amplifier stage 430 and second differential voltage amplifier stage 432). The gain stages provide two gain levels for the differential output of the differential transimpedance amplification stage discussed in FIG. 3 to produce a second differential voltage output v 2 and a third differential voltage output v 3 , where the second differential voltage output v 2 and the third differential voltage output v 3 correspond to the first differential voltage output 212 and the second differential voltage output 214 of FIG.

參考圖5,圖5是描繪一全差分放大電路的另一實施例。圖5和圖4的差異在於第一差分電壓放大器級430可以由放大級434和放大級436所組成,而第二差分電壓放大器級432可以由放大級438和放大級440所組成。 Referring to Figure 5, Figure 5 is another embodiment depicting a fully differential amplifier circuit. The difference between FIG. 5 and FIG. 4 is that the first differential voltage amplifier stage 430 can be comprised of an amplification stage 434 and an amplification stage 436, and the second differential voltage amplifier stage 432 can be comprised of an amplification stage 438 and an amplification stage 440.

參考圖6,圖6是描繪一全差分放大電路的又一實施例。圖6其和圖4的差異在於全差分放大電路可以額外包含一盲級552、比較器554、比較器556。該盲級552可以包括一盲光偵測器和一盲偏壓電路。該盲光偵測器係與該主要光偵測器所看到的大多數的光子放射隔離開,但是 在結構上與該主要光偵測器相同,以代表該主要光偵測器302的一漏電流。該盲偏壓電路係耦接至一第三跨阻抗放大器電路512以及一第四跨阻抗放大器電路520的電壓輸入518、526,並且被配置以利用與橫跨該主要光偵測器302的該偏壓等同大小的偏壓來對該盲光偵測器502進行偏壓。盲級552可輸出一盲差分輸出v4Referring to Figure 6, Figure 6 depicts yet another embodiment of a fully differential amplifier circuit. FIG. 6 differs from FIG. 4 in that the fully differential amplifying circuit can additionally include a blind stage 552, a comparator 554, and a comparator 556. The blind stage 552 can include a blind light detector and a blind bias circuit. The blind light detector is isolated from most of the photon radiation seen by the primary light detector, but is identical in structure to the primary light detector to represent one of the primary light detectors 302 Leakage current. The blind biasing circuit is coupled to a third transimpedance amplifier circuit 512 and a voltage input 518, 526 of a fourth transimpedance amplifier circuit 520, and is configured to utilize and span the primary photodetector 302. The bias voltage is equal to the magnitude of the bias to bias the blind photodetector 502. The blind stage 552 can output a blind differential output v 4 .

比較器554和比較器556的每一個係具有一對輸入並且耦接至該主要差分電壓輸出v1以及該盲差分電壓輸出v4,該些比較器554、556係具有極性以使得該對比較器554、556的一差分輸出v5係等於在該主要差分輸出v1與該盲差分輸出v4之間的一差值。 Each of comparator 554 and comparator 556 has a pair of inputs coupled to the primary differential voltage output v 1 and the blind differential voltage output v 4 , the comparators 554, 556 having a polarity such that the pair is compared A differential output v 5 of the 554, 556 is equal to a difference between the primary differential output v 1 and the blind differential output v 4 .

參考圖7~8,圖7~8是描繪圖6之一全差分放大電路的一詳細視圖,其中圖6中之第一差分電壓放大器級430和第二差分電壓放大器級432已分別改用圖5中之第一差分電壓放大器級430和第二差分電壓放大器級432來表示。全部的第一跨阻抗放大器電路312、第二跨阻抗放大器電路320、第三跨阻抗放大器電路512、第四跨阻抗放大器電路520皆改用圖1之具有回授電阻例如Rf之跨阻抗放大器104來表示。 Referring to FIGS. 7-8, FIGS. 7-8 are detailed views depicting a fully differential amplifying circuit of FIG. 6, wherein the first differential voltage amplifier stage 430 and the second differential voltage amplifier stage 432 of FIG. 6 have been respectively modified. The first differential voltage amplifier stage 430 and the second differential voltage amplifier stage 432 of 5 are represented. All of the first transimpedance amplifier circuit 312, the second transimpedance amplifier circuit 320, the third transimpedance amplifier circuit 512, and the fourth transimpedance amplifier circuit 520 use the transimpedance amplifier of FIG. 1 with a feedback resistor such as R f . 104 to indicate.

在全部跨阻抗放大器電路中的回授電阻的數值可以是任何合適的數值,並且回授電阻的數值可以彼此相同或不同。例如,這是可能的:R1=R2=Rf、R1=R2≠Rf、R1≠R2≠Rf...等等。此外,在全部跨阻抗放大器電路中的單一電阻符號並未意謂跨阻抗放大器電路中只使用一個電阻。該發明所屬技術領域中具有通常知識者將明白在全部跨阻抗放大器電路中的單一電阻符號只是一個等效電阻符號,並且它可能包括多個串聯及/或並聯聯接的多個電阻。 The value of the feedback resistor in all transimpedance amplifier circuits can be any suitable value, and the values of the feedback resistors can be the same or different from each other. For example, this is possible: R 1 = R 2 = R f , R 1 = R 2 ≠ R f , R 1 ≠ R 2 ≠ R f ... and so on. Moreover, a single resistance symbol in all transimpedance amplifier circuits does not mean that only one resistor is used in the transimpedance amplifier circuit. Those of ordinary skill in the art will appreciate that a single resistance symbol in all transimpedance amplifier circuits is only one equivalent resistance symbol, and that it may include multiple resistors connected in series and/or in parallel.

需注意的是,該全差分放大電路可以額外其進一步包括一第一開關328和在該第一及第二系統輸入304、306之間一導電的迴路360。該第一開關328係選擇性地耦接該第一系統輸入304至該第一跨阻抗放大電路312的該第一電流輸入316。該導電的迴路360係包含選擇性地短路該第一及第二系統輸入304、306的一第二開關330。該第一開關以及該第二開關係交替被切換,使得該主要光偵測器302係選擇性地從該全差分放大電路被切換出。 It should be noted that the fully differential amplifier circuit may additionally include a first switch 328 and a conductive loop 360 between the first and second system inputs 304, 306. The first switch 328 selectively couples the first system input 304 to the first current input 316 of the first transimpedance amplifying circuit 312. The electrically conductive loop 360 includes a second switch 330 that selectively shorts the first and second system inputs 304, 306. The first switch and the second open relationship are alternately switched such that the primary photodetector 302 is selectively switched out of the fully differential amplifying circuit.

參考圖8,圖8是描繪一全差分放大電路的一詳細視圖。圖8和圖7的差異在於圖8中全差分放大電路的開關狀態是逆向的。 Referring to Figure 8, Figure 8 is a detailed view depicting a fully differential amplifier circuit. The difference between FIG. 8 and FIG. 7 is that the switching state of the fully differential amplifying circuit of FIG. 8 is reversed.

在一實施例中,該主要偏壓電路308可包括兩個電壓源,每一個電壓源係被配置以施加一相反的偏壓至該主要光偵測器302的一側。一個此種實施例可以見於圖9中,其中是特別參考至該陽極偏壓以及陰極偏壓。 In an embodiment, the primary biasing circuit 308 can include two voltage sources, each configured to apply an opposite bias to one side of the primary photodetector 302. One such embodiment can be seen in Figure 9, with particular reference to the anode bias and cathode bias.

參考圖10,圖10是描繪一種高溫計系統的一實施例。需注意的是,可把二個高溫計系統整合在一起,以感測不同通道(channel)的溫度。 Referring to Figure 10, Figure 10 depicts an embodiment of a pyrometer system. It should be noted that two pyrometer systems can be integrated to sense the temperature of different channels.

除了在此所述的特定實體裝置之外,在此所述的系統及方法可被實施在一電腦系統中。圖11係展示一電腦系統1100的一實施例之概略的表示,一組指令可以在該電腦系統1100之內執行,以用於使得一裝置實行或執行本揭露內容的特點及/或方法的任一或是多個。在圖11中的構件只是例子而已,而且並不限制任何實施此揭露內容的特定實施例之硬體、軟體、韌體、內嵌式邏輯構件、或是兩個或多個此種構件的一組合之使用或 功能的範疇。該些舉例說明的構件中的一些或是全部可以是該電腦系統1100的部分。譬如,該電腦系統1100可以是一般用途的電腦(例如,一膝上型電腦)或是一內嵌式邏輯裝置(例如,一FPGA),此僅舉出兩個非限制性的例子而已。 In addition to the specific physical devices described herein, the systems and methods described herein can be implemented in a computer system. 11 is a diagrammatic representation of an embodiment of a computer system 1100 that can be executed within the computer system 1100 for enabling a device to perform or perform the features and/or methods of the present disclosure. One or more. The components in FIG. 11 are merely examples and do not limit any hardware, software, firmware, embedded logic components, or one or more of such components of a particular embodiment that implements the disclosure. Combination use or The scope of function. Some or all of the illustrated components may be part of the computer system 1100. For example, the computer system 1100 can be a general purpose computer (eg, a laptop) or an embedded logic device (eg, an FPGA), to name but two non-limiting examples.

電腦系統1100係包含至少一處理器1101,例如是一中央處理單元(CPU)或是一FPGA,此係舉出兩個非限制性的例子。該電腦系統1100亦可包括一記憶體1103以及一儲存體1108,經由一匯流排1140來和彼此通訊,並且和其它構件通訊。該匯流排1140亦可以將一顯示器1132、一或多個輸入裝置1133(其例如可以包含一小型鍵盤、一鍵盤、一滑鼠、一指示筆、等等)、一或多個輸出裝置1134、一或多個儲存裝置1135、以及各種非暫態的實體的電腦可讀取的儲存媒體1136彼此連結,並且和該處理器1101、記憶體1103以及儲存體1108中的一或多個連結。這些元件的全部都可以直接或是經由一或多個介面或轉接器來介接至該匯流排1140。譬如,該各種非暫態的實體的電腦可讀取的儲存媒體1136可以經由儲存媒體介面1126來和該匯流排1140介接。電腦系統1100可以具有任何適當的實體形式,其包含但不限於一或多個積體電路(IC)、印刷電路板(PCB)、行動手持式裝置(例如行動電話或PDA)、膝上型或筆記型電腦、分散式電腦系統、網格計算、或是伺服器。 The computer system 1100 includes at least one processor 1101, such as a central processing unit (CPU) or an FPGA, to name two non-limiting examples. The computer system 1100 can also include a memory 1103 and a storage 1108 that communicate with each other via a bus 1140 and communicate with other components. The bus 1140 can also have a display 1132, one or more input devices 1133 (which can include, for example, a small keyboard, a keyboard, a mouse, a stylus, etc.), one or more output devices 1134, One or more storage devices 1135, and various non-transitory physical computer readable storage media 1136 are coupled to each other and to one or more of the processor 1101, memory 1103, and storage 1108. All of these components can be interfaced to the busbar 1140 either directly or via one or more interfaces or adapters. For example, the computer readable storage medium 1136 of the various non-transitory entities can interface with the busbar 1140 via the storage media interface 1126. Computer system 1100 can have any suitable physical form including, but not limited to, one or more integrated circuits (ICs), printed circuit boards (PCBs), mobile handheld devices (eg, mobile phones or PDAs), laptops, or Notebook, decentralized computer system, grid computing, or server.

處理器1101(或是中央處理單元(CPU))係選配地包含一快取記憶體單元1102,以用於指令、資料、或是電腦位址之暫時的本地儲存。處理器1101係被配置以協助儲存在至少一非暫態的實體的電腦可讀取的儲存媒體上的電腦可讀取的指令的執行。電腦系統1100可以提供由於該處理 器1101執行在一或多個例如是記憶體1103、儲存體1108、儲存裝置1135及/或儲存媒體1136(例如,唯讀記憶體(ROM))之非暫態的實體的電腦可讀取的儲存媒體中被體現的軟體所得到的功能。該非暫態的實體的電腦可讀取的儲存媒體可以儲存實施例如是在此揭露的方法的特定實施例之軟體,並且處理器1101可以執行該軟體。記憶體1103可以從一或多個其它非暫態的實體的電腦可讀取的儲存媒體(例如大量儲存裝置1135、1136)、或是透過一例如是網路介面1120之適當的介面而從一或多個其它來源以讀取該軟體。該軟體可以使得處理器1101實行在此敘述或描繪的一或多種方法、或是一或多種方法的一或多個步驟。實行此種方法或步驟可包含定義被儲存在記憶體1103中的資料結構,並且按照該軟體所指示地修改該資料結構。在某些實施例中,一FPGA可以儲存用於實行如同在此揭露內容中所述的功能的指令。在其它實施例中,韌體係包含用於實行如同在此揭露內容中所述的功能的指令。 The processor 1101 (or central processing unit (CPU)) optionally includes a cache memory unit 1102 for temporary local storage of instructions, data, or computer addresses. The processor 1101 is configured to facilitate execution of computer readable instructions stored on a computer readable storage medium of at least one non-transitory entity. Computer system 1100 can provide due to this processing The processor 1101 performs computer readable reading of one or more non-transitory entities such as the memory 1103, the storage 1108, the storage device 1135, and/or the storage medium 1136 (eg, read only memory (ROM)) The function of the software embodied in the storage medium. The computer readable storage medium of the non-transitory entity can store software that implements a particular embodiment, such as the methods disclosed herein, and the processor 1101 can execute the software. The memory 1103 can be from a computer readable storage medium (eg, mass storage devices 1135, 1136) of one or more other non-transitory entities, or from a suitable interface such as the network interface 1120. Or multiple other sources to read the software. The software may cause processor 1101 to perform one or more methods described herein or depicted, or one or more steps of one or more methods. Performing such a method or step can include defining a data structure stored in memory 1103 and modifying the data structure as directed by the software. In some embodiments, an FPGA may store instructions for performing the functions as described in the disclosure herein. In other embodiments, the tough system includes instructions for performing the functions as described in the disclosure herein.

該記憶體1103可包含各種的構件(例如,非暫態的實體的電腦可讀取的儲存媒體),其包含但不限於一隨機存取記憶體構件(例如,RAM 1104)(例如,一靜態RAM"SRAM"、一動態RAM"DRAM"、等等)、一唯讀構件(例如,ROM 1105)、以及其之任意組合。ROM 1105可以作用以單向地通訊資料及指令至處理器1101,並且RAM 1104可以作用以雙向地和處理器1101通訊資料及指令。ROM 1105以及RAM 1104可包含在以下所述的任何適當的非暫態的實體的電腦可讀取的儲存媒體。在某些實例中,ROM 1105以及RAM 1104係包含用於實行在此揭露的方法之非暫態的實體的電腦可讀取的儲存媒體。在一例子中,一基本輸入/輸出系統1106(BIOS)可被儲存 在該記憶體1103中,其係包含有助於例如是在開機期間,在電腦系統1100內的元件之間傳輸資訊之基本的常式。 The memory 1103 can include various components (eg, a non-transitory physical computer readable storage medium) including, but not limited to, a random access memory component (eg, RAM 1104) (eg, a static RAM "SRAM", a dynamic RAM "DRAM", etc.), a read-only component (eg, ROM 1105), and any combination thereof. ROM 1105 can function to communicate data and instructions unidirectionally to processor 1101, and RAM 1104 can function to communicate data and instructions to processor 1101 in both directions. ROM 1105 and RAM 1104 can comprise any suitable non-transitory physical computer readable storage medium as described below. In some examples, ROM 1105 and RAM 1104 are computer readable storage media containing entities for performing non-transitory methods of the methods disclosed herein. In an example, a basic input/output system 1106 (BIOS) can be stored In the memory 1103, it includes a basic routine that facilitates, for example, transferring information between components within the computer system 1100 during startup.

固定的儲存體1108係雙向地連接至處理器1101,其選配的是透過儲存體控制單元1107。固定的儲存體1108係提供額外的資料儲存容量,並且亦可包含任何在此所述之適當的非暫態的實體的電腦可讀取的媒體。儲存體1108可被用來儲存作業系統1109、EXEC 1110(執行檔)、資料1111、API應用程式1112(應用程式)、與類似者。通常(儘管並非總是),儲存體1108是一次要的儲存媒體(例如一硬碟),其係比主要儲存體(例如,記憶體1103)慢。儲存體1108亦可包含一光碟機、一固態記憶體裝置(例如,快閃為基礎的系統)、或是以上的任一者的一組合。在適當的情形中,在儲存體1108中的資訊可被納入作為在記憶體1103中之虛擬的記憶體。 The fixed storage 1108 is bidirectionally coupled to the processor 1101, which is optionally permeable to the storage control unit 1107. The fixed storage 1108 provides additional data storage capacity and may also include any suitable non-transitory physical computer readable media as described herein. The storage 1108 can be used to store the operating system 1109, EXEC 1110 (executive file), data 1111, API application 1112 (application), and the like. Typically (although not always), the storage 1108 is a primary storage medium (e.g., a hard disk) that is slower than the primary storage (e.g., memory 1103). The storage 1108 can also include a compact disc drive, a solid state memory device (e.g., a flash-based system), or a combination of any of the above. In the appropriate case, the information in the storage 1108 can be incorporated as a virtual memory in the memory 1103.

在一例子中,儲存裝置1135可以是經由一儲存裝置介面1125而可移除地與電腦系統1100介接(例如,經由一外部的埠連接器(未顯示))。尤其,儲存裝置1135以及一相關的機器可讀取的媒體可以提供用於該電腦系統1100之機器可讀取的指令、資料結構、程式模組及/或其它資料的非揮發性及/或揮發性的儲存。在一例子中,軟體可以完全或是部分地存在於儲存裝置1135上之一機器可讀取的媒體內。在另一例子中,軟體可以完全或是部分地存在於處理器1101內。 In one example, storage device 1135 can be removably interfaced with computer system 1100 via a storage device interface 1125 (eg, via an external port connector (not shown)). In particular, the storage device 1135 and an associated machine readable medium can provide non-volatile and/or volatile information for machine readable instructions, data structures, program modules, and/or other materials for the computer system 1100. Sexual storage. In one example, the software may reside entirely or partially within one of the machine readable media on storage device 1135. In another example, the software may reside entirely or partially within the processor 1101.

匯流排1140係連接廣泛多樣的子系統。在此,對於一匯流排的參照可以涵蓋一或多個在適當情況下作用為一共同的功能之數位信號線。匯流排1140可以是數種類型的匯流排結構的任一種,其包含但不限於一記憶體匯流排、一記憶體控制器、一週邊匯流排、一本地匯流排以及其 之任意組合,其係利用各種匯流排架構的任一種。作為一例子而且非限制性的,此種架構係包含一工業標準架構(ISA)匯流排、一強化的ISA(EISA)匯流排、一微通道架構(MCA)匯流排、一視訊電子標準協會本地匯流排(VLB)、一週邊元件互連(PCI)匯流排、一PCI-Express(PCI-X)匯流排、一加速繪圖埠(AGP)匯流排、超傳輸(HTX)匯流排、串列進階技術連接(SATA)匯流排、以及其之任意組合。 The busbar 1140 is connected to a wide variety of subsystems. Here, reference to a bus bar may encompass one or more digital signal lines that function as a common function where appropriate. The bus bar 1140 can be any one of several types of bus bar structures, including but not limited to a memory bus, a memory controller, a peripheral bus, a local bus, and Any combination of these utilizes any of a variety of bus bar architectures. As an example and not by way of limitation, such an architecture includes an industry standard architecture (ISA) bus, a enhanced ISA (EISA) bus, a micro channel architecture (MCA) bus, and a video electronic standards association local. Busbar (VLB), a peripheral component interconnect (PCI) bus, a PCI-Express (PCI-X) bus, an accelerated graphics (AGP) bus, a hyper-transport (HTX) bus, and a serial A technology connection (SATA) bus, and any combination thereof.

電腦系統1100亦可包含一輸入裝置1133。在一例子中,電腦系統1100的使用者可以經由輸入裝置1133來輸入命令及/或其它資訊到電腦系統1100中。一輸入裝置1133的例子係包含但不限於一字母數字的輸入裝置(例如,一鍵盤)、一指向裝置(例如,一滑鼠或觸控板)、一觸控板、一搖桿、一遊戲手把、一音訊輸入裝置(例如,一麥克風、一語音響應系統、等等)、一光學掃描器、一視訊或靜止影像的捕捉裝置(例如,一相機)、以及其之任意組合。輸入裝置1133可以經由各種輸入介面1123的任一種(例如,輸入介面1123)來介接至匯流排1140,該輸入介面1123係包含但不限於串列、並列、遊戲埠、USB、FIREWIRE、THUNDERBOLT、或是以上的任意組合。 Computer system 1100 can also include an input device 1133. In one example, a user of computer system 1100 can enter commands and/or other information into computer system 1100 via input device 1133. An example of an input device 1133 includes, but is not limited to, an alphanumeric input device (eg, a keyboard), a pointing device (eg, a mouse or trackpad), a trackpad, a joystick, a game A handle, an audio input device (eg, a microphone, a voice response system, etc.), an optical scanner, a video or still image capture device (eg, a camera), and any combination thereof. The input device 1133 can be interfaced to the bus bar 1140 via any of the various input interfaces 1123 (eg, the input interface 1123), including but not limited to tandem, parallel, gaming, USB, FIREWIRE, THUNDERBOLT, Or any combination of the above.

在特定的實施例中,當電腦系統1100連接至網路1130時,電腦系統1100可以和例如是行動裝置以及企業系統的其它連接至網路1130的裝置通訊。往返於電腦系統1100的通訊可以透過網路介面1120而被傳送。例如,網路介面1120可以從網路1130接收具有一或多個封包(例如是網際網路協定(IP)封包)的形式之進入的通訊(例如是來自其它裝置的請求或響應),並且電腦系統1100可以將該進入的通訊儲存在記憶體1103中以用 於處理。電腦系統1100可以類似地儲存具有一或多個封包的形式之向外的通訊(例如是對於其它裝置的請求或響應)在記憶體1103中,並且從網路介面1120來傳遞至網路1130。處理器1101可以存取被儲存在記憶體1103中的這些通訊封包以用於處理。 In a particular embodiment, when computer system 1100 is connected to network 1130, computer system 1100 can communicate with, for example, mobile devices and other devices of the enterprise system that are connected to network 1130. Communication to and from the computer system 1100 can be transmitted through the network interface 1120. For example, the network interface 1120 can receive incoming communications (eg, requests or responses from other devices) in the form of one or more packets (eg, Internet Protocol (IP) packets) from the network 1130, and the computer The system 1100 can store the incoming communication in the memory 1103 for use. For processing. Computer system 1100 can similarly store outgoing communications (eg, requests or responses to other devices) in the form of one or more packets in memory 1103 and from network interface 1120 to network 1130. The processor 1101 can access the communication packets stored in the memory 1103 for processing.

該網路介面1120的例子係包含但不限於一網路介面卡、一數據機、以及其之任意組合。一網路1130或是網路區段1130的例子係包含但不限於一廣域網路(WAN)(例如,網際網路、一企業網路)、一本地區域網路(LAN)(例如,和一辦公室、一建築物、一校園或是其它相當小的地理空間相關的一網路)、一電話網路,一在兩個計算裝置之間的直接連線、以及其之任意組合。一例如是網路1130的網路可以利用一有線模式及/或一無線模式的通訊。一般而言,任何的網路拓撲都可被使用。 Examples of the network interface 1120 include, but are not limited to, a network interface card, a data machine, and any combination thereof. An example of a network 1130 or network segment 1130 includes, but is not limited to, a wide area network (WAN) (eg, an internet, a corporate network), a local area network (LAN) (eg, and one) An office, a building, a campus or other network associated with a relatively small geographic space, a telephone network, a direct connection between two computing devices, and any combination thereof. For example, the network of the network 1130 can utilize a wired mode and/or a wireless mode of communication. In general, any network topology can be used.

資訊及資料可以透過一顯示器1132而被顯示。一顯示器1132的例子係包含但不限於一液晶顯示器(LCD)、一有機液晶顯示器(OLED)、一陰極射線管(CRT)、一電漿顯示器、以及其之任意組合。該顯示器1132可以經由匯流排1140來介接至該處理器1101、記憶體1103及固定的儲存體1108、以及例如是輸入裝置1133的其它裝置。該顯示器1132係經由一視訊介面1122而被連結至該匯流排1140,並且在該顯示器1132與匯流排1140之間的資料傳輸可以經由該繪圖控制1121來加以控制。 Information and materials can be displayed via a display 1132. An example of a display 1132 includes, but is not limited to, a liquid crystal display (LCD), an organic liquid crystal display (OLED), a cathode ray tube (CRT), a plasma display, and any combination thereof. The display 1132 can be interfaced to the processor 1101, the memory 1103 and the fixed storage 1108, and other devices such as the input device 1133 via the bus 1140. The display 1132 is coupled to the busbar 1140 via a video interface 1122, and data transfer between the display 1132 and the busbar 1140 can be controlled via the mapping control 1121.

除了一顯示器1132之外,電腦系統1100可包含一或多個其它週邊輸出裝置1134,其係包含但不限於一音訊揚聲器、一印表機、以及其之任意組合。此種週邊輸出裝置可以經由一輸出介面1124來連接至該匯流排1140。一輸出介面1124的例子係包含但不限於一串列埠,一並列的連 線、一USB埠、一FIREWIRE埠、一THUNDERBOLT埠、以及其之任意組合。 In addition to a display 1132, computer system 1100 can include one or more other peripheral output devices 1134, including but not limited to an audio speaker, a printer, and any combination thereof. Such a peripheral output device can be coupled to the busbar 1140 via an output interface 1124. An example of an output interface 1124 includes, but is not limited to, a series of columns, a parallel connection Line, a USB port, a FIREWIRE port, a THUNDERBOLT port, and any combination thereof.

額外或作為一替代方案的是,電腦系統1100可以提供由於固線線路邏輯或是其它方式被體現在一電路中所得的功能,其可以運作來取代軟體、或是和軟體一起以執行在此敘述或描繪的一或多種方法、或是一或多種方法的一或多個步驟。在此揭露內容中對於軟體的參照可以涵蓋邏輯,並且對於邏輯的參照可以涵蓋軟體。再者。對於一非暫態的實體的電腦可讀取的媒體的參照在適當情況下可以涵蓋一儲存用於執行的軟體之電路(例如一IC)、一體現用於執行的邏輯之電路、或是兩者。譬如,一非暫態的實體的電腦可讀取的媒體可以涵蓋一或多個FPGA、固定的邏輯、類比邏輯、或是以上的某種組合。本揭露內容係包含硬體、軟體、或是兩者的任意適當的組合。 Additionally or alternatively, computer system 1100 can provide functionality that is embodied in a circuit due to fixed line logic or other means that can operate in place of software or in conjunction with software to perform the description herein. Or one or more methods depicted, or one or more steps of one or more methods. References to software in this disclosure may encompass logic, and references to logic may encompass software. Again. A reference to a computer readable medium of a non-transitory entity may, where appropriate, include a circuit for storing software for execution (eg, an IC), a circuit embodying logic for execution, or two By. For example, a non-transitory entity's computer readable medium can cover one or more FPGAs, fixed logic, analog logic, or some combination of the above. The disclosure includes hardware, software, or any suitable combination of the two.

具有此項技術中的技能者將會理解到資訊及信號可以利用各種不同的科技及技術的任一種來加以表示。例如,在整個以上的說明中可能參照到的資料、指令、命令、資訊、信號、位元、符號、以及晶片可以藉由電壓、電流、電磁波、磁場或磁性微粒、光場或光學微粒、或是其之任意組合來加以表示。 Those skilled in the art will appreciate that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and wafers that may be referenced throughout the above description may be by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or It is any combination of them to represent.

在此說明書內,相同的元件符號係被用來指出端子、信號線、導線、等等以及其對應的信號。就此點而言,該些術語"信號"、"導線"、"連線"、"端子"以及"接腳"在此說明書內可以偶爾交換地被使用。亦應該體認到該些術語"信號"、"導線"或類似者可以代表一或多個信號,例如是單一位元透過單一導線的運載、或是多個平行的位元透過多個平行的導線的運 載。再者,每一個導線或信號可以代表在兩個或更多個藉由一根據具體情況而定的信號或導線連接的構件之間的雙向的通訊。 Throughout the specification, the same element symbols are used to indicate terminals, signal lines, wires, and the like, and their corresponding signals. In this regard, the terms "signal", "wire", "wire", "terminal" and "pin" are used interchangeably in this specification. It should also be recognized that the terms "signal", "wire" or the like may represent one or more signals, such as a single bit carried through a single wire, or multiple parallel bits passing through multiple parallel Wire transport Loaded. Furthermore, each wire or signal can represent two-way communication between two or more components connected by a context-specific signal or wire.

具有技能者將會進一步體認到關連到在此揭露的實施例所敘述之各種舉例說明的邏輯區塊、模組、電路、以及演算法步驟可被實施為電子硬體、電腦軟體、或是兩者的組合。為了清楚地描繪硬體及軟體的此種可互換性,各種舉例說明的構件、區塊、模組、電路、以及步驟已經在以上大致就其功能方面來加以敘述。此種功能被實施為硬體或軟體是依據特定的應用以及被施加在該整體系統上的設計限制而定。本領域技術人員可以為了每個特定的應用而用變化的方式來實施所述的功能,但是此種實施方式的決策不應該被解釋為造成脫離本發明的範疇。 Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. The implementation of such functionality as hardware or software is dependent upon the particular application and design constraints imposed on the overall system. A person skilled in the art can implement the described functions in varying ways for each particular application, but the decision of such an embodiment should not be construed as causing a departure from the scope of the invention.

關連到在此揭露的實施例所述之各種舉例說明的邏輯區塊、模組以及電路可以利用被設計以執行在此所述的功能之一般用途的處理器、一數位信號處理器(DSP)、一特殊應用積體電路(ASIC)、一現場可程式化的閘陣列(FPGA)或其它可程式化的邏輯裝置、離散的閘或電晶體邏輯、離散的硬體構件、或是其之任意組合來加以實施或執行。一般用途的處理器可以是一微處理器,但是在替代方案中,該處理器可以是任意習知的處理器、控制器、或是微控制器。一處理器亦可被實施為計算裝置的一組合,例如是一DSP以及一微處理器的一組合、複數個微處理器、一或多個結合一DSP核心的微處理器、或是任何其它此種配置。 The various illustrated logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may utilize a processor, a digital signal processor (DSP), designed to perform the general purposes of the functions described herein. , a special application integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any of them Combine to implement or execute. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, or microcontroller. A processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other This configuration.

關連到在此揭露的實施例所述的一種方法或演算法的步驟可以直接用硬體、用藉由一處理器所執行的一軟體模組、一被實施為數位邏輯裝置的軟體模組、或是用這些的一組合來加以體現。一軟體模組可以 存在於RAM記憶體、快閃記憶體、ROM記憶體、EPROM記憶體、EEPROM記憶體、暫存器、硬碟、一可移除的碟片、一CD-ROM、或是此項技術中已知的任何其它形式之非暫態的實體的電腦可讀取的儲存媒體中。一範例的非暫態的實體的電腦可讀取的儲存媒體係耦接至該處理器,使得該處理器可以從該非暫態的實體的電腦可讀取的儲存媒體讀取資訊,並且寫入資訊至其。在替代方案中,該非暫態的實體的電腦可讀取的儲存媒體可以是與該處理器為一體的。該處理器以及非暫態的實體的電腦可讀取的儲存媒體可以存在於一ASIC中。該ASIC可以存在於一使用者終端中。在替代方案中,該處理器以及非暫態的實體的電腦可讀取的儲存媒體可以在一使用者終端中以離散的構件存在。在某些實施例中,一軟體模組可被實施為數位邏輯構件,例如是在一旦被程式化該軟體模組後的FPGA中的那些數位邏輯構件。 The steps of a method or algorithm described in connection with the embodiments disclosed herein may be directly implemented by hardware, by a software module executed by a processor, by a software module implemented as a digital logic device, Or use a combination of these to reflect. a software module can Exist in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, scratchpad, hard disk, a removable disc, a CD-ROM, or this technology Known in any other form of non-transitory entity in a computer readable storage medium. An exemplary non-transitory physical computer readable storage medium is coupled to the processor such that the processor can read information from the non-transitory entity's computer readable storage medium and write Information to it. In the alternative, the computer readable storage medium of the non-transitory entity may be integral to the processor. The processor and the non-transitory physical computer readable storage medium may reside in an ASIC. The ASIC can reside in a user terminal. In the alternative, the processor and the computer readable storage medium of the non-transitory entity may exist as discrete components in a user terminal. In some embodiments, a software module can be implemented as a digital logic component, such as those in an FPGA once the software module is programmed.

所揭露的實施例之先前的說明係被提供以使得任何熟習此項技術者能夠完成或利用本發明。各種對於這些實施例的修改對於熟習此項技術者而言將會是相當明顯的,並且在此界定的一般原理可被應用到其它實施例,而不脫離本發明的精神或範疇。因此,本發明並不欲受限於在此所示的實施例,但是欲被授予和在此揭露的原理及新穎的特點一致的最廣範疇。 The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments are obvious to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but the scope of the invention is to be

Claims (16)

一種用於在一高溫計中放大一光學信號之高速、高信號對雜訊、高增益、並且高動態範圍的全差分放大電路,該全差分放大電路係包括:一第一系統輸入(304),其係被配置以用於耦接至一主要光偵測器(302)的一陽極;一第二系統輸入(306),其係被配置以用於耦接至該主要光偵測器(302)的一陰極,其中,當該第一及第二系統輸入(304、306)耦接至該主要光偵測器(302)時,一光電流ip係在該第二及第一系統輸入(306、304)之間通過;一跨阻抗差分放大器級,其係包括:一主要偏壓電路(308),其係被配置以將該主要光偵測器(302)偏壓在0V到一逆向偏壓之間,並且具有第一及第二輸出(328、330);一第一跨阻抗放大電路(312),其係具有一第一電流輸入(316)以及一第一跨阻抗電壓輸出(314),其中:該第一電流輸入(316)係耦接至該第一系統輸入(304),一第一偏壓電壓輸入(318)係耦接至該主要偏壓電路(308)的該第一輸出(328),以及在該第一電壓跨阻抗輸出(314)處的一第一電壓係與該光電流ip成比例;以及一第二跨阻抗放大電路(320),其係具有一第二電流輸入(324)以及一第二跨阻抗電壓輸出(322),其中:該第二電流輸入(324)係耦接至該第二系統輸入(306), 一第二偏壓電壓輸入(326)係耦接至該主要偏壓電路(308)的該第二輸出(330),以及在該第二電壓跨阻抗輸出(322)處的一第二電壓係與在該第二及第一系統輸入(306、304)之間通過的該光電流ip成比例;其中該主要偏壓電路(308)係耦接至該第一及第二跨阻抗放大電路(312、320),以使得一0V到一逆向偏壓存在於橫跨該主要光偵測器(302);以及一主要差分輸出v1係被配置以用於在一處理器(210)中轉換成為一溫度或反射係數值。 A high-speed, high-signal-to-noise, high-gain, and high dynamic range fully differential amplifying circuit for amplifying an optical signal in a pyrometer, the fully differential amplifying circuit comprising: a first system input (304) Is configured to be coupled to an anode of a primary photodetector (302); a second system input (306) configured to be coupled to the primary photodetector ( 302) is a cathode, wherein, when the first and second system input (304, 306) coupled to the main photodetector (302), the current i p a light-based system in the first and second Passing between inputs (306, 304); a transimpedance differential amplifier stage comprising: a primary bias circuit (308) configured to bias the primary photodetector (302) at 0V Between a reverse bias and having first and second outputs (328, 330); a first transimpedance amplifying circuit (312) having a first current input (316) and a first transimpedance a voltage output (314), wherein: the first current input (316) is coupled to the first system input (304), and a first bias voltage input (318) is coupled A bias circuit connected to the primary (308) the first output (328), the transimpedance and the first output voltage (314) a first voltage line and a current i p of the light at the proportional; and a The second transimpedance amplifying circuit (320) has a second current input (324) and a second transimpedance voltage output (322), wherein the second current input (324) is coupled to the second a system input (306), a second bias voltage input (326) coupled to the second output (330) of the primary bias circuit (308), and a second voltage transimpedance output (322) a second voltage system is proportional to the photocurrent i p passing between the second and first system inputs (306, 304); wherein the primary bias circuit (308) is coupled to the first and a second transimpedance amplifying circuit (312, 320), so that a reverse bias voltage to a 0V across present in the main photodetector (302); and a differential output v 1 major system configured for Converted into a temperature or reflection coefficient value in a processor (210). 如申請專利範圍第1項之全差分放大電路,其進一步包括兩個或多個差分電壓放大器級(430、432),其分別包括兩個並聯配置的差分電壓放大器,該兩個或多個差分電壓放大器級的每一個係具有一差分電壓輸出v2、v3A fully differential amplifying circuit as claimed in claim 1, further comprising two or more differential voltage amplifier stages (430, 432) each comprising two differential voltage amplifiers arranged in parallel, the two or more differentials Each of the voltage amplifier stages has a differential voltage output v 2 , v 3 . 如申請專利範圍第2項之全差分放大電路,其中在該兩個或多個差分電壓放大器級中之一者(430)內的該兩個差分電壓放大器的每一個係耦接至該跨阻抗差分放大器級(350)的該差分輸出。 A fully differential amplifying circuit as claimed in claim 2, wherein each of the two differential voltage amplifiers in one of the two or more differential voltage amplifier stages (430) is coupled to the transimpedance This differential output of the differential amplifier stage (350). 如申請專利範圍第3項之全差分放大電路,其中該跨阻抗差分放大器級(350)的該差分輸出的一接腳係耦接至在該兩個或多個差分電壓放大器級中之該一者(430)內的該兩個差分電壓放大器中之一的一反相輸入、以及在該兩個或多個差分電壓放大器級中之該一者(430)內的該兩個差分電壓放大器的另一個的一非反相輸入,藉此產生其輸入未被反相的一對差分放大器的增益的兩倍。 The full differential amplifier circuit of claim 3, wherein a pin of the differential output of the transimpedance differential amplifier stage (350) is coupled to the one of the two or more differential voltage amplifier stages An inverting input of one of the two differential voltage amplifiers (430), and the two differential voltage amplifiers in the one of the two or more differential voltage amplifier stages (430) The other is a non-inverting input, thereby generating twice the gain of a pair of differential amplifiers whose inputs are not inverted. 如申請專利範圍第2項之全差分放大電路,其中該兩個或多個差分電壓放大器級(430、432)具有不同的增益。 A fully differential amplifier circuit as in claim 2, wherein the two or more differential voltage amplifier stages (430, 432) have different gains. 如申請專利範圍第5項之全差分放大電路,其中該兩個或多個差分電壓放大器級(430、432)係被配置以用於耦接至具有一軟體選擇器(208)的該處理器(210),該軟體選擇器(208)係被配置以用於在該兩個或多個差分電壓放大器級(430、432)的輸出之間做選擇,使得放大增益的選擇可以在資料收集期間加以執行,而不使用一機械式開關,並且因此資料串流不需進行接縫。 A fully differential amplifier circuit as in claim 5, wherein the two or more differential voltage amplifier stages (430, 432) are configured for coupling to the processor having a software selector (208) (210), the software selector (208) is configured to select between outputs of the two or more differential voltage amplifier stages (430, 432) such that selection of amplification gain can be during data collection It is executed without using a mechanical switch, and therefore the data stream does not need to be seamed. 如申請專利範圍第1項之全差分放大電路,其進一步包括一盲級,該盲級係包括:一盲光偵測器,其係與該主要光偵測器所看到的大多數的光子放射隔離開,但是在結構上與該主要光偵測器相同;一盲偏壓電路,其係耦接至一第三跨阻抗放大器電路(512)以及一第四跨阻抗放大器電路(520)的電壓輸入(518、526),並且被配置以利用與橫跨該主要光偵測器(302)的該偏壓等同大小的偏壓來對該盲光偵測器(502)進行偏壓,其中該盲光偵測器係代表該主要光偵測器(302)的一漏電流;以及一盲差分輸出v4,其係被配置以用於從該主要差分輸出v1中予以減去。 The full differential amplification circuit of claim 1, further comprising a blind stage, the blind stage comprising: a blind light detector, which is associated with most of the photons seen by the primary light detector Radiation isolation, but identical in structure to the primary photodetector; a blind bias circuit coupled to a third transimpedance amplifier circuit (512) and a fourth transimpedance amplifier circuit (520) a voltage input (518, 526) and configured to bias the blind photodetector (502) with a bias equal to the magnitude of the bias across the primary photodetector (302), wherein the photodetector blind system on behalf of the main photodetector (302) is a leakage current; and a blind differential output v 4, which system is to be configured for the primary differential output from subtracting v 1. 如申請專利範圍第7項之全差分放大電路,其進一步包括一對比較器(554、556),每一個比較器係具有一對輸入並且耦接至該主要差分電壓輸出v1以及該盲差分電壓輸出v4,該些比較器(554、556)係具有極性以使得該對比較器(554、556)的一差分輸出v5係等於在該主要差分輸出v1與該盲差分輸出v4之間的一差值。 A fully differential amplifying circuit as in claim 7 further comprising a pair of comparators (554, 556) each having a pair of inputs coupled to the primary differential voltage output v 1 and the blind differential a voltage output v 4 , the comparators (554, 556) having a polarity such that a differential output v 5 of the pair of comparators (554, 556) is equal to the primary differential output v 1 and the blind differential output v 4 A difference between. 如申請專利範圍第1項之全差分放大電路,其進一步包括:一第一開關(328),其係選擇性地耦接該第一系統輸入(304)至該第一跨阻抗放大電路(312)的該第一電流輸入(316);以及一導電的迴路(360),其係在該第一及第二系統輸入(304、306)之間,該導電的迴路(360)係包含選擇性地短路該第一及第二系統輸入(304、306)的一第二開關(330),其中該第一開關以及該第二開關係交替被切換,使得該主要光偵測器(302)係選擇性地從該全差分放大電路被切換出,藉此容許漏電流的校正能夠在該主要光偵測器(302)不存在時加以執行。 The fully differential amplifying circuit of claim 1, further comprising: a first switch (328) selectively coupling the first system input (304) to the first transimpedance amplifying circuit (312) The first current input (316); and a conductive loop (360) between the first and second system inputs (304, 306), the conductive loop (360) comprising a selectivity Grounding a second switch (330) of the first and second system inputs (304, 306), wherein the first switch and the second open relationship are alternately switched such that the primary photodetector (302) is The full differential amplification circuit is selectively switched out, whereby the correction of the allowable leakage current can be performed when the primary photodetector (302) is not present. 一種高溫計系統,其係包括:一主要光偵測器(201);一雙差分放大電路(202),其係包括一對跨阻抗放大器,該對跨阻抗放大器係耦接至該主要光偵測器(201),並且具有與該主要光偵測器(201)所產生的光電流ip成比例之兩個差分電壓輸出(212、214),但是具有不同的增益;一第一類比至數位轉換器(204),其係耦接至該兩個差分電壓輸出(212)的一第一差分電壓輸出,並且被配置以轉換一第一差分電壓輸出(212)成為一對應的數位值,並且具有提供該對應的數位值至一處理器(210)的一第一數位輸出(216);一第二類比至數位轉換器(206),其係耦接至該兩個差分電壓輸出(204)的一第二差分電壓輸出,並且被配置以轉換一第二差分電壓輸出(214)成為一對應的數位值,並且具有提供該對應的數位值至該處理器(210)的一第二數位輸出(218);以及 該處理器(210),其係耦接至該第一及第二數位輸出(216、218),且具有一選擇器(208),該選擇器(208)係耦接至該第一及第二數位輸出(216、218)並且被配置以選擇該第一及第二數位輸出(216、218)中的哪一個將藉由該處理器加以處理,該處理器(210)係被配置以轉換該第一及第二數位輸出(216、218)的一所選者成為一溫度或是反射係數值,並且具有提供該溫度或是反射係數值的一輸出(220)。 A pyrometer system comprising: a primary photodetector (201); a dual differential amplifier circuit (202) comprising a pair of transimpedance amplifiers coupled to the main optical detector detector (201), and having a photocurrent i proportional to the differential voltage of the two p outputs (212, 214) generated by the main photodetector (201), but with different gain; a first analog-to a digital converter (204) coupled to a first differential voltage output of the two differential voltage outputs (212) and configured to convert a first differential voltage output (212) to a corresponding digital value, And having a first digital output (216) providing the corresponding digital value to a processor (210); a second analog to digital converter (206) coupled to the two differential voltage outputs (204) a second differential voltage output, and configured to convert a second differential voltage output (214) to a corresponding digit value, and having a second digit providing the corresponding digit value to the processor (210) An output (218); and the processor (210) coupled to the first a binary output (216, 218) having a selector (208) coupled to the first and second digital outputs (216, 218) and configured to select the first Which of the second digit outputs (216, 218) will be processed by the processor, the processor (210) being configured to convert a selected one of the first and second digit outputs (216, 218) The person becomes a temperature or reflection coefficient value and has an output (220) that provides the temperature or the value of the reflection coefficient. 如申請專利範圍第10項之高溫計系統,其中該雙差分放大電路(202)係包含一主要偏壓電路,其係被配置以在該主要光偵測器201上造成一偏壓,其中該偏壓的範圍可以是從0V到一逆向偏壓。 A pyrometer system according to claim 10, wherein the dual differential amplifier circuit (202) includes a primary bias circuit configured to cause a bias voltage on the primary photodetector 201, wherein The bias can range from 0V to a reverse bias. 一種操作一全差分雙放大電路之方法,該方法係包括:接收一光電流ip,該光電流ip通過一主要光偵測器至一差分跨阻抗差分放大器級(350),其係包括並聯配置的一第一對跨阻抗放大電路(312、320);經由該差分跨阻抗差分放大器級(350)以轉換該光電流ip成為一差分輸出電壓v1;提供該第一差分輸出電壓v1至一對並聯配置的差分電壓放大器級(430、432),藉此轉換該第一差分輸出電壓v1成為一對具有不同增益的第二及第三差分輸出電壓v2及v3;經由一對類比至數位轉換器(204、206)以提供該第二及第三對差分輸出電壓v2及v3至一處理器;選擇該第二及第三差分輸出電壓v2及v3中之一,以用於在無機械式開關下進行處理;轉換該第二及第三差分輸出電壓v2及v3中之一所選者成為一溫度或是 反射係數值。 A method of operating a dual fully-differential amplification method circuits, which system comprises: a light-receiving current i p, i p of the photocurrent by a photodetector to a primary differential transimpedance differential amplifier stage (350), which system comprises the transimpedance amplifying circuit (312,320) a first pair of parallel configuration; differential transimpedance via the differential amplifier stage (350) to convert the light into a current i p differential output voltage v 1; providing the first differential output voltage v 1 to a pair of differential voltage amplifier stages (430, 432) arranged in parallel, thereby converting the first differential output voltage v 1 into a pair of second and third differential output voltages v 2 and v 3 having different gains; Providing the second and third pairs of differential output voltages v 2 and v 3 to a processor via a pair of analog to digital converters (204, 206); selecting the second and third differential output voltages v 2 and v 3 One of them is used for processing without a mechanical switch; converting one of the second and third differential output voltages v 2 and v 3 to a temperature or a reflection coefficient value. 如申請專利範圍第12項之方法,其進一步包括:接收一暗偏移電流id,該暗偏移電流id通過一盲光偵測器至一盲級(350),該盲級(350)係包括並聯配置的一第二對跨阻抗放大電路(512、520);經由該差分跨阻抗差分放大器級(350)以轉換該暗偏移電流id成為一第四差分輸出電壓v4,該盲光偵測器係代表在該主要光偵測器中的一漏電流;從該第一差分輸出電壓v1減去該第四差分輸出電壓v4,以形成一第五差分輸出電壓v5;並且提供該第五差分輸出電壓v5至該對差分電壓放大器級(430、432);轉換該第五差分輸出電壓v5成為該第二及第三差分輸出電壓v2及v3;以及轉換該第二及第三差分輸出電壓v2及v3中之一所選者成為一溫度或是反射係數值,該減去係利用該暗偏移電流id以考量在該主要光偵測器中的漏電流。 The method of claim 12, further comprising: receiving a dark offset current i d , the blind offset current i d passing through a blind photodetector to a blind stage (350), the blind stage (350) a second pair of transimpedance amplifying circuits (512, 520) arranged in parallel; via the differential transimpedance differential amplifier stage (350) to convert the dark offset current i d into a fourth differential output voltage v 4 , The blind light detector represents a leakage current in the primary photodetector; the fourth differential output voltage v 4 is subtracted from the first differential output voltage v 1 to form a fifth differential output voltage v 5; and providing the differential output voltage V to the 5 V voltage for the differential amplifier stage (430, 432); converting the fifth differential output voltage V 5 becomes the second and third differential output voltage v 2 and v 3; And converting one of the second and third differential output voltages v 2 and v 3 to a temperature or a reflection coefficient value, the subtracting system utilizing the dark offset current i d to consider the primary optical detection Leakage current in the detector. 如申請專利範圍第12項之方法,其進一步包括:從該全差分雙放大電路選擇性地移除該主要光偵測器以及該盲光偵測器;在無該主要光偵測器的影響下決定在該全差分雙放大電路中的偏移電流;以及從主要光電流ip減去該偏移電流,該主要光電流ip係根據該第二或第三差分輸出電壓v2及v3中之該所選者而決定的,該減去係發生在該處理器中。 The method of claim 12, further comprising: selectively removing the primary photodetector and the blind photodetector from the fully differential dual amplifying circuit; without the influence of the primary photodetector Determining an offset current in the fully differential dual amplifying circuit; and subtracting the offset current from the primary photocurrent i p , the primary photocurrent i p being based on the second or third differential output voltage v 2 and v The subtraction is determined by the selector in 3 , and the subtraction occurs in the processor. 如申請專利範圍第12項之方法,其進一步包括:利用在包含0V與 包含一逆向偏壓之間的一主要偏壓來偏壓該主要光偵測器,並且利用和該主要偏壓的大小相同但是極性相反之一盲偏壓來偏壓該盲光偵測器。 For example, the method of claim 12, further comprising: utilizing A primary bias between the reverse bias is included to bias the primary photodetector and bias the blind photodetector with a blind bias of the same magnitude but opposite polarity. 如申請專利範圍第12項之方法,其進一步包括:利用在包含0V與包含一逆向偏壓之間的一主要偏壓來偏壓該主要光偵測器,並且利用和該主要偏壓的大小及極性相同之一盲偏壓來偏壓該盲光偵測器。 The method of claim 12, further comprising: biasing the primary photodetector with a primary bias between 0V and a reverse bias, and utilizing the magnitude of the primary bias And a blind bias of the same polarity to bias the blind photodetector.
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US5897610A (en) * 1994-09-26 1999-04-27 Luxtron Corporation Electro optical board assembly for measuring the temperature of an object surface from infra red emissions thereof including an automatic gain control therefore
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