TWI640005B - Method for generating a data set on an integrated circuit, method of manufacturing an integrated circuit, and integrated circuit device - Google Patents

Abstract

A method of generating a data set on an integrated circuit containing a programmable resistive memory cell includes applying a pulse to all members of the set of programmable resistive memory cells. The forming pulse has a forming pulse level, which is characterized in that a resistance change from an initial resistance range to an intermediate resistance range is induced in the first subset of the set, and after the formation of the pulse, a second subset of the set has a fall in the middle Out of range resistance. The method includes applying a programming pulse to the first and second subsets. The programming pulse has a programming pulse level, which is characterized by inducing a change in the resistance of the first subset from the intermediate range to the first final range, and after the programming pulse, the second subset has a resistance in the second final range, the first The subset and the second subset thereby store the data set.

Description

Method for generating data set on integrated circuit, method for manufacturing integrated circuit, and integrated circuit device

The present invention relates to an integrated circuit device having a data set generated using a physical non-copyable function, and a method for generating such a data set.

A physical unclonable function (PUF) is a processing program that can be used to create unique, random keys for physical entities such as integrated circuits. The use of PUF is a solution to generate an identification code (ID) that supports hardware intrinsic security (HIS) technology. PUF has been used for key creation in applications with high security requirements such as portable and embedded devices. One exemplary PUF is a ring oscillator PUF that uses manufacturing variability inherent to the gate's circuit conduction delay. Another exemplary PUF is a static random access memory (SRAM) PUF, in which the threshold voltages in the transistors are different such that the SRAM power is turned on at a logic "0" or a logic "1".

It is desirable to provide a physically non-copyable function for creating data in programmable resistive memory with low bit error rate and high reliability under process, voltage, temperature (PVT) conditions set.

A method for generating a data set on an integrated circuit is provided. The integrated circuit includes a plurality of programmable resistive memory cells.

The method includes applying a forming pulse to all members of a set of the programmable resistive memory cells. The forming pulse has a forming pulse level, which is characterized in that in a first subset of the set of programmable resistive memory cells, a resistance change is initiated from an initial resistance range to an intermediate resistance range, After the forming pulse, a second subset of the set of programmable resistive memory cells has a resistance that falls outside the intermediate range. Member membership in the first and second subsets is determined by the physical change in response to the forming pulse across the set.

The method includes applying a programming pulse to the first subset and the second subset of a programmable resistive memory cell. The programming pulse has a programming pulse level, which is characterized by inducing a change in resistance of the first subset from the intermediate range to a first final resistance range. The programming pulse can make the memory cell distribution in the first and second subsets of a given set of one of the programmable resistive memory cells more stable under a harsh environmental condition. In the embodiment described herein, the programming pulse can increase the sensing margin between the memory cells in the first subset and the memory cells in the second subset. After the programming pulse, the memory cells in the second subset of the programmable resistive memory cells can be maintained in a resistance range close to the initial resistance range, otherwise having a resistance in a second final resistance range, the second final The resistance range does not overlap the first final resistance range. The first and second subsets of this set of programmable memory cells are established by the combination of forming pulses and programming pulses, and will be based on the programmable resistive type naturally caused by the natural properties of the material and the manufacturing process Changes in memory cells.

The method can include, before applying the forming pulse, testing the programmable resistive memory cells of the programmable resistive memory cells on the integrated circuit to find the forming pulse level.

In order to find the formation pulse level, a test pulse with a test pulse level can be applied iteratively to the same integrated circuit as the memory cells to be used to create a unique data set, and preferably have Programmable resistive memory cells of the same structure. For each iteration, one of the test sets can be used that is different from the previously used test set. It is possible to determine a proportion of the memory cells in the test set having a resistance in the intermediate resistance range. If the ratio is lower than a threshold value, the test pulse level may be updated, and the operation of applying the test pulse and determining the ratio is repeated until the determined ratio reaches the threshold value, or more preferably falls to about 50% (for example, 40% to 60). %), And the formation pulse level can be set based on a test pulse level in an iteration that reaches the threshold or falls within the specific range.

The data set can be used to form a response to a challenge, such as in the example of a security agreement. A method of using a data set includes sensing all or part of the data set with a read voltage for a resistance between a first final resistance range and a second final resistance range, where the first final The resistance range is separated from the second final resistance range by a read limit. As mentioned earlier, the read limit can be greater than the limit between the initial resistance range and the intermediate range.

The programmable resistive memory cells can include a plurality of programmable resistive memory elements. In one embodiment, the programmable resistive memory element can be characterized by an initial resistance in a high resistance range, wherein the intermediate resistance range is lower than the high resistance range, and the first final resistance range is lower than the intermediate resistance. Range, the second final resistance range is higher than the first final resistance range.

In another embodiment, the programmable resistive memory element can be characterized by an initial resistance in a low resistance range, wherein the intermediate resistance range is higher than the low resistance range, and the first final resistance range is higher than the middle Resistance range, the second final resistance range is lower than the first final resistance range.

Applying the formation pulse as described herein can form a conductive filament that connects the first electrode and the second electrode of the memory cells in the first subset, and does not make the first electrode that connects the memory cells in the second subset. An electrode and a conductive filament of the second electrode are formed.

The programming pulse described herein can stabilize and strengthen the conductivity of the conductive filaments of the memory cells in the first subset, and does not cause a conductive filament of the memory cells in the second subset to form.

A method for manufacturing an integrated circuit is also provided, which is based on the method for generating a data set provided herein.

A device is also described that includes an integrated circuit having a memory that uses PUF to create and store a unique data set. The apparatus in this aspect of the technology includes a controller configured to perform a PUF. The controller can include a state machine located on the same integrated circuit as the memory, and logic such as a computer on a separate system that can be placed in communication with the memory or a combination of on-chip and off-chip logic Program.

Other aspects and advantages of the technology can be seen by reviewing the drawings, detailed description, and claims below.

A detailed description of embodiments of the present technology is provided with reference to the accompanying drawings. It should be understood that there is no intention to limit the technology to explicitly disclosed structural embodiments and methods, but that other features, elements, methods, and embodiments may be used to implement the technology. The preferred embodiment is described to describe the technology, rather than limiting the scope defined by the claims. Those skilled in the art to which this invention pertains will recognize various equivalent variations described below. Similar elements in the various embodiments are generally indicated by similar element symbols.

FIG. 1 is a simplified block diagram of a device, which includes a plurality of programmable resistive memory cells and a controller. The controller executes PUF to store a data set in the programmable resistive memory cells. In this example, the device includes an integrated circuit 100 having a memory formed using a programmable resistive memory cell, which is programmed using PUF to create and store a unique data set, which Can be used, for example, as a unique chip ID, a key for an authentication or encryption protocol, or other types of secret or unique data values.

The integrated circuit 100 includes a mission function circuit 110, which can include special purpose logic (sometimes referred to as application-specific integrated circuit logic), data processor resources (e.g., used in microprocessors and digital signal processors) ), Large-scale memory (such as flash memory, dynamic random access memory (DRAM), programmable resistive memory), and a combination of various types of circuits called chip system configuration. The integrated circuit 100 includes an input / output interface 120, which can include a wireless or wired port that provides access to other devices or networks. In this simplified illustration, an access control block 115 is provided between the input / output interface 120 and the task function circuit 110. The access control block 115 is coupled to the input / output interface 120 by the bus 116 and is coupled to the task function circuit 110 by the bus 111. An access control protocol is executed by the access control block 115 to enable or disable communication between the task function circuit 110 and the input / output interface 120.

With the support of the access control block 115, the security logic 125 is provided on the chip in this example. The security logic 125 is coupled to a PUF-programmed memory array 130 that stores a unique data set after the PUF is executed. The unique data set is accessible via a PUF programming controller 140 on the bus 131 next to the security logic 125 and is used by the security logic that communicates with the access control block 115 across the trace 122.

The PUF-programmed memory array 130 includes a programmable resistive memory cell, which includes a programmable element having a programmable resistor. The programmable device can include a metal oxide, such as tungsten oxide (WO _x ), hafnium oxide (HfO _x ), titanium oxide (TiO _x ), tantalum oxide (TaO _x ), and titanium oxynitride (TiNO) , Nickel oxide (NiO _x ), hafnium oxide (YbO _x ), aluminum oxide (AlO _x ), niobium oxide (NbO _x ), zinc oxide (ZnO _x ), copper oxide (CuO _x ), vanadium Oxide (VO _x ), molybdenum oxide (MoO _x ), ruthenium oxide (RuO _x ), copper silicon oxide (CuSiO _x ), silver zirconium oxide (AgZrO), aluminum nickel oxide (AlNiO), aluminum titanium Oxide (AlTiO), hafnium oxide (GdO _x ), gallium oxide (GaO _x ), zirconium oxide (ZrO _x ), chromium-doped SrZrO ₃ , chromium-doped SrTiO ₃ , PCMO, or LaCaMnO, and the like. In some cases, the programmable element of the memory cell can be a semiconductor oxide, for example silicon oxide (SiO _x).

In this example of the device, the PUF programming controller 140 is implemented as, for example, a state machine on an integrated circuit with the programmable resistive memory cells. The PUF programming controller 140 provides signals to control the bias configuration. The application of voltage to perform PUF procedures and other operations involving accessing the PUF-programmed memory array 130 for PUF and for reading data sets stored in the PUF-programmed memory array 130. The controller 140 can be implemented using special-purpose logic circuits known in the technical field to which the present invention pertains. In an alternative embodiment, the controller 140 includes a general-purpose processor that can be implemented on the same integrated circuit that executes a computer program to control the operation of the device. In yet other embodiments, a combination of special-purpose logic circuits and a general-purpose processor can be used to implement the controller 140.

In one embodiment, an apparatus includes an off-chip system (such as 410 in FIG. 4) and an integrated circuit (such as 440 in FIG. 4 and 100 in FIG. 1). The off-chip system is used to control the execution of physically non-reproducible functions on integrated circuits. For example, the off-chip system can operate a PUF programming controller (such as 140 in Figure 1) on the integrated circuit to perform all operations of applying the forming pulse, applying the programming pulse, and finding the forming pulse level Some operations. For example, the system can communicate a resistance threshold to the integrated circuit, which can be used to determine a pulse formation level. For example, the system can communicate a formation pulse level to the integrated circuit, which can be used to apply a formation pulse. For example, the system can generate memory cells for a test set in a memory array in an integrated circuit to find the address that forms the pulse level and communicate the address to an integrated system that is coupled to the system. Circuit. In another embodiment, the PUF programming controller 140 on the integrated circuit includes all the logic necessary to apply the forming pulse and the programming pulse, and to find out the forming pulse level. In this embodiment, the PUF programming controller 140 can execute logic in response to a set command from an external source, and does not need to be used for control of a system that executes a physically non-copyable function on an integrated circuit.

The PUF programming controller 140 is configured to apply a formation pulse to all members of a set of programmable resistive memory cells in the PUF-programmed memory array 130 via a bus 141. The forming pulse has a forming pulse level, which is characterized in that in a first subset of the set of memory cells, a resistance change is initiated from an initial resistance range to an intermediate resistance range, and in the formation After the pulse, a second subset of the set of programmable resistive memory cells has a resistance that falls outside the intermediate range.

The PUF programming controller 140 is configured to apply a programming pulse to the first and second subsets of the programmable resistive memory cell. The programming pulse has a programming pulse level, which is characterized by inducing a first subset of resistance changes from the intermediate resistance range to a first final resistance range. The programming pulse can increase the sensing limit between the memory cells in the first subset and the memory cells in the second subset. After the programming pulse, the memory cells in the second subset of the programmable resistive memory cells can be maintained in a resistance range close to the initial resistance range, otherwise having a resistance in a second final resistance range, the second final resistance range Does not overlap the first final resistance range. The first and second subsets of this set of programmable memory cells are established by the combination of forming pulses and programming pulses, and will be based on the programmable resistive type naturally caused by the natural properties of the material and the manufacturing process Changes in memory cells.

The PUF programming controller 140 can be configured to find the formation pulse level by testing some memory cells of the programmable resistive memory cells on the integrated circuit before applying the formation pulse. The programmable resistive memory cell under test can be in a test set of the PUF-programmed memory array 130. The test set of programmable resistive memory cells is on the same integrated circuit as the memory cells to be used to create the unique data set. The test set can be placed in a memory cell block in the PUF-programmed memory array 130, or in a discrete location in the PUF-programmed memory array 130, or at other locations on the device. In some embodiments, the test set is part of the PUF-programmed memory array 130 or is located adjacent to the memory array 130 and is formed using the same process as used to form the PUF circuit, so that they can be used in The behavior of the predictive PUF circuit in response to the formation and programming handlers described herein.

In order to find the formation pulse level, the PUF programming controller 140 can be configured to iteratively apply a test pulse having a test pulse level to a plurality of tests of a programmable resistive memory cell on the same integrated circuit A test set in the set, and determines a ratio of the memory cells in the test set having a resistance in the intermediate resistance range, and if the ratio is lower than a threshold value, then the test pulse level is updated, and the test pulse and The operation of determining the ratio is until the determined ratio reaches the threshold, and based on the test pulse level in the iterations that reach the threshold, the formation pulse level is set. For each iteration, one of the test sets can be used that is different from the previously used test set.

The PUF programming controller 140 can be configured to sense all or part of the data set in the programmed memory array 130 using a read voltage via a safety circuit (such as 125 in Figure 1), the read voltage being used in the media The resistance between the first final resistance range and the second final resistance range, wherein the first range and the second range are separated by a read limit that is greater than a limit between the initial resistance range and the intermediate range.

The programmable resistive memory cell can include a programmable resistive memory element. In one embodiment, the programmable resistive memory element can be characterized by an initial resistance in a high resistance range, wherein the intermediate resistance range is lower than the high resistance range, and the first final resistance range is lower than the intermediate resistance. Range, the second final resistance range is higher than the first final resistance range.

In another embodiment, the programmable resistive memory element can be characterized by an initial resistance in a low resistance range, wherein the intermediate resistance range is higher than the low resistance range, and the first final resistance range is higher than the middle Resistance range, the second final resistance range is lower than the first final resistance range.

Applying the formation pulse as described herein can form a conductive filament that connects the first electrode and the second electrode of the memory cells in the first subset, and does not make the first electrode that connects the memory cells in the second subset. An electrode and a conductive filament of the second electrode are formed.

The programming pulse described herein can stabilize and strengthen the conductivity of the conductive filaments of the memory cells in the first subset, and does not cause a conductive filament of the memory cells in the second subset to form.

FIG. 2 illustrates an exemplary flowchart of generating a data set on a integrated circuit including a programmable resistive memory cell. In step 210, by detecting some of the programmable resistive memory cells on the programmable resistive memory cell on the integrated circuit, a pulse formation level is found. This step is further described with reference to FIG. 3. At step 220, a set of programmable resistive memory cells forming a pulse on the integrated circuit is applied. The formation pulse has a formation pulse level found in step 210. The pulse formation level is characterized in that a resistance change from an initial resistance range to an intermediate resistance range is induced in a first subset of the set of memory cells, and after the formation pulse, a programmable resistive memory cell A second subset of the set has a resistance that falls outside the intermediate range. For example, for a WO _x (tungsten oxide) -based programmable resistive memory with an initial resistance in a high resistance range, an initial resistance range can be between about 2700 kohm (thousand ohms) and 3000 kohm. (Figure 7A), an intermediate resistance range can be in a range below a threshold level of about 400 kohm, and can be, for example, between about 100 kohm and 400 kohm (Figure 7B), the second sub A resistor set that falls outside the intermediate range after forming a pulse can be in a range that overlaps the initial resistance range, otherwise it maintains a resistance higher than the intermediate resistance range. For example, the second subset can have a resistance above a threshold level of about 2700 kohm.

At step 230, a programming pulse is applied to the first and second subsets of the programmable resistive memory cells, which increases the read limit between the memory cells in the first subset and the memory cells in the second subset. The programming pulse has a programming pulse level which is characterized by inducing a change in resistance of the first subset from a middle range to below a threshold level in a resistance of a first final resistance range. The programming pulse can increase the sensing limit between the memory cells in the first subset and the memory cells in the second subset. After the programming pulse, the memory cells in the second subset of the programmable resistive memory cells can be maintained in a resistance range that is well above a threshold level that is much greater than the maximum level of the first final resistance range, such as close to The initial resistance range, otherwise has a resistance in a second final resistance range, which does not overlap the first final resistance range. The first and second subsets of this set of programmable memory cells are established by the combination of forming pulses and programming pulses, and will be based on the programmable resistive type naturally caused by the natural properties of the material and the manufacturing process Changes in memory cells. For example, for a WO _x (tungsten oxide) -based programmable resistive memory (Figure 7C) having an initial resistance in a high resistance range, a first final resistance range can be between about 0 kohm and Between 100 kohm, a second final resistance range can be between about 2700 kohm and 3000 kohm. The first final resistance range is separated from the second final resistance range by a read limit 745 which is greater than a limit 725 between the initial resistance range and the intermediate resistance range as shown and described with reference to FIGS. 7B and 7C.

FIG. 3 shows an exemplary flowchart for finding a pulse formation level, corresponding to step 210 in FIG. 2. In step 310, a test pulse with a test pulse level is applied to a new test set of programmable resistive memory cells. The test set has a smaller size than the set of programmable resistive memory cells. For example, a test set can have a size of 64 bits, and the set can have a size of 1000 bits. The test set can be in a PUF-programmed memory array (eg, 130 in Figure 1). For each iteration, a new test set is used. As used herein, a new test set is a programmable resistive memory cell in a integrated circuit that is different from a test set of any previously used test set. In order to find out the purpose of forming a pulse level, a plurality of test sets can be obtained on an integrated circuit, such as a memory array 130 (FIG. 1) programmed by PUF. In step 320, a proportion of the memory cells having a resistance in the intermediate resistance range in the test set is determined.

In step 330, if the ratio is below a threshold (for example, 40% to 50%), then in step 340, the test pulse level is updated, and step 310 of applying the test pulse and step 320 of determining the ratio are repeated until the determined The ratio reaches this threshold. When steps 310 and 320 are repeated, a new test set is used. In the process of finding the formation of the pulse level, a new test set is used for each iteration, so different test sets in the initial resistance range can be used to determine the formation of the pulse level, which is different from the programmable in the same initial resistance range. The collection of resistive memory cells is used. Corresponding to the updated test pulse level, it is possible to determine a range of the proportion of memory cells having resistance in the intermediate resistance range in different test sets. For example, for WO _x (tungsten oxide) -based programmable resistive memory with initial resistance in a high resistance range (Figures 9-13), corresponding to the newer, applied to the individual test set The test pulse levels of different word line voltages and bit line voltages above, the proportion of memory cells with resistance in the intermediate resistance range in different test sets, with a range between 8% and 90% .

In step 350, the formation pulse level is set based on the test pulse level in the iterations that reach the threshold. Steps 310, 320, 330, 340, and 350 can be performed by the PUF programming controller 140 described with reference to the integrated circuit 100 shown in FIG. The formation of the pulse level can be based on a specific test pulse level used in a specific iteration, the result of which is the ratio to the ratio of memory cells with resistance in the intermediate resistance range in different test sets Compared to other ratios in the range, a ratio closer to the threshold. For example, if the threshold is 50%, the formation pulse level can be based on the test pulse level in an iteration that results in 53% of the memory cells having a resistance in the intermediate resistance range (Figure 11).

The procedures of Figures 2 and 3 are sufficient as part of a process for manufacturing an integrated circuit. The process includes forming a plurality of programmable resistive memory cells on the integrated circuit, connecting the integrated circuit to a system, the system. A programmable resistive memory cell configured to apply a physically non-copyable function to an integrated circuit, and using the system to a set of programmable resistive memory cells among the programmable resistive memory cells In the process described herein, a data set is generated. An example of forming a plurality of programmable resistive memory cells is included in many known manufacturing procedures in the technical field to which the present invention pertains. For example, the invention name of Lee et al. Is US Patent Application Publication No. As shown in 2016/0218146, the publication is incorporated herein by reference as if fully set forth herein.

FIG. 4 illustrates an example system for performing a physically non-copyable function on an integrated circuit. A plurality of programmable resistive memory cells are formed on the integrated circuit. The integrated circuit is connected to a system configured to apply a physically non-copyable function to a programmable resistive memory cell on the integrated circuit. Using the system, a data set can be generated in one of the sets of programmable resistive memory cells among the programmable resistive memory cells. The system can use, for example, the method described with reference to the flowcharts of FIGS. 2 and 3.

The method used by the system can include applying a forming pulse to all members of the set, wherein the forming pulse has a forming pulse level, which is characterized by the fact that it is in a set of programmable resistive memory cells. A first subset that induces a change in resistance from an initial resistance range to an intermediate resistance range, and after the forming pulse, a second subset of the set of programmable resistive memory cells has fallen outside the intermediate range The resistance.

The method used by the system can include applying a programming pulse to the first and second subsets of the programmable resistive memory cell, wherein the programming pulse has a programming pulse level, and the programming pulse level is characterized in that The first subset changes the resistance from the intermediate resistance range to a first final resistance range. The programming pulse can increase the sensing limit between the memory cells in the first subset and the memory cells in the second subset. After the programming pulse, the memory cells in the second subset of the programmable resistive memory cells can be maintained in a resistance range close to the initial resistance range, otherwise having a resistance in a second final resistance range, the second final resistance range Does not overlap the first final resistance range. The first and second subsets of the set of programmable memory cells are established by the combination of forming pulses and programming pulses, and will be based on the programmable resistive memory naturally created by the natural properties of the material and the manufacturing process Cell changes. The method used by the system can include finding the formation pulse level by testing different test sets of programmable resistive memory cells on the integrated circuit before applying the formation pulse.

An example system for executing a physically non-copyable function on an integrated circuit can include multiple device testers, multiple device probes, multiple device handlers, and multiple interface test adapters (interface test adapter). The device tester can interact with the device pin tester to test integrated circuit wafers in wafer form. The device tester can also interact with the device handler to test the packaged integrated circuit. As shown in FIG. 4, an exemplary system 410 includes a PUF logic and driver 420, and a device handler / stylus 430 coupled to a device tester (420). The integrated circuit 440 to be subject to the PUF logic and the driver 420 is coupled to the device handler / probe 430. The integrated circuit 440 includes a safety circuit. A PUF ID circuit in the security circuit includes a first subset and a second subset of a set of programmable resistive memory cells established by a combination of forming pulses and programming pulses applied to the system.

An example integrated circuit in the system 410 may be the integrated circuit 100, as described with reference to FIG. 1. During the manufacturing process of the integrated circuit 100, the system 410 performs the actions identified in the flowcharts of FIGS. 2 and 3.

Figures 5A, 5B, and 5C show a conductive filament and a non-conductive filament in a programmable resistive memory cell. Figure 5A shows a programmable resistive memory cell. A programmable resistive memory cell 500 includes a first electrode, a second electrode, and a programmable metal oxide memory element 510 located between the first electrode and the second electrode. The forming pulse can have a voltage high enough to generate a conductive portion in the programmable metal oxide memory element of the memory cell. In some metal oxide memory materials, the conductive portion can include an oxygen vacancy induced and arranged by an electrical field across the material to provide a conductive path. The formation pulses applied to the first subset and the second subset of memory cells in the set of memory cells, such as the memory cells, can make one of the first electrodes and the second electrodes connecting the memory cells in the first subset conductive. The filament is formed without forming a conductive filament that connects the first electrode and the second electrode of the memory cells in the second subset. Thus, the memory cells in the first subset can be in a low resistance state (Figure 5B), and the memory cells in the second subset can be in a high resistance state (Figure 5C). The low-resistance state and high-resistance state can be used to indicate a logic "1" or "0" in the data set.

The programming pulses applied to the first and second subsets of the programmable resistive memory cells after forming the pulses can stabilize and strengthen the conductivity of the conductive filaments of the memory cells in the first subset without making A conductive filament of memory cells in the second subset is formed.

FIG. 5B illustrates an exemplary conductive filament connected to the first electrode and the second electrode of the memory cell in the first subset through two conductive paths formed by an oxygen vacancy in the metal oxide memory element. FIG. 5C illustrates an exemplary non-conductive filament, in which the oxygen vacancy does not form a path connecting the first electrode and the second electrode of the memory cells in the second subset. Although Figures 5A, 5B, and 5C show that programmable resistive memory cells include programmable metal oxide memory elements, the techniques described herein can be applied to other types of programmable resistive memory materials.

Figures 6A and 6B illustrate a plurality of resistance ranges in an operation for generating a data set. Before a forming pulse with a forming pulse level is applied to a set of programmable resistive memory cells, all members of the set are in an initial resistance range (eg, ranges 610, 610b). After the formation pulse is applied to the set, the resistance in a first subset of the set of programmable resistive memory cells changes to an intermediate resistance range (for example, range 620, 620b), and one of the set of programmable resistive memory cells The second subset has resistances that fall outside the middle range (eg, ranges 630, 630b). After the programming pulse is applied to the set, the resistance of the first subset changes from a middle range to a first final resistance range (for example, the range 640, 640b), and the second subset of the programmable resistive memory cell has a second The resistance of the final resistance range (for example, ranges 650, 650b), and the second final resistance range does not overlap the first final resistance range.

In an embodiment shown in FIG. 6A, the initial resistance range (for example, 610) is a high resistance range, the intermediate resistance range (for example, 620) is lower than the initial resistance range (for example, 610), and the first final resistance range (for example, 610) is 640) is lower than the intermediate resistance range (for example 620), and the second final resistance range (for example 650) is higher than the first final resistance range (for example 640). The programming pulse in this embodiment is called a set pulse. The set pulse has a voltage high enough to reconnect the conductive paths in the filaments in the programmable resistive memory element in the first subset of the set of memory cells, so the programmable memory element is in a low resistance state. The filaments are further described with reference to Figures 5A, 5B, and 5C. This embodiment is suitable for technologies in which the memory cell has an initial resistance in a high resistance range and then forms a lower intermediate range, such as a WO _x- based programmable manufactured in an oxidation process that results in a high initial resistance. Resistive memory.

In another embodiment shown in FIG. 6B, the initial resistance range (for example, 610b) is a low resistance range, the intermediate resistance range (for example, 620b) is higher than the initial resistance range (for example, 610b), and the first final resistance range (for example, For example, 640b) is higher than the intermediate resistance range, and the second final resistance range (for example, 650b) is lower than the first final resistance range (for example, 640b). The programming pulse in this embodiment is called a reset pulse. The reset pulse has a voltage high enough to interrupt the conductive path in the filaments in the programmable resistive memory element in the first subset of the set of memory cells, so the programmable resistive memory element is in a high-resistance state. The filaments are further described with reference to Figures 5A, 5B, and 5C. This embodiment is suitable for a technique in which the memory cell has an initial resistance in a low resistance range and then forms to a higher intermediate range, such as a WO _x- based based on a different oxidation process that results in a low initial resistance. Programmable resistive memory.

Figures 7A, 7B, and 7C show probability plots of the resistance of memory cells at different stages of one of the PUF processing routines described herein. Figure 7A shows that before a forming pulse having a forming level is applied to a set of programmable resistive memory cells, all members of the set are in an initial resistance range, such as between about 2700 kohm and 3000 kohm (E.g. range 710).

Figure 7B shows the results after applying a pulse forming pulse to all members of the set of programmable resistive memory cells. The forming pulse has a forming pulse level, which is characterized in that in a first subset of the set of programmable resistive memory cells, a resistance change is initiated from an initial resistance range to an intermediate resistance range. The resistance range is, for example, between about 100 kohm and 400 kohm (eg, range 720), and after the forming pulse, a second subset of the set of programmable resistive memory cells has a resistance that falls outside the intermediate range (E.g. range 730). Member membership in the first and second subsets is determined by the physical change in response to the forming pulse across the set. The initial resistance range and the intermediate resistance range are separated by a read limit 725. A formation pulse level used for forming a pulse and a resistance threshold 705 for determining the formation pulse level are described with reference to FIGS. 9 to 13.

FIG. 7C illustrates the results after applying a programming pulse to the first and second subsets of the programmable resistive memory cell. The programming pulse has a programming pulse level, which is characterized in that it causes a change in the resistance of the first subset from the intermediate range to a first final resistance range, for example between about 0 kohm and 100 kohm (for example, range 740). The programming pulse can increase the sensing limit between the memory cells in the first subset and the memory cells in the second subset. After the programming pulse, the memory cells in the second subset of the programmable resistive memory cells can be maintained in a resistance range close to the initial resistance range, otherwise having a resistance in a second final resistance range (for example, the range 750), the first The two final resistance ranges do not overlap with the first final resistance range. The first and second subsets of the set of programmable memory cells are established by the combination of forming pulses and programming pulses, and will be based on the programmable resistive memory naturally created by the natural properties of the material and the manufacturing process Cell changes. The first final resistance range and the second final resistance range are separated by a read limit 745, which is larger than a limit 725 between the initial resistance range and the intermediate resistance range shown in FIG. 7B. Such a read limit can be wide enough to ensure the reliability of the first and second subsets of the programmable resistive memory cells storing the data set under PVT (process, voltage, temperature) changes.

FIG. 8 shows different conditions for finding a pulse level, and then forming a pulse level can control the randomness of the data set. These conditions can include the height of the voltage and / or current pulses applied to the set of programmable resistive memory cells used to generate the data set. The randomness of the data set is related to the proportion of one of the memory cells in the test set with a resistance in the middle resistance range. As shown in the example in FIG. 8, conditions 1, 2, 3, 4, and 5 respectively make the data “0” corresponding to the intermediate resistance range have about 10%, about 30%, about 50%, and about 80% of the test set. , And about 90% of memory cells. The formation pulse level can be adjusted according to the design specifications of a specific integrated circuit using the techniques described herein.

Figures 9 to 13 show operations for finding a pulse level. To find out the formation pulse level, a test pulse with a test pulse level can be applied iteratively to the same integrated circuit as the memory cells to be used to create a unique data set, and preferably One test set of programmable resistive memory cells with the same structure. For each iteration, one of the test sets can be used that is different from the previously used test set. It is possible to determine a proportion of the memory cells in the test set having a resistance in the intermediate resistance range. If the ratio is lower than a threshold value, the test pulse level can be updated, and the operation of applying test pulses and determining the ratio is repeated until the determined ratio reaches the threshold value, and can be based on the test pulses in the iterations that reach the threshold value. The level sets the formation pulse level.

An empirically determined resistance threshold 905 can be used to determine whether a memory cell has a resistance that is below the resistance threshold and falls in the middle resistance range. As shown in the examples in Figures 9 to 13, the resistance threshold 905 is about 700 kohm. Because the first final resistance range is separated from the second final resistance range by a wide read limit 745 (Figure 7C), the resistance threshold 905 can fall within this wide limit and is used to determine which memory cells are in the middle resistance range In purpose. For example, instead of 700 kohm, the resistance threshold can be 800 kohm, 900 kohm, and 1000 kohm. An advantage of having a wide limit is that the resistance of any memory cell may cause reliability problems due to drift across the limits of PVT (process, voltage, temperature) conditions, which is less likely to occur.

FIG. 9 shows an exemplary condition 1 for finding the pulse formation level. Condition 1 includes a test set of 5 V bit line (WL) voltage, 5 V bit line (BL) voltage, and a current of 41 μA to the programmable resistive memory cell. Condition 1 causes 8% of the memory cells in the test set to be in the set state or have data "0" (for example, range 940), and 92% of the memory cells in the test set are in the initial resistance state or have data "1" (for example, range 950) .

FIG. 10 shows an exemplary condition 2 for finding the pulse formation level. Condition 2 includes a test set of applying a word line voltage of 2.5 V and a bit line voltage of 4 V to a programmable resistive memory cell. Condition 2 makes 35% of the memory cells in the test set in the set state or have data "0" (for example, range 1040), and 65% of the memory cells in the test set are in the initial resistance state or have data "1" (for example, range 1050) .

FIG. 11 shows an example condition 3 for finding the pulse formation level. Condition 3 includes a test set of applying a word line voltage of 4 V and a bit line voltage of 4 V to a programmable resistive memory cell. Condition 3 makes 53% of the memory cells in the test set in the set state or have the data "0" (for example, range 1140), and 47% of the memory cells in the test set are in the initial resistance state or have the data "1" (for example, range 1150) .

FIG. 12 illustrates an exemplary condition 4 for finding the pulse formation level. Condition 4 includes a test set of applying a word line voltage of 2.5 V and a bit line voltage of 4.5 V to a programmable resistive memory cell. Condition 4 enables 80% of the memory cells in the test set to be in the set state or have data "0" (for example, range 1240), and 20% of the memory cells in the test set are in the initial resistance state or have data "1" (for example, range 1250) .

FIG. 13 shows an exemplary condition 5 for finding the pulse formation level. Condition 5 includes a test set of applying a word line voltage of 3.5 V and a bit line voltage of 4.5 V to a programmable resistive memory cell. Condition 5 enables 90% of the memory cells in the test set to be in the set state or have data "0" (for example, range 1340), and 10% of the memory cells in the test set are in the initial resistance state or have data "1" (for example, range 1350) .

For example, if the desired threshold for the proportion of memory cells in the test set is about 50%, or better falls within a specific range of about 50% (e.g., 40% to 60%), it can be achieved based on use. The threshold, or the test pulse level in an iteration that falls within the specific range (e.g., condition 3 in Figure 10), or more preferably based on the use of the test pulse bit in the iterations that fall within the specific range Level, set the pulse formation level.

Figures 14A, 14B, and 14C show exemplary results of applying test pulses in a test set using condition 3 described with reference to Figure 11. In the example of Figure 14A, the memory cells in the test set are in an initial resistance range greater than one of 3 Mohm. In the example in FIG. 14B, after a test pulse corresponding to condition 3 is applied, a first subset of the test set changes to an intermediate resistance range, or is in a forming state. In the example of Figure 14C, after the programming / setting pulse is applied, the first subset changes from the intermediate resistance range to a first final resistance range below 50 kohm.

15A and 15B illustrate the results of generating a first data set (PUF-ID1) in a first PUF ID array and generating a second data set (PUF-ID2) in a second PUF ID array. As shown in Figures 15A and 15B, the present technology exhibits high uniqueness and unpredictable characteristics between a first PUF ID array (such as array 01) and a second PUF ID array (such as array 02), where each PUF ID array Contains 1 kbits. In this example, the first PUF ID array and the second PUF ID array have WO _x (tungsten oxide) -based programmable resistive memory cells that have an initial resistance in a high resistance range.

Reliability tests have been performed on data sets generated by this technology under various conditions (eg, before baking, baking at 250 ^o C for 0.25 hours, and baking at 250 ^o C for 65 hours). The reliability testing before use in baking, after baking at 250 ^o C 0.25 hours and ID memory cell array 1000 in a PUF after baking at 250 ^o C 65 h. In contrast, the resistance state of the 1000 memory cells in the PUF ID array after baking under two different conditions is consistent with the resistance state of the 1000 memory cells in the PUF ID array before baking. Therefore, the data set generated by this technology demonstrates the performance of no bit error rate (BER) under high temperature (250 ^o C) baking conditions (BER = 0.00%), and can be applied to the Internet of Things (Internet of Things, IoT) products and security chips.

FIG. 16 illustrates a reading limit 1660 between a first final resistance range (eg, a range of 1640) and a second final resistance range (eg, a range of 1650) under high temperature baking conditions (eg, 250 ^o C). In this example, the read limit of 1660 is between 400 kohm and 1000 kohm, that is, a sense resistance threshold of 700 kohm +/- 300 kohm is supported. The read limit of 1660 is wide enough to separate the first final resistance range and the second final resistance range, even in a few tail bits (e.g., range) that may be induced under high temperature baking conditions (e.g., 250 ^o C) 1670) The same is true where it exists.

This technology can be implemented in devices where the memory cell has an initial resistance in a high resistance range and then forms a lower intermediate range, including transition metal oxide devices (programmable resistive memory based on WO _x , Programmable resistive memory based on tantalum pentoxide (Ta ₂ O ₅ ), programmable resistive memory based on hafnium dioxide (HfO ₂ ), programmable resistive memory based on titanium oxynitride (TiON) , based on a programmable resistance memory TiO _x), the programmable resistance conductive filament RRAM (based on copper, silver based), with the memory, and the anti-fuse device (metal oxide semiconductor (MOS variation) or Metal-Insulator-Metal (MIM) structure, with dielectric breakdown, acts as an anti-fuse memory cell).

The technology can be implemented in a memory cell where the memory cell has an initial resistance in a low resistance range and then formed into a higher intermediate range memory cell, including a metal oxide memory with a low initial resistance, such as a WO _x programmable resistor Memory, and fuse devices such as metal fuses, polycrystalline silicon fuses, and contact fuses.

Although the present technology is disclosed by the above-mentioned preferred embodiments and detailed examples, it can be understood that these examples are for description rather than limitation. It is expected that those with ordinary knowledge in the technical field to which the present invention pertains may reasonably make adjustments and combinations without departing from the spirit of the present technology and the scope of the following claims.

100, 440: integrated circuit 110: task function circuit 111, 116, 131, 141: bus 115: access control block 120: input / output interface 122: wiring 125: safety logic 130: memory array 140: controller 210, 220, 230, 310, 320, 330, 340, 350: Step 410: System 420: PUF logic and driver 430: Device handler / probe 500: Memory cell 510: Metal oxide memory element 610, 610b, 620, 620b, 630, 630b, 640, 640b, 650, 650b, 710, 720, 730, 740, 750, 940, 950, 1040, 1050, 1140, 1150, 1240, 1250, 1340, 1350, 1640, 1650, 1670: range 705, 905: resistance threshold 725: limit 745, 1660: read limit

Figure 1 is a simplified block diagram of a device that includes an integrated circuit with memory that uses PUF to create and store a unique data set. FIG. 2 illustrates an exemplary flowchart of generating a data set on a integrated circuit including a programmable resistive memory cell. FIG. 3 shows an exemplary flowchart for finding a pulse formation level. FIG. 4 illustrates an exemplary system for performing a physically non-copyable function on an integrated circuit. Figures 5A, 5B, and 5C show a conductive filament and a non-conductive filament in a programmable resistive memory cell. Figures 6A and 6B illustrate a plurality of resistance ranges in an operation for generating a data set. Figures 7A, 7B, and 7C show probability plots of the resistance of memory cells at different stages of one of the PUF processing routines described herein. FIG. 8 illustrates different conditions for finding a pulse level. Figures 9 to 13 show operations for finding a pulse level. Figures 14A, 14B, and 14C show exemplary results of applying test pulses in a test set. 15A and 15B illustrate the results of generating a first data set in a first PUF ID array and generating a second data set in a second PUF ID array. FIG. 16 illustrates a read limit between the exemplified first final resistance range and the second final resistance range under high temperature baking conditions.

Claims (10)

A method for generating a data set on an integrated circuit. The integrated circuit includes a plurality of programmable resistive memory cells. The method includes: applying a forming pulse to a set of the programmable resistive memory cells. For all members, the forming pulse has a forming pulse level, which is characterized in that, in a first subset of the set of the programmable resistive memory cells, triggering from an initial resistance range to a middle A resistance change in a resistance range, and after the forming pulse, a second subset of the set of the programmable resistive memory cells has a resistance that falls outside the intermediate resistance range; and a programming pulse is applied to the The first and second subsets of the programmable resistive memory cell, the programming pulse has a programming pulse level, and the programming pulse level is characterized by triggering the first subset from the intermediate resistance range to A resistance change in a first final resistance range, and after the programming pulse, the second subset of the programmable resistive memory cells has a second final resistance range Resistance, the second final resistance ranges do not overlap with the first final resistance range, the plurality of programmable resistive memory cells of the first subset and the second subset of the set storing the data set thereby. The method according to item 1 of the scope of patent application, comprising, before applying the forming pulse, testing the programmable resistive memory cells of the programmable resistive memory cells on the integrated circuit to find the The pulse level is formed. The method according to item 1 of the scope of patent application, comprising, before applying the forming pulse, finding the forming pulse level by a method including the following steps: Iteratively applying a test with a test pulse level Pulse to one of the programmable resistive memory cells test set, and determine a proportion of the programmable resistive memory cells having a resistance in the intermediate resistance range in the test set, and if the ratio is low Update the test pulse level at a threshold, repeat the steps of applying the test pulse and the step of determining on different test sets until the determined ratio reaches the threshold, and based on the threshold being reached The test pulse level in one iteration sets the formation pulse level. The method according to item 1 of the patent application scope, comprising sensing the data set using a read voltage, the read voltage being used for a resistance between the first final resistance range and the second final resistance range, The first final resistance range and the second final resistance range are separated by a read limit, and the read limit is greater than a limit between the initial resistance range and the intermediate resistance range. The method according to item 1 of the scope of patent application, wherein the programmable resistive memory cells include a plurality of programmable resistive memory elements, and the features of the programmable resistive memory elements are in a high resistance range. An initial resistance, wherein the intermediate resistance range is lower than the high resistance range, the first final resistance range is lower than the intermediate resistance range, and the second final resistance range is higher than the first final resistance range. The method according to item 1 of the patent application range, wherein the programmable resistive memory cells include a plurality of programmable resistive memory elements, and the features of the programmable resistive memory elements are in a low resistance range. An initial resistance, wherein the intermediate resistance range is higher than the low resistance range, the first final resistance range is higher than the intermediate resistance range, and the second final resistance range is lower than the first final resistance range. The method according to item 1 of the scope of patent application, wherein the programmable resistive memory cells include a plurality of programmable resistive memory elements, and the step of applying the forming pulses connects the first subset of the A conductive filament of the first electrode and the second electrode of the programmable resistive memory cells is not formed to connect the first electrode and the second electrode of the programmable resistive memory cells in the second subset. A conductive filament is formed. The method according to item 7 of the scope of patent application, wherein the programming pulse stabilizes and strengthens the conductivity of the conductive filaments of the programmable resistive memory cells in the first subset without making the second sub A conductive filament of the concentrated resistive memory cells is formed. A method of manufacturing an integrated circuit, comprising: forming a plurality of programmable resistive memory cells on the integrated circuit; connecting the integrated circuit to a system configured to apply a physically non-copyable function to The programmable resistive memory cells on the integrated circuit; and using the system to collect one of the programmable resistive memory cells in the programmable resistive memory cells through the following steps, Generate a data set: A forming pulse is applied to all members in the set, the forming pulse has a forming pulse level, and the forming pulse level is characterized in that one of the sets of the programmable resistive memory cells The first subset causes a change in resistance from an initial resistance range to an intermediate resistance range, and after the forming pulse, a second subset of the set of the programmable resistive memory cells has the intermediate resistance Resistance outside the range; and applying a programming pulse to the first subset and the second subset of the programmable resistive memory cells, the programming pulse having a programming pulse The programming pulse level is characterized in that it causes a change in the resistance of the first subset from the intermediate resistance range to a first final resistance range, and after the programming pulse, the programmable resistive memory cells The second subset has a resistance in a second final resistance range, the second final resistance range does not overlap the first final resistance range, the first subset of the set of the programmable resistive memory cells and The second subset thereby stores the data set. An integrated circuit device includes: a plurality of programmable resistive memory cells; and a controller configured to be included in a set of the programmable resistive memory cells among the programmable resistive memory cells A data set is generated by a program including the following steps: A formation pulse is applied to all members in the set, the formation pulse has a formation pulse level, and the formation pulse level is characterized in that A first subset of the set of programmed resistive memory cells initiates a change in resistance from an initial resistance range to an intermediate resistance range, and after the formation pulse, a set of the programmable resistive memory cells A second subset having a resistance falling outside the intermediate resistance range; and applying a programming pulse to the first subset and the second subset of the programmable resistive memory cells, the programming pulse having a programming pulse Level, the programming pulse level is characterized by inducing a change in resistance of the first subset from the intermediate resistance range to a first final resistance range, and after the programming pulse The second subset of the programmable resistive memory cells has a resistance in a second final resistance range, the second final resistance range does not overlap the first final resistance range, the programmable resistive memories The first subset and the second subset of the set thereby store the data set.