TWI536595B - Solar cell, method of manufacturing the same and module comprising the same - Google Patents

Description

Solar cell, manufacturing method thereof and module thereof

The invention relates to a solar cell, a manufacturing method thereof and a module thereof, in particular to a back contact solar cell, a manufacturing method thereof and a module thereof.

Referring to FIG. 1 , a conventional interdigitated back contact solar cell (IBC) 9 includes an n-type substrate 91 , a passivation layer 92 , and a first electrode 93 and a first Two electrodes 94. The substrate 91 includes a light receiving surface 911, a back surface 912 opposite to the light receiving surface 911 and disposed on the passivation layer 92, and an emitter region 913, a spacer region 915 and a back surface electric field respectively located on the back surface 912 side. Back Surface Field 914. The emitter region 913 is p-type, the back surface electric field region 914 is of the n ⁺ type, and the spacer region 915 separates the emitter region 913 from the back surface electric field region 914. The first electrode 93 is located on the passivation layer 92 and passes through the passivation layer 92 to connect the emitter layer. The second electrode 94 is located on the passivation layer 92 and can pass through the passivation layer 92 to connect the back surface electric field. District 914.

The main feature of the back contact solar cell 9 is that the first An electrode 93 and the second electrode 94 are both located on the back surface 912 of the substrate 91, and no electrode is disposed on the light-receiving surface 911 side. Therefore, the light-receiving area of the light-receiving surface 911 can be increased to increase the amount of light, thereby enhancing the back contact. Photoelectric conversion efficiency of the solar cell 9.

In practice, the surface of the substrate 91 is usually passivated and repaired through the setting of the passivation layer 92 to reduce Dangling Bond and defects on the surface, thereby reducing carrier traps and reducing surface recombination of carriers. The rate is to increase the photoelectric conversion efficiency of the solar cell 9.

As far as the material of the passivation layer 92 is concerned, some solar cells 9 use a material with a negative fixed charge (for example, Al ₂ O ₃ ) as the material of the passivation layer 92, in this case, although negatively charged. The passivation layer 92 has an excellent passivation protection effect for the p-type emitter region 913, but the passivation layer 92 with a negative fixed charge has a poor passivation effect on the n-type back surface electric field region 914, and is negatively charged. The passivation layer 92 attracts positive charges to accumulate in the spacer 915, and the spacer 915 forms an inversion layer (also referred to as a floating junction), which forms a fixed charge, thereby forming a parasitic shunt ( Parasitic Shunting) causes leakage current (Leakage Current), causing a short circuit of the component, which will affect the photoelectric conversion efficiency of the solar cell 9. Some solar cells 9 will use a material with a positive fixed charge (e.g., SiN _X ) as the material of the passivation layer 92, although the positively charged passivation layer 92 has a back surface electric field region 914 for the n-type. An excellent passivation protection effect, but the relatively positively charged passivation layer 92 has a poor passivation effect on the p-type emitter region 913.

In addition, some solar cells 9 use a material having a lower fixed charge density (for example, SiO _X ) as a material of the passivation layer 92, which is not attracted because of a low fixed charge density. Charge builds up in the spacer 915, thereby avoiding the generation of parasitic shunts, so that the passivation protection is provided for both the n-type emitter region 913 or the p-type back surface electric field region 914.

However, such a passivation layer 92 is mainly formed by a high-temperature thermal oxidation process, specifically, heating the substrate 91 to a high temperature of several hundred degrees C or more in a heating chamber, and then introducing moisture and oxygen. The back surface 912 of the substrate 91 is oxidized. The high-temperature environment of the high-temperature thermal oxidation process not only lowers the service life of the substrate 91 but also degrades the material quality of the substrate 91, thereby facilitating the formation of defects in the substrate 91, resulting in an increase in the composite probability of the carrier in the substrate 91.

In addition, since the manufacturing sequence of the passivation layer 92 is generally after the emitter region 913 and the back surface electric field region 914, the aforementioned high temperature environment also affects the doping elements of the emitter region 913 and the back surface electric field region 914. Diffusion of the range doped in the substrate 91 causes the spacer 915 to shrink, which in turn makes the solar cell 9 susceptible to leakage current and component short-circuit problems, thereby affecting its photoelectric conversion efficiency.

Therefore, an object of the present invention is to provide a solar cell, a method for manufacturing the same, and a module thereof which are excellent in passivation effect and can avoid generation of leakage current and component short-circuit problem, thereby improving photoelectric conversion efficiency.

Therefore, the solar cell of the present invention comprises: a substrate, a a passivation layer, and an electrode layer. The substrate includes a light receiving surface and a back surface, and a back surface electric field region, a spacing region and an emitter region respectively located on the back surface, the spacing region separating the emitter region from the back surface electric field interval. The passivation layer is on the back side. The electrode layer is disposed on the passivation layer, and the electrode layer is connected to the emitter region and the back surface electric field region through a first through hole and a second through hole of the passivation layer. The passivation layer includes an intrinsic amorphous germanium layer that directly covers the emitter region, the spacer region, and the back surface electric field region.

The solar cell module of the present invention comprises: a first plate and a second plate disposed oppositely, a plurality of solar cells arranged as described above between the first plate and the second plate, and a An encapsulating material between the first plate and the second plate and surrounding the plurality of solar cells.

The method for manufacturing a solar cell of the present invention comprises: preparing a substrate, the substrate comprising a light receiving surface and a back surface; forming an emitter region, a spacer region and a back surface electric field region on the back surface of the substrate, and making the spacer region Separating the emitter region from the back surface electric field; forming a passivation layer on the back surface, the passivation layer comprising an intrinsic amorphous germanium layer, and the intrinsic amorphous germanium layer directly covering the emitter region, a spacer region and the back surface electric field region; and forming an electrode layer on the passivation layer, and connecting the electrode layer through the first through hole and the second through hole of the passivation layer to respectively connect the emitter region and the back surface Electric field area.

The effect of the invention is that the intrinsic amorphous germanium layer of the passivation layer directly covers the emitter region, the spacer region and the back surface electric field region, thereby improving the passivation effect and the carrier collection rate of the substrate, and avoiding the interval The region generates parasitic shunts to avoid leakage currents and component short circuits. Therefore, in general, the solar cell of the present invention can improve current collection efficiency and improve photoelectric conversion efficiency.

11‧‧‧ first plate

12‧‧‧Second plate

13‧‧‧Solar battery

14‧‧‧Package

15‧‧‧welding wire

2‧‧‧Substrate

21‧‧‧Stained surface

22‧‧‧ Back

23‧‧‧ front surface electric field

24‧‧‧The polar zone

25‧‧‧Back surface electric field

26‧‧‧ interval zone

3‧‧‧Anti-reflective layer

4‧‧‧ Passivation layer

41‧‧‧ Essential amorphous layer

42‧‧‧Undoped dielectric layer

43‧‧‧First perforation

44‧‧‧Second perforation

5‧‧‧electrode layer

51‧‧‧First electrode

52‧‧‧second electrode

7‧‧‧mask layer

81~87‧‧‧Steps

Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a schematic cross-sectional view of a known back contact solar cell; FIG. 2 is one of the solar cell modules of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a schematic cross-sectional view showing a solar cell of a preferred embodiment; FIG. 4 is a flow chart of a preferred embodiment of a solar cell manufacturing method of the present invention. Figure 5 and Figure 5 are schematic flow diagrams of one of the steps of the manufacturing method.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 2, a preferred embodiment of the solar cell module of the present invention comprises: a first plate 11 and a second plate 12 disposed at an upper and lower interval, and a plurality of arrays arranged on the first plate 11 and a solar cell 13 between the second sheets 12, and a first sheet 11 and the same The package material 14 between the second sheets 12 and surrounding the plurality of solar cells 13.

In the present embodiment, the material of the first plate 11 and the second plate 12 is not particularly limited, and a glass or plastic plate may be used, and the plates on the light receiving side of the plurality of solar cells 13 must be transparent. The material of the encapsulant 14 is, for example, a light transmissive ethylene vinyl acetate copolymer (EVA), or other related materials usable for the solar cell module package, and is not limited to the examples of the embodiment. Further, the plurality of solar cells 13 are electrically connected to each other through a plurality of ribbon wires 15. Since the structures of the plurality of solar cells 13 are the same, only one of them will be described below as an example. Of course, the structure of the plurality of solar cells 13 in a module is not absolutely necessary.

Referring to FIG. 3, the solar cell 13 of the present embodiment includes a substrate 2, an anti-reflection layer 3, a passivation layer 4, and an electrode layer 5.

The substrate 2 of the present embodiment may be an n-type single crystal germanium substrate or a polycrystalline germanium substrate, and includes a light receiving surface 21 and a back surface 22 opposite to each other, a front surface electric field region 23 disposed on the light receiving surface 21 side, and respectively An emitter region 24, a back surface electric field region 25 and a spacer region 26 are disposed on the back surface 22 side.

The light receiving surface 21 has a roughened structure, thereby increasing the amount of light incident. The front surface electric field region 23 is located inside the light receiving surface 21, and is arranged to extend along the unevenness of the light receiving surface 21. The front surface electric field region 23 is an n ⁺ -type semiconductor, and its doping concentration is greater than the doping concentration of the substrate 2, thereby forming a front surface electric field (Front-Side Field, FSF for short) to improve carrier collection efficiency and photoelectric conversion. effectiveness. In practice, a diffusion process (eg, phosphorus diffusion) or other doping method may be utilized to make the doping concentration at the light receiving surface 21 higher than the inside of the substrate 2, thereby forming an n ⁺ -type semiconductor.

The emitter region 24 is located inside the back surface 22 and is a p ⁺ -type semiconductor having different doping properties than the substrate 2, thereby forming a pn junction, which is a source of photoelectric effect. In practice, the emitter region 24 partially forms a heavily doped p ⁺ -type semiconductor inside the substrate 2 by a diffusion process (eg, boron diffusion) or other doping.

The back surface electric field region 25 is located inside the back surface 22 and is an n ⁺⁺ type semiconductor. In practice, the back surface electric field region 25 is partially formed into a heavily doped n ⁺⁺ type semiconductor by a diffusion process (eg, phosphorus diffusion) or other doping manner, and the doping concentration thereof is greater than The doping concentration of the substrate 2, thereby forming a Back-Side Field (BSF) to improve carrier collection efficiency and photoelectric conversion efficiency.

It should be noted that if the substrate 2 is a p-type semiconductor substrate, the front surface electric field region 23 is formed as a p ⁺ -type semiconductor having a doping concentration greater than that of the p-type substrate 2, and the back surface electric field region 25 is fabricated. The p ⁺⁺ type semiconductor having a doping concentration greater than the front surface electric field region 23 is formed, and the emitter region 24 is formed as an n-type semiconductor.

The spacer 26 is located inside the back surface 22 and spaces the emitter region 24 from the back surface electric field region 25 so that the two are not connected to each other. In fact, when the emitter region 24 and the back surface electric field region 25 are formed by a diffusion process, the emitter region 24 and the back surface electric field region 25 are separated by appropriate process control, and the emitter region 24 is The back surface electric field region 25 The region where no diffusion process is additionally performed becomes the spacer 26. The surface of the spacer 26 may be as high as the surface of the emitter region 24 and the back surface electric field region 25 as shown in FIG. 3, but the surface of the spacer region 26 may also be opposite to the emitter according to process requirements. The surface 24 and the surface of the back surface electric field region 25 are not equal in height.

The anti-reflection layer 3 of the present embodiment is disposed on the light-receiving surface 21 along the undulations of the light-receiving surface 21, and covers the front surface electric field region 23, such as tantalum nitride (SiN _X ). It is used to increase the amount of light incident and reduce the surface recombination Velocity (SRV).

The passivation layer 4 of the present embodiment is disposed on the back surface 22 and includes an Intrinsic Amorphous Silicon Layer directly covering the emitter region 24, the spacer region 26, and the back surface electric field region 25. 41. An undoped dielectric layer 42 (Undoped Dielectric Layer) directly covering the intrinsic amorphous germanium layer 41 and having a material different from the amorphous germanium layer, a through-essential amorphous germanium layer 41 and the undoped dielectric layer The electrical layer 42 exposes the first via 43 of the emitter region 24, and a second via 44 extending through the intrinsic amorphous germanium layer 41 and the undoped dielectric layer 42 to expose the back surface electric field region 25. The passivation layer 4 is mainly used for passivating and repairing the surface of the substrate 2 to reduce the Dangling Bond and defects of the surface, thereby reducing carrier trap and reducing the surface recombination rate of the carrier, thereby improving the The photoelectric conversion efficiency of the solar cell 13.

In practice, the material of the intrinsic amorphous germanium layer 41 may be Intrinsic Silicon or Intrinsic Hydrogenated Silicon; and the material of the undoped dielectric layer 42 may be an oxide. , nitride or a combination of the above materials. In the present embodiment, the material of the intrinsic amorphous germanium layer 41 is specifically an essentially hydrogenated amorphous germanium. For the substrate 2 having a germanium material, the hydrogen bond of the substantially hydrogenated amorphous germanium can provide better passivation and The repair effect; and the undoped dielectric layer 42 specifically uses tantalum nitride (SiN _X ).

The electrode layer 5 of this embodiment is located on the passivation layer 4, the electrode layer 5 has a first via 51 connected to the emitter region 24 through the first via 43 of the passivation layer 4, and a passivation layer 4 The second via 44 is connected to the second electrode 52 of the back surface electric field region 25.

It should be noted that, in this embodiment, an emitter region 24, a spacer region 26, and a back surface electric field region 25 are taken as an example. However, in a solar cell 13, the emitter region 24 and the spacer region 26 are actually included. The number of the back surface electric field regions 25 may be more and arranged in a staggered manner in a pnpn manner, and a spacer 26 is formed between any adjacent set of the emitter regions 24 and the back surface electric field region 25. The first electrode 51 and the first through hole 43 correspond to the number and position of the emitter regions 24, and the second electrode 52 and the second through hole 44 correspond to the number and position of the back surface electric field regions 25.

Referring to Figures 3, 4 and 5, a preferred embodiment of the manufacturing method of the present invention comprises:

Step 81: Prepare the substrate 2, roughen the light-receiving surface 21 of the substrate 2, and polish the back surface 22 of the substrate 2. Wherein, the light-receiving surface 21 is formed into a roughened structure to improve the entrance. The amount of light, but the implementation is not necessary for roughening.

Step 82: forming the emitter region 24, the spacer region 26 and the back surface electric field region 25 on the inner side of the back surface 22 of the substrate 2, and causing the spacer region 26 to combine the emitter region 24 and the back surface electric field region. 25 spaced apart. Thereafter, a mask layer 7 is disposed on the back surface 22.

Specifically, the emitter region 24 is doped with boron diffused manner in the local region of the back surface 22 of the inner prepared heavily doped p ⁺ -type semiconductor. The back surface electric field region 25 is a doping concentration of phosphorus diffusion in a local region on the inner side of the back surface 22 to produce a doping concentration greater than that of the substrate 2 of the n ⁺⁺ type semiconductor. At the same time, the emitter region 24 can be spaced from the back surface electric field region 25 by appropriate process control, such as providing a barrier layer or a mask, to avoid parasitic shunting and leakage current ( Leakage Current). At this time, the region between the emitter region 24 and the back surface electric field region 25 without additional diffusion process becomes the spacer region 26.

Next, the mask layer 7 may be formed by vacuum coating using, for example, PECVD, so that the mask layer 7 covers the emitter region 24, the spacer region 26, and the back surface electric field region 25. The vacuum coating method may include physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like, and the material of the mask layer 7 is specifically, for example, ruthenium oxide.

In this embodiment, the emitter region 24, the back surface electric field region 25, and the mask layer 7 are both fabricated in an environment greater than 700 °C.

Step 83: The front surface electric field region 23 is formed inside the light receiving surface 21 of the substrate 2. In practice, a diffusion process or a doping paste may be used to make a local region of the light-receiving surface 21 have a higher doping concentration than the inside of the substrate 2, thereby forming a partially doped n ⁺ -type semiconductor. The front surface electric field region 23 is obtained. In the present embodiment, the front surface electric field region 23 is fabricated in an environment of more than 700 °C.

Further, in practice, the order of steps 82 and 83 may be reversed, that is, after the front surface electric field region 23 is formed on the light receiving surface 21, the emitter layer region is formed on the back surface 22, and the interval is formed. The region 26 and the back surface electric field region 25 are not limited to the examples of the embodiment.

Step 84: forming the anti-reflection layer 3 on the light-receiving surface 21 of the substrate 2, and the anti-reflection layer 3 covers the front surface electric field region 23. Thereafter, the mask layer 7 is removed.

In practice, the anti-reflective layer 3 may be formed on the front surface electric field region 23 by a vacuum coating method such as PECVD, and the anti-reflective layer 3 may be made of tantalum nitride (SiN _X ) or the like. Further, this embodiment removes the mask layer 7 by wet etching. In the present embodiment, the anti-reflection layer 3 is manufactured in an environment of more than 350 °C.

Step 85: forming the passivation layer 4 on the back surface 22 of the substrate 2 such that the intrinsic amorphous germanium layer 41 of the passivation layer 4 directly covers the emitter region 24, the spacer region 26 and the back surface electric field region 25. The undoped dielectric layer 42 of the passivation layer 4 directly covers the intrinsic amorphous germanium layer 41.

In practice, the intrinsic amorphous germanium layer 41 is formed on the back surface 22 by a vacuum coating method of PECVD under the environment of a temperature of 200 to 250 ° C, and the material of the intrinsic amorphous germanium layer 41 is substantially hydrogenated. Amorphous germanium. Then, using the vacuum coating method of PECVD, at the temperature The undoped dielectric layer 42 is formed on the intrinsic amorphous germanium layer 41 in an environment below 200 ° C, and the material of the undoped dielectric layer 42 is tantalum nitride.

Step 86: forming the first via 43 on the passivation layer 4 and corresponding to the emitter region 24 to expose the emitter region 24, and forming on the passivation layer 4 and corresponding to the back surface electric field region 25. The second via 44 exposes the back surface electric field region 25. Specifically, through photolithography, dry etching, such as laser etching, wet etching, or etching (Etching Paste), etc., respectively, through the intrinsic amorphous germanium layer 41 and the undoped dielectric layer. The first through hole 43 of the 42 and the second through hole 44.

Step 87: forming the electrode layer 5 on the passivation layer 4, and passing the first electrode 51 and the second electrode 52 of the electrode layer 5 through the first through hole 43 and the second through hole 44 of the passivation layer 4, respectively. The emitter region 24 is connected to the back surface electric field region 25. Specifically, the first electrode 51 and the second electrode 52 may be disposed by screen printing, printing, or vacuum coating.

It should be noted that the formation temperature of the undoped dielectric layer 42 of the present embodiment is lower than the formation temperature of the intrinsic amorphous germanium layer 41, and the amorphous semiconductor layer 42 is disposed to protect the amorphous矽 layer 41. Specifically, since the material of the undoped dielectric layer 42 is ceramic, it has better hardness and chemical resistance, so that the amorphous layer 41 can be prevented from being destroyed or due to environmental factors such as moisture or Oxidation causes a problem that the passivation ability of the intrinsic amorphous germanium layer 41 is lowered.

In addition, although the passivation effect of the intrinsic amorphous germanium layer 41 is better, the amorphous germanium layer 41 is more susceptible to the external environment based on the above-described nature. In this embodiment, the material of the undoped dielectric layer 42 is designed to have a material other than amorphous germanium and has better protection ability to protect and avoid the intrinsic amorphous germanium layer 41 from being affected by the external environment and reducing the passivation. quality.

Of course, in practice, the passivation layer 4 of the solar cell 13 may not include the undoped dielectric layer 42 . In this case, in the manufacturing process, only the essential amorphous is formed on the back surface 22 of the substrate 2 in step 85 . The germanium layer 41; in step 86, the first via 43 and the second via 44 are only penetrated through the intrinsic amorphous germanium layer 41.

In this embodiment, since the intrinsic amorphous germanium layer 41 has a low fixed charge density (Fixed Charge Density), the intrinsic amorphous germanium layer 41 directly covers the emitter region 24, the spacer region 26 and the The design of the back surface electric field region 25 allows the charge to be accumulated without being attracted to the spacer region 26, thereby avoiding the problem of parasitic shunting, leakage current, and short-circuiting of components, so that the emitter region of the p-type is used. The back surface electric field region 25 of the 24 or n type provides better passivation protection. Thus, the present embodiment contacts the back surface 22 of the substrate 2 through the intrinsic amorphous germanium layer 41 to repair and passivate the dangling bonds and defects on the back surface 22, thereby reducing carrier traps and reducing the surface recombination rate of the carriers. Thereby, the photoelectric conversion efficiency of the solar cell 13 can be improved.

Further, in step 85, the formation temperature of the intrinsic amorphous germanium layer 41 is 200 to 250 ° C, and the formation temperature of the undoped dielectric layer 42 is lower than 200 ° C and lower than the intrinsic amorphous germanium layer 41. The formation temperature, the aforementioned means for using a relatively low process temperature, can reduce the chance of defects being formed in the substrate 2, thereby enabling the substrate 2 to retain the desired material The quality, in turn, reduces the probability of the carrier being recombined during transport in the substrate 2, while the substrate 2 can retain its useful life. In addition, the use of a lower process temperature can also avoid affecting the range in which the dopant elements of the emitter region 24 and the back surface electric field region 25 are diffused and doped into the substrate 2, thereby avoiding problems such as leakage current and component short-circuit. .

In addition, since the emitter region 24 and the back surface electric field region 25 of the present embodiment are formed on the inner side of the back surface 22 of the substrate 2 through a diffusion process, the substrate 2 and the emitter region 24 are formed by the foregoing method. The junction between the substrate and the junction between the substrate 2 and the back surface electric field is a homojunction. In other words, in this embodiment, the homojunction is used instead of the heterojunction structure, and the emitter region 24 obtained by the boron diffusion doping method has a better junction effect.

In summary, the intrinsic amorphous germanium layer 41 of the passivation layer 4 directly covers the emitter region 24, the spacer region 26 and the back surface electric field region 25, thereby improving the passivation effect and carrier collection rate of the substrate 2. Moreover, the parasitic shunt phenomenon of the spacer 26 can be avoided, so that the problem of leakage current and short circuit of the component can be effectively avoided. Therefore, as a whole, the solar cell 13 of the present invention can improve the current collecting efficiency and improve the photoelectric conversion efficiency, so that the object of the present invention can be achieved.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and patent specification content of the present invention, All remain within the scope of the invention patent.

13‧‧‧Solar battery

2‧‧‧Substrate

21‧‧‧Stained surface

22‧‧‧ Back

23‧‧‧ front surface electric field

24‧‧‧The polar zone

25‧‧‧Back surface electric field

26‧‧‧ interval zone

3‧‧‧Anti-reflective layer

4‧‧‧ Passivation layer

41‧‧‧ Essential amorphous layer

42‧‧‧Undoped dielectric layer

43‧‧‧First perforation

44‧‧‧Second perforation

5‧‧‧electrode layer

51‧‧‧First electrode

52‧‧‧second electrode

Claims (6)

A solar cell comprising: a substrate comprising a light receiving surface and a back surface; and a back surface electric field region respectively located on the back surface, a spacer region and an emitter region, the spacer region and the back surface The electric field is spaced apart, wherein the emitter region is formed by a doping method of boron diffusion; a passivation layer is disposed on the back surface; and an electrode layer is disposed on the passivation layer, and the electrode layer passes through the passivation layer a first through hole and a second through hole respectively connecting the emitter region and the back surface electric field region; wherein the passivation layer comprises an intrinsic amorphous germanium layer directly covering the emitter region, The spacer and the back surface electric field region. The solar cell of claim 1, wherein the passivation layer further comprises an undoped dielectric layer directly covering the intrinsic amorphous germanium layer and having a material different from amorphous germanium. A solar cell module comprising: a first plate and a second plate disposed oppositely; and a plurality of solar cells according to any one of claims 1 to 2, arranged on the first plate and the second plate And a package material between the first plate and the second plate and wrapped around the plurality of solar cells. A method of manufacturing a solar cell, comprising: preparing a substrate, the substrate comprising a light receiving surface and a back surface; Forming an emitter region, a spacer region and a back surface electric field region on the back surface of the substrate, and spacing the emitter region from the back surface electric field region; forming a passivation layer on the back surface The passivation layer includes an intrinsic amorphous germanium layer, and the intrinsic amorphous germanium layer directly covers the emitter region, the spacer region and the back surface electric field region; and an electrode layer is formed on the passivation layer, and the electrode is formed The layer is connected to the emitter region and the back surface electric field region through a first through hole and a second through hole of the passivation layer, wherein the passivation layer further comprises an undoped dielectric layer different in material from amorphous germanium. The formation temperature of the undoped dielectric layer is lower than 200 ° C; in the process of forming the passivation layer, the undoped dielectric layer is directly covered on the intrinsic amorphous germanium layer. The method for producing a solar cell according to claim 4, wherein the formation temperature of the intrinsic amorphous germanium layer is 200 to 250 °C. The method of manufacturing a solar cell according to claim 4, wherein the emitter region is produced by a doping method of boron diffusion.