TWI533666B - Power detecting circuit and rf power amplifier, electronic system using the same - Google Patents

Description

Power detection circuit and radio frequency power amplifying circuit and electronic system using same

The present invention relates to a power detection circuit, and more particularly to a power detection circuit capable of simultaneously providing a positive/negative slope voltage curve.

AMPS, PHS, NADC, GSM, DCS, PCS, IS-95, CDMA, WCDMA, DECT, WLAN (802.11), DECT, CT0, CT1, etc., all of which are well known in the industry for wireless networking and personal communication. The standard of the device. Personal communication devices (PCDs) include mobile phones, wireless phones, personal digital assistants (PDAs), walkie-talkie, smart phones, and the like. All of these devices are wireless communication devices (or radio communication devices). The communication link between the PCDs is established by transmitting and receiving radio-frequency signals.

In the wireless communication system, in order to track the current output power of the Power Amplifier in Transmit Mode, enable feedback to the Transceiver system for power. Detection, at this time, a power detection circuit (Power Detector Circuit) is required in the power amplifier, so that the power signal generated by the PA can be converted into a voltage level through the closed loop power detection circuit and then fed back to the transceiver system. in.

Please refer to FIG. 1A and FIG. 1B simultaneously. FIG. 1A can generate a positive slope voltage output. Conventional power detection circuit. FIG. 1B is a schematic diagram corresponding to the positive slope voltage curve of FIG. 1A. The conventional power detecting circuit 100 includes a coupling capacitor CP', a first diode D1, a second diode D2, a capacitor C, and a resistor R. The coupling capacitor CP' is a RF coupling capacitor that allows the RF signal of the RF signal to pass through and can isolate DC at the same time. The second transistor is biased by the system voltage VDD' to generate a forward bias, and then supplied to the first diode D1 bias, and a resistor R is provided to provide a DC bias loop to ground. The diode rectifying circuit comprising the first diode D1, the resistor R and the capacitor C converts the power signal RFD to be coupled from the coupling capacitor CP' to a DC voltage DCOUT and feeds it back to the transceiver circuit. Closed-loop power control is used by pairing with firmware. It can be seen from FIG. 1B that after the voltage curve rectified by the diode power detecting circuit, different input power levels correspond to one voltage value.

In the prior art, the architecture of the above-described two-stage power detection circuit is simple and easy to implement. However, this architecture will not be achieved in the face of the Negative Slope detection voltage approach used by some Main-chip system operators.

The embodiment of the invention provides a power detection circuit for detecting the RF output power of the RF power amplifier circuit and outputting the dual slope voltage accordingly to provide a voltage slope curve requirement of the main chip. The power detection circuit includes a first bias resistor, a first rectifier circuit, and a second rectifier circuit. One end of the first bias resistor is electrically connected to the system voltage. The first rectifying circuit is electrically connected to the other end of the first bias resistor, and the first rectifying circuit is configured to rectify and output a first output voltage according to the first output voltage, wherein the first output voltage is a system voltage minus the first bias resistor The voltage is across and the first output voltage is a negative slope voltage. The second rectifying circuit is electrically connected to the first rectifying circuit to receive the first current, and the second rectifying circuit is configured to receive the power signal to be tested and rectify the power signal to be tested into a DC voltage signal to output a second output voltage, The second output voltage is proportional to the voltage level of the power signal to be tested, when the work to be measured When the rate signal is increased, the first current is increased to increase the voltage across the first bias resistor, thereby reducing the first output voltage, wherein the second output voltage is a positive slope voltage. The power detection circuit is electrically connected to the multiplexer, and the multiplexer receives the first and second output voltages and transmits one of the first and second output voltages to the main chip according to the selection signal, thereby dynamically adjusting the RF power amplification The RF input power of the circuit, in turn, makes the RF output power of the RF power amplifier circuit consistent.

In one embodiment of the present invention, wherein the first current is proportional to the power signal to be tested, the first output voltage is inversely proportional to the first current, and the second output voltage is proportional to the first current, wherein the The power signal is a coupling signal of the RF output power, and the dual slope voltage includes a positive slope voltage and a negative slope voltage.

In one embodiment of the present invention, the first rectifying circuit includes a first rectifying transistor, a first rectifying resistor, and a first rectifying capacitor. The collector of the first rectifying transistor is connected to the other end of the first bias resistor and outputs a first output voltage, and the base of the first rectifying transistor is connected to the system voltage through the second bias resistor, wherein the first and second biases A piezoresistor is used to bias the first rectifying transistor. One end of the first rectifying resistor is connected to the other end of the first bias resistor, and the other end of the first rectifying resistor is connected to the ground voltage. One end of the first rectifying capacitor is connected to the other end of the first bias resistor, and the other end of the first rectifying capacitor is connected to the ground voltage, wherein when the power signal to be tested increases, the first current flows through the first bias resistor The two currents rise correspondingly to increase the voltage across the first bias resistor, thereby lowering the collector voltage of the first rectifying transistor.

In one embodiment of the present invention, the second rectifying circuit includes a second rectifying transistor, a second rectifying resistor, and a second rectifying capacitor. The collector and the base of the second rectifying transistor are connected to each other to form an equivalent diode and connected to the emitter of the first rectifying transistor, and the base of the second rectifying transistor is connected to the power signal to be tested through the coupling capacitor. One end of the second rectifying resistor is connected to the emitter of the second rectifying transistor, and the other end of the second rectifying resistor is connected to the grounding voltage. One end of the second rectifying capacitor is connected to the emitter of the second rectifying transistor, and the other end of the second rectifying capacitor is connected to the ground voltage, wherein the coupling capacitor is coupled through the second rectifying transistor, the second rectifying resistor and the second rectifying capacitor Wait The measured power signal is rectified into a DC voltage signal and the second output voltage is output at an emitter of the second rectifying transistor. When the power signal to be tested increases, the emitter voltage level of the second rectifying transistor rises correspondingly.

The embodiment of the invention further provides a radio frequency power amplifying circuit, the radio frequency power amplifying circuit is electrically connected to a main chip and the radio frequency power amplifying circuit comprises a power amplifier, a power detecting circuit and a multiplexer. The power amplifier is electrically connected to the input matching circuit to receive and amplify the RF input signal, and the power amplifier outputs an RF output signal through an electrical connection output matching circuit. The power detection circuit is configured to detect the RF output power of the power amplifier, and the power detection circuit is electrically connected between the power amplifier and the output matching circuit to receive the power detection signal. The multiplexer is electrically connected between the power detecting circuit and the main chip, and the multiplexer receives the first and second output voltages and transmits one of the first and second output voltages to the main chip according to the selection signal, thereby dynamically adjusting The RF input power of the RF power amplifier circuit, in turn, makes the RF output power of the RF power amplifier circuit consistent.

An embodiment of the present invention further provides an electronic system including a radio frequency power amplifying circuit and a load. The RF power amplifier circuit is configured to receive and amplify the RF input signal, and output the RF output signal accordingly. The load is electrically connected to the RF power amplifier circuit.

In summary, the power detecting circuit and the RF power amplifying circuit and the electronic system using the same according to the embodiments of the present invention directly integrate the power detecting circuit having a positive/negative slope voltage curve on the main chip to provide The voltage slope curve requirements of different main chips can reduce the extra external circuit and reduce the peripheral circuit cost.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

100‧‧‧Finding power detection circuit

200, 300‧‧‧RF power amplifier circuit

700‧‧‧Electronic system

210‧‧‧Power Amplifier

220‧‧‧Input matching circuit

230‧‧‧Output matching circuit

240‧‧‧Power detection circuit

242‧‧‧First rectifier circuit

244‧‧‧Second rectifier circuit

250‧‧‧Multiplexer

260‧‧‧ main chip

710‧‧‧RF power amplifier circuit

720‧‧‧load

CP', CP‧‧‧ coupling capacitor

C‧‧‧ capacitor

C1‧‧‧First rectifying capacitor

C2‧‧‧Secondary rectifying capacitor

D1‧‧‧First Diode

D2‧‧‧ second diode

DCOUT‧‧‧ DC voltage

GND‧‧‧ Grounding voltage

Q1‧‧‧First rectifier crystal

Q2‧‧‧Second rectifier crystal

I1‧‧‧First current

I2‧‧‧second current

R‧‧‧resistance

R1‧‧‧First Rectifier

R2‧‧‧Second rectifier resistor

RB1‧‧‧First Bias Resistor

RB2‧‧‧second bias resistor

RFD’, RFD‧‧‧ power signal to be tested

RFIN‧‧‧RF input signal

RFOUT‧‧‧RF output signal

SEL‧‧‧Select signal

VDD', VDD‧‧‧ system voltage

VRB1‧‧‧cross pressure

VOUT1‧‧‧ first output voltage

VOUT2‧‧‧second output voltage

Figure 1A shows a conventional power detection circuit that produces a positive slope voltage output.

FIG. 1B is a schematic diagram corresponding to the positive slope voltage curve of FIG. 1A.

2 is a block diagram of a radio frequency power amplifying circuit in accordance with an embodiment of the present invention.

3 is a block diagram of a power detection circuit in accordance with an embodiment of the present invention.

4 is a detailed circuit diagram of a power detection circuit in accordance with still another embodiment of the present invention.

Figure 5 is a schematic illustration of a positive slope voltage curve in accordance with an embodiment of the present invention.

6 is a schematic diagram of a negative slope voltage curve in accordance with an embodiment of the present invention.

7 is a block diagram of an electronic system in accordance with an embodiment of the present invention.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be in the In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Similar numbers always indicate similar components.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the term "and/or" includes any of the associated listed items and all combinations of one or more.

In the wireless communication system, in order to be able to track the current output power of the RF power amplifier circuit in the transmission mode and enable it to be fed back to the transceiver system for power detection, the RF power amplifier circuit requires a power. Detection circuit. In practical applications, some main chip system operators will use the power detection circuit of the positive slope voltage curve to detect the current output power, but another part of the main chip system industry will take the power detection circuit of the negative slope voltage curve to detect. a system for measuring the current output power, so a power detection circuit using a positive slope voltage curve The industry needs to add additional circuit area and cost to generate a power detection circuit with a negative slope voltage curve. In order to meet the needs of current system operators, the present disclosure provides a power detection circuit that can be directly integrated on a main chip (a wafer of a radio frequency power amplifier circuit) and can simultaneously provide a positive/negative slope voltage curve to respond to different main chips. Voltage slope curve demand. At least one of the various embodiments will be further described below in order to understand the present disclosure.

[Embodiment of Power Detection Circuit]

Please refer to FIG. 2. FIG. 2 is a block diagram of a radio frequency power amplifying circuit according to an embodiment of the present invention. As shown in FIG. 2, the RF power amplifier circuit 200 includes a power amplifier 210, an input matching circuit 220, an output matching circuit 230, a power detecting circuit 240, and a multiplexer 250. The power amplifier 210 is electrically connected between the input matching circuit 220 and the output matching circuit 230. The power detection circuit 240 is electrically connected to the output of the power amplifier 210. The multiplexer 250 is electrically connected between the power detecting circuit 240 and the main wafer 260.

In the present communication system, when the transceiver is in the transmitting mode, the power amplifier 210 receives the RF input signal RFIN transmitted by the main chip 260 through an input matching circuit 220 and amplifies it, and then transmits it through an output matching circuit 230. The RF output signal RFOUT is connected to an antenna (not shown) for wireless communication. At this time, the power detection circuit 240 detects the current output power of the power amplifier 210 as the power signal RFD to be tested (that is, the power signal RFD to be measured is the coupling signal of the RF output power RFOUT), and the power signal RFD to be tested After being rectified into a DC voltage signal, the first output voltage VOUT1 and the second output voltage VOUT2 are simultaneously outputted to the multiplexer 250, wherein the first output voltage VOUT1 is a negative slope voltage, and the second output voltage VOUT2 is a positive slope voltage. Thereafter, the multiplexer 250 receives the first output voltage VOUT1 and the second output voltage VOUT2 and transmits one of the first and second output voltages VOUT1, VOUT2 to the main wafer according to the selection signal SEL to achieve closed loop power control (Closed-loop power) Control, wherein the selection signal SEL is actively transferred from the main wafer 260 to the multiplexer 250 to allow the output voltage delivered by the multiplexer 250 to conform to the voltage slope curve of the main wafer 260 itself. According to this, to dynamically adjust the RF work The RF input power of the amplifying circuit 200 is increased, and the RF output power of the RF power amplifying circuit 200 is kept consistent.

In order to explain in more detail the operational flow of the power detection circuit 240 of the present invention, at least one of the following embodiments will be further described.

In the following various embodiments, portions different from the above-described embodiment of Fig. 2 will be described, and the remaining omitted portions are the same as those of the above-described embodiment of Fig. 2. In addition, for the sake of convenience, like reference numerals or numerals indicate similar elements.

[Another embodiment of the power detection circuit]

Please refer to FIG. 3. FIG. 3 is a block diagram of a power detection circuit according to an embodiment of the present invention. The power detection circuit 240 of the present disclosure is configured to detect the RF output power of the RF power amplifier circuit 300 (that is, the coupling signal of the current output power of the power amplifier 210 as the power signal RFD to be tested), and output the dual slope voltage accordingly. To provide voltage slope curve requirements for different system main chips, the signal of the dual slope voltage includes a positive slope voltage and the negative slope voltage. As shown in FIG. 3, the power detection circuit 240 includes a first bias resistor RB1, a first rectifier circuit 242, and a second rectifier circuit 244. One end of the first bias resistor RB1 is electrically connected to a system voltage VDD, and the first rectifier circuit 242 is electrically connected to the other end of the first bias resistor RB1 and the multiplexer 250. The second rectifier circuit 244 is electrically connected to the first rectifier circuit 242, the output end of the power amplifier 210, and the multiplexer 250.

The first rectifying circuit 242 is configured to rectify and output the first output voltage VOUT1 to the multiplexer 250 and output the first current I1 to the second rectifying circuit 244, wherein the first output voltage VOUT1 is the system voltage VDD minus the first bias voltage The voltage across the resistor RB1 is VRB1, and the first output voltage VOUT1 is a negative slope voltage. Further, when the power signal RFD to be tested increases and rises, the current of the first current I1 and the current flowing through the first bias resistor RB1 also rises. Therefore, according to Ohm's law, the voltage across the first bias resistor RB1 is increased such that the first output voltage VOUT1 exhibits a characteristic of a negative slope voltage curve.

The second rectifier circuit 244 is configured to receive the power signal RFD to be tested and rectify the power signal RFD to be measured into a DC voltage signal to output a second output voltage VOUT2. The voltage level of the second output voltage VOUT2 relative to the power signal RFD to be tested is In a proportional relationship, when the current output power of the power amplifier 210 rises, that is, when the power signal RFD to be measured increases, the second output voltage VOUT2 also rises, wherein the second output voltage VOUT2 has a positive slope voltage curve. characteristic. Briefly speaking, the first current I1 is proportional to the power signal RFD to be measured, the first output voltage VOUT1 is inversely proportional to the first current I1, and the second output voltage VOUT2 is proportional to the first current I1. The power signal RFD to be tested is a signal that the RF output power RFOUT is not processed by the output matching circuit 230, that is, the power signal RFD to be tested is a coupling signal of the RF output power RFOUT.

What is to be taught next is to further explain the working principle of the power detection circuit 240.

Similarly, in the transmitting mode, the power amplifier 210 of the RF power amplifier circuit 300 receives the RF input signal RFIN transmitted by the main chip 260 through an input matching circuit 220 and amplifies it, and then passes through an output matching circuit 230. The RF output signal RFOUT is output for RF communication. At this time, the present disclosure uses the power detection circuit 240 to immediately detect the current output power of the power amplifier 210. Further, the second rectifier circuit 244 receives the current output power of the power amplifier 210 as the power signal RFD to be tested. When the voltage level of the power signal RFD to be tested rises, the second rectifier circuit 244 not only rectifies the voltage to be measured RFD into a DC voltage, but also outputs a second output voltage VOUT2 having a positive slope voltage curve. At most 250. At this time, that is, when the voltage level of the power signal RFD to be tested rises, the current of the first current I1 and the current flowing through the first bias resistor RB1 is correspondingly increased so that the voltage across the first bias resistor RB1 is VRB1. rise. Because the voltage level of the first output voltage VOUT1 is the system voltage VDD minus the voltage across the first bias resistor RB1, VRB1, the first output voltage VOUT1 will correspondingly decrease as the voltage across the first voltage resistor RB1 increases. Therefore, the first output voltage VOUT1 has a negative slope The characteristics of the rate voltage curve. Next, the multiplexer 250 receives the first output voltage VOUT1 having a negative slope voltage curve and the second output voltage VOUT2 having a positive slope voltage curve, and outputs the demand according to the positive/negative slope voltage curve of the main wafer 260. One of the first output voltage VOUT1 and the second output voltage VOUT2 is applied to the main chip 260 to dynamically adjust the current output power of the power amplifier 210, thereby complying with the requirements of today's communication systems.

For example, when the main chip 260 provided by the system manufacturer has a negative slope voltage curve, the main chip 260 transmits a selection signal SEL (such as digital logic "0") to the multiplexer 250 to enable multiplexing. The processor 250 transmits a first output voltage VOUT1 having a negative slope voltage curve to the main wafer 260. Thereafter, the main chip 260 adjusts the RF input signal RFIN according to a built-in lookup table, that is, generates a corresponding RF input signal RFIN to the RF power amplifier circuit 300. On the other hand, when the main chip 260 provided by the system manufacturer has a demand for a positive slope voltage curve, the main chip 260 transmits a selection signal SEL (such as digital logic "1") to the multiplexer 250 to enable multiplexing. The processor 250 transmits a second output voltage VOUT2 having a positive slope voltage curve to the main wafer 260. Thereafter, the main chip 260 adjusts the RF input signal RFIN according to a built-in lookup table, that is, generates a corresponding RF input signal RFIN to the RF power amplifier circuit 300.

In order to explain in more detail the operational flow of the power detection circuit 240 of the present invention, at least one of the following embodiments will be further described.

In the following various embodiments, portions different from the above-described embodiment of Fig. 3 will be described, and the remaining omitted portions are the same as those of the above-described embodiment of Fig. 3. In addition, for the sake of convenience, like reference numerals or numerals indicate similar elements.

[Further embodiment of power detection circuit]

Please refer to FIG. 4. FIG. 4 is a detailed circuit diagram of a power detecting circuit 240 according to still another embodiment of the present invention. The first rectifying circuit 242 of the power detecting circuit 240 of the present embodiment includes a first rectifying transistor Q1, a first rectifying resistor R1 and a first rectifying capacitor C1. The second rectifier circuit 244 includes a second rectifier transistor Q2, the second rectifying resistor R2 and the second rectifying capacitor C2. The collector of the first rectifying transistor Q1 is connected to the other end of the first bias resistor RB1 and outputs a first output voltage VOUT1. The base of the first rectifying transistor Q1 is connected to the system voltage VDD through the second bias resistor RB2. The first and second bias resistors RB1, RB2 are used to bias the first rectifying transistor Q1. One end of the first rectifying resistor R1 is connected to the other end of the first bias resistor RB1, and the other end of the first rectifying resistor R1 is connected to the ground voltage GND. One end of the first rectifying capacitor C1 is connected to the other end of the first bias resistor RB1, and the other end of the first rectifying capacitor C1 is connected to the ground voltage GND. The collector and the base of the second rectifying transistor Q2 are connected to each other to form an equivalent diode and connected to the emitter of the first rectifying transistor Q1, and the base of the second rectifying transistor Q2 is connected to the to-be-tested through the coupling capacitor CP Power signal RFD. One end of the second rectifying resistor R2 is connected to the emitter of the second rectifying transistor Q2, and the other end of the second rectifying resistor R2 is connected to the grounding voltage GND. One end of the second rectifying capacitor C2 is connected to the emitter of the second rectifying transistor Q2, and the other end of the second rectifying capacitor C2 is connected to the grounding voltage GND.

What is to be taught next is to further explain the working principle of the power detection circuit 240. When the power detecting circuit 240 receives the power signal RFD to be tested through the base of the second rectifying transistor Q2, the second rectifying transistor Q2, the second rectifying resistor and the second rectifying capacitor C2 couple the coupling capacitor CP. The power signal RFD to be tested is rectified into a DC voltage form, and a second output voltage VOUT2 is outputted at the emitter of the second rectifying transistor Q2. At the same time, the first current I1 flows from the emitter of the first rectifying transistor Q1 to the collector of the second transistor Q2, and the first rectifying transistor Q1 is biased by the first bias resistor RB1 and the second bias resistor RB2. Pressed in the active region, and the first bias resistor RB1 has a second current I2 flowing through it, and a cross voltage VRB1 is generated across it. Therefore, as can be seen from FIG. 4, the first output voltage VOUT1 outputted from the collector of the first rectifying transistor Q1 is the system voltage VDD minus the crossover voltage VRB1 of the first bias resistor RB1.

When the voltage level of the power signal RFD to be tested rises or increases, the emitter current of the second transistor Q2 also rises correspondingly, and part of the current of the emitter current of the second transistor Q2 reaches the second rectifying capacitor. C2 is charged to store energy, so according to one The voltage-current relationship of the capacitor, the capacitor voltage on the second rectifying capacitor C2 (ie, the second output voltage VOUT2) will exhibit an exponential rise. Here, please refer to FIG. 4 and FIG. 5 at the same time. FIG. 5 is a schematic diagram of a positive slope voltage curve according to an embodiment of the present invention. In Figure 5, the horizontal axis is the power signal to be measured (in dBm) and the vertical axis is the second output voltage (in volts). As can be seen from FIG. 5, the voltages of the different power signals RFD to be tested correspond to different second output voltages VOUT2, and exhibit an exponential rise trend, so the second output voltage VOUT2 is a positive slope voltage curve. At the same time, when the voltage level of the power signal RFD to be tested rises or increases, the first current I1 and the second current I2 flowing through the first bias resistor RB1 also rise synchronously, thereby making the first bias resistor RB1 The voltage across the voltage VRB1 rises, thereby lowering the collector voltage of the first rectifying transistor Q1. In detail, since the first output voltage VOUT1 is the system voltage VDD minus the voltage across the first bias resistor RB1, when the voltage across the first bias resistor RB1 is increased, the first output voltage VOUT1 is correspondingly decreased. . Further, the first rectifying capacitor C1 discharges the collector terminal of the first rectifying transistor Q1. Please refer to FIG. 4 and FIG. 6 at the same time. FIG. 6 is a schematic diagram of a negative slope voltage curve according to an embodiment of the present invention. In Figure 6, the horizontal axis is the power signal to be measured (in dBm) and the vertical axis is the first output voltage (in volts). As can be seen from FIG. 6, the voltages of the different power signals RFD to be tested correspond to different first output voltages VOUT1, and exhibit an exponentially decreasing trend, so the first output voltage VOUT1 is a negative slope voltage curve. Next, the multiplexer 250 (corresponding to FIG. 3) simultaneously receives the first output voltage VOUT1 having a negative slope voltage curve and the second output voltage VOUT2 having a positive slope voltage curve, and is positive/negative according to the main wafer 260. The demand for the slope voltage curve outputs a control voltage to the power amplifier to dynamically adjust the current output power of the power amplifier 210, thereby accommodating the requirements of the current communication system for the RF power amplifier circuit.

[An embodiment of an electronic system]

Please refer to FIG. 7. FIG. 7 is a block diagram of an electronic system according to an embodiment of the present invention. The electronic system 700 includes a radio frequency power amplifying circuit 710 and a load 720 connected to the radio frequency power amplifying circuit. The RF power amplifying circuit 710 may be in the above embodiment. One of the RF power amplifier circuits 200 and 300 is configured to amplify the received RF input signal RFIN and transmit the RF output signal RFOUT to the load 720.

[Possible effects of the examples]

In summary, the power detecting circuit and the RF power amplifying circuit and the electronic system using the same according to the embodiments of the present invention directly integrate the power detecting circuit having a positive/negative slope voltage curve on the main chip to provide The voltage slope curve requirements of different main chips can reduce the extra external circuit and reduce the peripheral circuit cost.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

240‧‧‧Power detection circuit

242‧‧‧First rectifier circuit

244‧‧‧Second rectifier circuit

CP‧‧‧Coupling Capacitor

C1‧‧‧First rectifying capacitor

C2‧‧‧Secondary rectifying capacitor

GND‧‧‧ Grounding voltage

Q1‧‧‧First rectifier crystal

Q2‧‧‧Second rectifier crystal

I1‧‧‧First current

I2‧‧‧second current

R1‧‧‧First Rectifier

R2‧‧‧Second rectifier resistor

RB1‧‧‧First Bias Resistor

RB2‧‧‧second bias resistor

RFD‧‧‧ power signal to be tested

VDD‧‧‧ system voltage

VRB1‧‧‧cross pressure

VOUT1‧‧‧ first output voltage

VOUT2‧‧‧second output voltage

Claims (10)

A power detection circuit for detecting a radio frequency output power of a radio frequency power amplifying circuit and outputting a dual slope voltage according to the same to provide a voltage slope curve requirement of a main chip, the power detecting circuit comprising: a first bias a voltage resistor, one end of which is electrically connected to a system voltage; a first rectifier circuit electrically connected to the other end of the first bias resistor, the first rectifier circuit is used for rectifying and outputting a first output voltage according to the The first output voltage is the voltage of the system minus the voltage across the first bias resistor, and the first output voltage is a negative slope voltage; and a second rectifier circuit electrically connected to the first rectifier circuit for receiving a first current, the second rectifier circuit is configured to receive a power signal to be tested and rectify the power signal to be tested into a DC voltage signal to output a second output voltage, wherein the second output voltage is relative to the power signal to be tested The voltage level is a proportional relationship. When the power signal to be tested increases, the first current is increased to increase the voltage across the first bias resistor, thereby reducing the first input. a voltage, wherein the second output voltage is a positive slope voltage, wherein the power detection circuit is electrically connected to a multiplexer, the multiplexer receives the first and second output voltages and transmits the signal according to a selection signal One of the first and the second output voltage is applied to the main chip, thereby dynamically adjusting the RF input power of the RF power amplifier circuit, so that the RF output power of the RF power amplifier circuit is consistent. The power detection circuit of claim 1, wherein the first current is proportional to the power signal to be tested, the first output voltage is inversely proportional to the first current, and the second output voltage is Directly proportional to the first current, wherein the power signal to be tested is a coupling signal of the RF output power, and the dual slope voltage includes the positive slope voltage and the negative slope voltage. The power detection circuit of claim 1, wherein the first rectifier circuit comprises: a first rectifying transistor having a collector connected to the other end of the first bias resistor and outputting the first output voltage, the base of which is coupled to the system voltage through a second bias resistor, wherein the first and the first a second bias resistor for biasing the first rectifying transistor; a first rectifying resistor having one end connected to the other end of the first bias resistor, the other end connected to a ground voltage; and a first rectifying capacitor, One end of the first bias resistor is connected to the other end, and the other end is connected to the ground voltage. When the power signal to be tested increases, the first current flows through a second current flowing through the first bias resistor. Correspondingly rising to increase the voltage across the first bias resistor, thereby lowering the collector voltage of the first rectifying transistor. The power detection circuit of claim 3, wherein the second rectifier circuit comprises: a second rectifier transistor, the collector and the base are connected to each other to form an equivalent diode and connect the first An emitter of a rectifying transistor, the base of which is connected to the power signal to be tested through a coupling capacitor; a second rectifying resistor, one end of which is connected to the emitter of the second rectifying transistor, and the other end of which is connected to the ground voltage; And a second rectifying capacitor, one end of which is connected to the emitter of the second rectifying transistor, and the other end of which is connected to the ground voltage, wherein the second rectifying transistor, the second rectifying resistor and the second rectifying capacitor are The power signal to be tested coupled to the coupling capacitor is rectified into a DC voltage signal and outputted to the emitter of the second rectifier transistor, wherein when the power signal to be tested increases, the second rectifier power The emitter voltage level of the crystal will rise correspondingly. An RF power amplifying circuit electrically connected to a main chip, the RF power amplifying circuit comprising: a power amplifier electrically connected to an input matching circuit to receive an RF input The power amplifier is electrically connected to an output matching circuit to output an RF output signal; a power detecting circuit is configured to detect the RF output power of the power amplifier, and the power detecting circuit is electrically Connected to the power amplifier and the output matching circuit to receive a power signal to be tested, the power detecting circuit includes: a first bias resistor, one end of which is electrically connected to a system voltage; a first rectifier circuit, Connected to the other end of the first bias resistor, the first rectifier circuit is configured to rectify and output a first output voltage, wherein the first output voltage is the system voltage minus the crossover of the first bias resistor Pressing, and the first output voltage is a negative slope voltage; and a second rectifier circuit electrically connected to the first rectifier circuit to receive a first current, the second rectifier circuit is configured to receive a power signal to be tested and The power signal to be tested is rectified into a DC voltage signal to output a second output voltage, and the second output voltage is proportional to the voltage level of the power signal to be tested. When the power signal to be tested increases, the first current is increased to increase the voltage across the first bias resistor, thereby reducing the first output voltage, wherein the second output voltage is a positive a slope voltage, a multiplexer electrically connected between the power detecting circuit and the main chip, the multiplexer receiving the first and second output voltages and transmitting the first and second according to a selection signal One of the output voltages is applied to the main chip, thereby dynamically adjusting the RF input power of the RF power amplifier circuit, so that the RF output power of the RF power amplifier circuit is consistent. The radio frequency power amplifying circuit of claim 5, wherein the first current is proportional to the power signal to be tested, the first output voltage is inversely proportional to the first current, and the second output voltage is It is proportional to the first current, wherein the power signal to be tested is a coupling signal of the RF output power. The radio frequency power amplifying circuit of claim 5, wherein the first rectifying circuit comprises: a first rectifying transistor having a collector connected to the other end of the first bias resistor and outputting the first output voltage, the base of which is coupled to the system voltage through a second bias resistor, wherein the first and the first a second bias resistor for providing a bias voltage to the first rectifying transistor; a first rectifying resistor having one end connected to the other end of the first bias resistor and the other end connected to a ground voltage; and a first rectification a capacitor, one end of which is connected to the other end of the first bias resistor, and the other end of which is connected to the ground voltage, wherein when the power signal to be tested increases, the first current flows through one of the first bias resistors The two currents are correspondingly raised to increase the voltage across the first bias resistor, thereby lowering the collector voltage of the first rectifying transistor. The radio frequency power amplifying circuit according to claim 7, wherein the second rectifying circuit comprises: a second rectifying transistor, wherein the collector and the base are connected to each other to form an equivalent diode and connect the first An emitter of a rectifying transistor, the base of which is connected to the power signal to be tested through a coupling capacitor; a second rectifying resistor, one end of which is connected to the emitter of the second rectifying transistor, and the other end of which is connected to the ground voltage; And a second rectifying capacitor, one end of which is connected to the emitter of the second rectifying transistor, and the other end of which is connected to the ground voltage, wherein the second rectifying transistor, the second rectifying resistor and the second rectifying capacitor are The power signal to be tested coupled to the coupling capacitor is rectified into a DC voltage signal and outputted to the emitter of the second rectifier transistor, wherein when the power signal to be tested increases, the second rectifier power The emitter voltage level of the crystal will rise correspondingly. An electronic system comprising: the RF power amplifying circuit as described in claim 5, for receiving an RF input signal and amplifying the same, and outputting an RF output signal accordingly And a load electrically connected to the RF power amplifier circuit. The electronic system of claim 9, wherein the first current is proportional to the power signal to be tested, the first output voltage is inversely proportional to the first current, and the second output voltage is relative to The first current is proportional, wherein the power signal to be tested is a coupling signal of the RF output power.