TWI532166B - Lateral-diffused metal oxide semiconductor device (ldmos) and fabrication method thereof - Google Patents

Description

Laterally diffused MOS device and method of manufacturing same

The present invention relates to a laterally diffused MOS device and a method of fabricating the same, and more particularly to a laterally diffused MOS device having a low On-state resistance (Ron)/Breakdown Voltage (VB) value and Its manufacturing method.

With the development of semiconductor integrated circuit manufacturing technology, there is an increasing demand for components such as control circuits, memory, low-voltage operation circuits, and high-voltage operation circuits formed on a single wafer, and conventional techniques more often utilize insulated gates. An insulated gate bipolar transistor (IGBT) and a double-diffused metal oxide semiconductor (DMOS) device are used as high voltage components in a single wafer.

The double-diffused MOS device can be roughly classified into a laterally diffused MOS device (lateral DMOS, hereinafter referred to as LDMOS) and a vertically diffused MOS device (VDMOS), wherein the LDMOS is compatible with a standard complementary MOS device ( The CMOS) component process has better integration, has better switching efficiency, and is more commonly used in the industry.

Fig. 1 is a schematic cross-sectional view showing a conventional laterally diffused MOS device. As shown in FIG. 1, the laterally diffused MOS device 100 includes a P-type substrate 110, an N-type well 120 disposed in the substrate 110, a field oxide layer 130 disposed on the substrate 110, and a gate 140 disposed on the portion. On the field oxide layer 130, a sidewall 150 is disposed on both sides of the gate 140. A P-type doping region 160 is located in the N-type well 120, and a source 170 is located in the P-type doping region 160 on one side of the sidewall sub-150, and a drain electrode 180 is disposed on the other side of the sidewall sub-150. In the well 120.

When the voltage applied to the gate 140 of the laterally diffused MOS device 100 is greater than a threshold voltage, the laterally diffused MOS device 100 is turned on. At this time, the high voltage signal input from the drain 180 is transmitted to the source 170 via the N-well 120. The N-type well 120 is used as a resistor, so that the high voltage signal flowing through the N-type well 120 generates a voltage drop to become a low voltage signal for internal circuit use. However, since the interface between the P-type doping region 160 and the N-type well 120 has an extreme doping electrical difference, local electric field concentration is caused, resulting in a decrease in breakdown voltage and an increase in on-resistance of the laterally diffused MOS device 100. Therefore, the R/B (on-resistance/crash voltage) value of the conventional laterally diffused MOS device is high. Therefore, there is a need in the industry for a lateral diffusion of MOS components, which can effectively solve the above problems and effectively reduce the R/B value.

The present invention provides a laterally diffused MOS device and a method of fabricating the same, which has a lower R/B value than conventionally known.

The present invention provides a laterally diffused MOS device comprising a substrate, a first deep well region, at least one oxide layer, a gate, a second deep well region, a first doped region, a drain, and a common source pole. The substrate has a first deep well region of a first conductivity type. At least one oxide layer is on the substrate. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well region has a second conductivity type disposed in the substrate and adjacent to the first deep well region. The first doped region has a second conductivity type disposed in the second deep well region, and the doping concentration of the first doping region is higher than the doping concentration of the second deep well region. The drain is placed in the first deep well area outside the gate. The common source is disposed in the first doped region inside the gate.

The present invention provides a laterally diffused MOS device comprising a substrate, an epitaxial layer, a first deep well region, a buried layer, at least one oxide layer, a gate, a second deep well region, and a first doping Zone, a bungee and a common source. The epitaxial layer is on the substrate and has a first deep well region of a first conductivity type. The buried layer is between the substrate and the epitaxial layer. At least one oxide layer is on the epitaxial layer. The gate is disposed on the epitaxial layer and covers a portion of the field oxide layer. The second deep well region has a second conductivity type disposed in the epitaxial layer and adjacent to the first deep well region. The first doped region has a second conductivity type disposed in the second deep well region, and the doping concentration of the first doping region is higher than the doping concentration of the second deep well region. The drain is placed in the first deep well area outside the gate. The common source is disposed in the first doped region inside the gate.

The present invention provides a method of fabricating a laterally diffused MOS device, comprising the following steps. First, a substrate is provided. Next, a first deep well region is formed in the substrate, and the first deep well region has a first conductivity type. Subsequently, a second deep well region is formed in the substrate and adjacent to the first deep well region, and the second deep well region has a second conductivity type. Continued, forming a smash in the first deep well area. Next, at least one oxide layer is formed on the substrate. Successively, a first doped region is formed in the second deep well region, the first doped region has a second conductivity type, and the doping concentration of the first doped region is higher than the doping concentration of the second deep well region. Furthermore, a gate is formed on the substrate between the first doped region and the drain and covers a portion of the field oxide layer. Finally, a common source is formed in the first doped region.

Based on the above, the present invention provides a laterally diffused MOS device and a method of fabricating the same, which has a second deep well region, and the second deep well region has the same electrical conductivity as the first doped region, but the second deep well region is doped The impurity concentration is smaller than the doping concentration of the first doping region, so the laterally diffused MOS device of the present invention has a gradual doping concentration gradient structure, and thus can be lower than the conventional laterally diffused MOS device. R (on resistance) / B (crash voltage) value. Further, the laterally diffused MOS device of the present invention further has a buried layer for use as an insulating layer, and can further prevent a situation in which the current flowing on the buried layer, particularly the second deep well region, flows downward and leaks.

Fig. 2 is a top plan view and a cross-sectional view showing a laterally diffused MOS device according to a first preferred embodiment of the present invention. As shown in FIG. 2 (where (2a) is a top view, (2b) is a cross-sectional view), a laterally diffused MOS device 200 includes a substrate 210, a first deep well region 220, and at least one oxide layer 230. a gate 240, a second deep well region 250, a first doped region 260, a drain 270, and a common source 280. The substrate 210 has a first deep well region 220, wherein the substrate 210 comprises a germanium substrate, a germanium-containing substrate, a germanium insulating substrate or other semiconductor substrate. The field oxide layer 230 is disposed on the substrate 210 and includes a ruthenium dioxide layer, but may also be an insulating structure such as a shallow trench isolation (STI). The invention is not limited thereto. The gate 240 is disposed on the substrate 210 and covers a portion of the field oxide layer 230. The gate 240 may include a gate dielectric layer 242, a gate electrode 244, and a sidewall spacer 246, and may also include a cap layer. The material of the gate 240 is well known in the art and will not be described here.

The first deep well region 220 has a first conductivity type, and the second deep well region 250 has a second conductivity type adjacent to the first deep well region 220 and disposed in the substrate 210, and the substrate 210 preferably has a second conductivity type. Furthermore, in the present embodiment, the first deep well region 220 is located at the periphery of the second deep well region 250, and the first deep well region 220 and the second deep well region 250 do not overlap, but this arrangement is only one embodiment of the present invention. The invention is not limited thereto. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type, but those skilled in the art should know that the first conductivity type may also be different depending on the conductivity type of the transistor to be formed. P type, and the second conductivity type may be N type. The first doping region 260 also has a second conductivity type disposed in the second deep well region 250, and the doping concentration of the first doping region 260 is higher than the doping concentration of the second deep well region 250, thereby forming a The structure of the gradient concentration gradient. The common source 280 is disposed in the first doped region 260 inside the gate 240, and the drain 270 is disposed in the first deep well region outside the gate 240. Thus, the drain 270 is disposed adjacent to the field oxide layer 230 so that when the laterally diffused MOS device 200 is turned on and the high voltage current flows from the drain 270, current can be prevented from flowing through the gate dielectric layer 242 to the gate electrode. 244 causes lateral diffusion of the MOS device 200 to fail. In addition, the drain 270 is disposed around the gate 240, and by using the common source 280, a relatively uniform electric field can be obtained, thereby increasing the breakdown voltage.

It must be emphasized that the gate 240 of the preferred embodiment of the present invention has a racetrack layout shape (e.g., Figure 2a), wherein the gate 240 is disposed by a pair of mutually parallel straight portions and a pair respectively. The curved end portion of the straight portion of the gate 240 is formed by a curved end portion. In other embodiments, the gate 240 may have a rectangular and hollow layout pattern, and the invention is not limited thereto. In addition, in a preferred embodiment, a pair of doped regions 290 having a second conductivity type are further included in the substrate 210 at both ends of the common source 280, and the setting range is corresponding to and partially overlaps the curved end of the gate 240. Part and share source 280. The doping region 290 is arranged to avoid the generation of channels at the end portions of the curved lines, thereby avoiding the generation of an electric field. The interface S1 between the second deep well region 250 and the first deep well region 220 may include a playground runway layout curved surface similar to the curved shape of the playground track layout shape of the gate 240. In a preferred embodiment, the interface S1 between the second deep well region 250 and the first deep well region 220 is located directly below the gate 240. In other words, the interface between the second deep well region 250 and the first deep well region 220 is S1 is located between the drain 270 and the common source 280. Furthermore, the interface S2 of the first doped region 260 and the second deep well region 250 also includes a playground runway layout curved surface, and in a preferred embodiment, the second deep well region 250 intersects with the first doped region 260. The interface S2 is also located directly below the gate 240. In other words, the interface S2 between the second deep well region 250 and the first doping region 260 is also located between the drain 270 and the common source 280, and the interface S1 is surrounded. Interface S2. Thus, by adjusting the concentrations of the first doping region 260, the second deep well region 250, and the first deep well region 220, the internal voltage distribution of the laterally diffused MOS device 200 when it is turned on can be effectively controlled to further improve the lateral diffusion gold. The breakdown voltage of the oxygen semiconductor device 200 and the resistance value thereof are reduced. For example, the present invention is such that the doping concentration of the first doping region 260 is greater than the doping concentration of the second deep well region 250, so that the doping concentration of the first doping region 260 and the second deep well region 250 has a moderate concentration. Doping concentration gradient. Therefore, when a current flows, there is no extreme difference in doping concentration, which can improve the problem of concentration of the electric field distribution, thereby improving the breakdown voltage of the laterally diffused MOS device 200 and reducing its on-resistance. Therefore, the present invention can effectively reduce the R/B (on-resistance/crash voltage) value, and can effectively improve the electrical quality of the laterally diffused MOS device 200.

In a preferred embodiment, only the second deep well region 250 is disposed between the first deep well region 220 and the first doped region 260. In other words, no other components are additionally disposed in the first deep well region 220 and the first blending zone. Between the miscellaneous regions 260, to further avoid the problem that the electric field curve distribution is disordered or the electric field is concentrated in a specific region to reduce the breakdown voltage or increase the on-resistance.

Further, the drain 270 is disposed in the first deep well area outside the gate 240, and may also have a playground runway layout surface. The common source 280 is disposed in the first doping region 260 inside the gate 240. In the design of the circuit layout, the common source 280 is surrounded by the gate 240, and the common source 280 may also be a boat-shaped structure having a playground runway layout curved surface. Furthermore, the common source 280 may further include a second doped region 282 and a plurality of island-shaped third doped regions 284, and the second doped region 282 and the island-shaped third doped region 284 respectively have a first Conductive type and a second conductivity type. In a preferred embodiment, the doping concentration of the second deep well region 250, the first doped region 260, and the island-shaped third doped region 284 is sequentially from island to third. A doped region 260 and a second deep well region 250. As such, a structure having a graded concentration gradient is provided to improve the electrical distribution of the laterally diffused MOS device 200, thereby reducing the R (on-resistance) / B (crash voltage) value of the laterally diffused MOS device 200. In addition, the island-shaped third doping region 284 may be further provided with a plurality of base contact plugs 284a; the second doping region 282 may be further provided with a plurality of source contact plugs 282a for electrically connecting other electronic components. .

Figure 3 is a cross-sectional view showing a laterally diffused MOS device in accordance with a second preferred embodiment of the present invention. As shown in FIG. 3, the difference between the present embodiment and the first embodiment is that the laterally diffused MOS device 300 of the present embodiment further includes an epitaxial layer 310 on the substrate 210, and the first conductivity type. The first deep well region 220 is located in the epitaxial layer 310. Furthermore, the laterally diffused MOS device 300 further includes a buried layer 320 between the substrate 210 and the epitaxial layer 310 for electrically isolating the second deep well region 250 on the buried layer 320 to prevent current flow. Causes leakage. The buried layer 320 can be, for example, a heavily doped region, an N+ buried layer, or an oxide layer. The invention is not limited thereto. In other embodiments, the laterally diffused MOS device 300 may include only one buried layer 320 in the substrate 210 without the placement of the epitaxial layer 310.

4 to 10 illustrate a method of fabricating a laterally diffused MOS device according to a preferred embodiment of the present invention. Hereinafter, a method of fabricating a laterally diffused MOS device will be described by taking a single laterally diffused MOS device as an example, but the practical application of the present invention is not limited to the fabrication of a single laterally diffused MOS device, and the present invention The laterally diffused MOS device can also be fabricated together with other low voltage transistors and the like, and the invention is not limited thereto. In addition, for convenience of explanation, the following is regarded as the first conductivity type by taking the N type as an example, and the P type is regarded as the second conductivity type, but it is well known in the art that the type P is also different depending on the type of the transistor to be formed. It can be regarded as the first conductivity type, and the N type is regarded as the second conductivity type.

As shown in FIG. 4, a substrate 210 is first provided, wherein the substrate is, for example, a germanium substrate, a germanium-containing substrate, or a semiconductor substrate such as a germanium insulating layer. In this embodiment, a P-type germanium substrate is taken as an example, and a buried layer 320 is selectively formed in the substrate 210. The buried layer 320 can be, for example, an N+ heavy ion doped region formed by an N+ heavy ion implantation process. For example, an oxidized insulating layer can be formed by a thermal oxidation process, and the invention is not limited thereto. Next, after the buried layer 320 is formed, an epitaxial layer 310 may be further formed on the substrate 210. The epitaxial layer 310 is formed, for example, by an epitaxial method. However, in other embodiments, it is also possible to form a tantalum-oxide-germanium structure by covering the insulating substrate. At this time, the oxide layer can be used as the buried layer 320 in the present embodiment, and the upper layer of tantalum can correspond to the epitaxial layer 310. Of course, the present invention can also be directly applied to a substrate 210 without additionally forming a buried layer 320 or an epitaxial layer 310, as in the first embodiment.

As shown in FIG. 5, a first deep well region 220 is formed in the epitaxial layer 310, and the first deep well region 220 is an N-type deep well region. For example, the N-type dopant can be implanted first by using an ion implantation process. The epitaxial layer 310 is formed by using a heat treatment process to drive-in the dopant.

As shown in FIG. 6, a second deep well region 250 is formed in the epitaxial layer 310 and adjacent to the first deep well region 220. The second deep well region 250 is, for example, a P-type deep well region, and the second deep well region 250 can be implanted into the first deep well region 220 by using an ion implantation process, for example, and then driven by a heat treatment process (drive- In) formed by doping.

As shown in FIG. 7, a patterned tantalum nitride layer (not shown) is formed on the substrate 210. The patterned tantalum nitride layer is formed, for example, by an etch lithography method to define the position of the field oxide layer 230. Thereafter, an N-type drain 270' is formed, for example, by lithography and ion implantation process P1. Then, the patterned tantalum nitride layer is used as a mask, and an oxidation process is performed to form the field oxide layer 230. The oxide layer 230 is used as an isolation structure, but the isolation structure is not limited to the field oxide layer 230, but may be an insulating material such as a shallow trench isolation (STI). In the present embodiment, the field oxide layer 230 is formed in the first deep well region 220 and protrudes from the surface of the substrate 210. Then, for example, a lithography and ion implantation process P2 is performed to form a P-type first doping region 260 in the second deep well region 250, wherein the doping concentration of the first doping region 260 is higher than that of the second deep well The doping concentration of region 250, thereby forming a graded doping concentration P-type doped structure.

As shown in FIG. 8, a gate dielectric layer 242 and a gate electrode 244 are formed on the substrate 210 between the first doping region 260 and the drain 270', and patterned to cover a portion of the field. The oxide layer 230 has a playground track layout shape. The method of forming the gate dielectric layer 242 and the gate electrode 244 is well known in the art and will not be described herein.

As shown in FIG. 9, a N-type lightly doped drain 270" is formed in the first deep well region 220 on the side of the field oxide layer 230 by, for example, lithography and ion implantation process P3, and simultaneously oxidized in the field. A common source 280' having an N-type light doping is formed in the first doped region 260 on the other side of the layer 230. In addition, a lithography and ion implantation process P4 is also used in the common source 280' to form a plurality of lightly doped P-type island-shaped third doped regions 284 ′, while a portion of the common source 280 ′ that does not perform the lithography and ion implantation process P 4 forms a lightly doped N-type second doped region 282'.

As shown in FIG. 10, a sidewall 246 is formed around the gate electrode 244, for example, by an etch lithography process. Then, a heavily doped N-type drain 270 is formed in the first deep well region 220 on the side of the field oxide layer 230 by using, for example, a lithography and ion implantation process P5, and simultaneously on the other side of the field oxide layer 230. A heavily doped N-type common source (not shown) is formed in the first doped region 260. In addition, a plurality of heavily doped P-type island-shaped third doped regions 284 are formed in the common source by using the lithography and ion implantation process P6, and partial etching of the lithography and ion implantation process P6 is not performed. The source forms a heavily doped N-type second doped region 282, such that the second doped region 282 and the island-shaped third doped region 284 form a common source 280. Thus, the fabrication of the laterally diffused MOS device 200 of the present invention is completed.

In summary, the present invention provides a laterally diffused MOS device and a method of fabricating the same, which has a second deep well region, and the second deep well region has the same electrical properties as the first doped region, and the second deep well region The doping concentration is smaller than the first doping region, so the laterally diffused MOS device of the present invention has a gradual doping concentration gradient structure. In this way, the laterally diffused MOS device of the present invention can solve the difference in doping electrical properties between the first doped region and the first deep well region and the electric field concentration and electrical distribution caused by the difference in doping concentration being too large. A good problem is that the R (on-resistance) / B (crash voltage) value of the laterally diffused MOS device can be reduced, thereby improving the electrical quality. Further, the laterally diffused MOS device of the present invention further has a buried layer for use as an insulating layer, and can further prevent a situation in which the current flowing on the buried layer, particularly the second deep well region, flows downward and leaks.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200, 300. . . Laterally diffused MOS device

110, 210. . . Base

120. . . N-type well

130, 230. . . Field oxide layer

140, 240. . . Gate

150, 246. . . Side wall

160. . . P-doped region

170. . . Source

180, 270, 270', 270"... bungee

220. . . First deep well area

242. . . Gate dielectric layer

244. . . Gate electrode

250. . . Second deep well area

260. . . First doped region

280, 280’. . . Shared source

282, 282’. . . Second doped region

282a. . . Source contact plug

284, 284’. . . Island-shaped third doped region

284a. . . Base contact plug

290. . . Doped region

310. . . Epitaxial layer

320. . . Buried layer

S1, S2. . . Interface

P1, P2, P3, P4, P5. . . Lithography and ion implantation process

Fig. 1 is a schematic cross-sectional view showing a conventional laterally diffused MOS device.

Fig. 2 is a top plan view and a cross-sectional view showing a laterally diffused MOS device according to a first preferred embodiment of the present invention.

Figure 3 is a cross-sectional view showing a laterally diffused MOS device in accordance with a second preferred embodiment of the present invention.

4 to 10 illustrate a method of fabricating a laterally diffused MOS device according to a preferred embodiment of the present invention.

200. . . Laterally diffused MOS device

210. . . Base

220. . . First deep well area

230. . . Field oxide layer

240. . . Gate

242. . . Gate dielectric layer

244. . . Gate electrode

246. . . Side wall

250. . . Second deep well area

260. . . First doped region

270. . . Bungee

280. . . Shared source

282. . . Second doped region

282a. . . Source contact plug

284. . . Island-shaped third doped region

284a. . . Base contact plug

S1, S2. . . Interface

Claims (23)

A laterally diffused MOS device comprising: a substrate having a first deep well region of a first conductivity type; at least one oxide layer on the substrate; and a gate disposed on the substrate and covering a portion of the field An oxide layer; a second deep well region having a second conductivity type disposed in the substrate and adjacent to the first deep well region; a first doped region having a second conductivity type disposed in the second deep well region And the doping concentration of the first doping region is higher than the doping concentration of the second deep well region; a drain is disposed in the first deep well region outside the gate, wherein the gate and the crucible The field oxide layer is disposed on the pole; a lightly doped drain is disposed on the drain; and a common source is disposed in the first doped region inside the gate. The laterally diffused MOS device of claim 1, wherein the gate has a playground track layout shape. The laterally diffused MOS device of claim 2, wherein the interface between the second deep well region and the first deep well region comprises a playground runway layout curved surface. The laterally diffused MOS semiconductor element as described in claim 3 And an interface between the second deep well area and the first deep well area is directly below the gate. The laterally diffused MOS device of claim 2, wherein the interface between the first doped region and the second deep well region comprises a playground runway layout surface. The laterally diffused MOS device of claim 1, wherein only the second deep well region is disposed between the first deep well region and the first doped region. The laterally diffused MOS device of claim 1, wherein the common source further comprises a second doped region and a plurality of island-shaped third doped regions, and the second doped region and the The island-shaped third doped regions respectively have a first conductivity type and a second conductivity type. The laterally diffused MOS device according to claim 7, wherein the doping concentration of the second deep well region, the first doped region and the island-shaped third doped regions are ordered from high to low. The island-shaped third doped region, the first doped region, and the second deep well region. A laterally diffused MOS device comprising: a substrate; An epitaxial layer is disposed on the substrate and has a first deep well region of a first conductivity type; a buried layer is between the substrate and the epitaxial layer; at least one oxide layer is located on the epitaxial layer; a first electrode is disposed on the epitaxial layer and covers a portion of the field oxide layer; a second deep well region having a second conductivity type disposed in the epitaxial layer and adjacent to the first deep well region; a region having a second conductivity type disposed in the second deep well region, wherein a doping concentration of the first doping region is higher than a doping concentration of the second deep well region; a drain is disposed at the gate In the outer first deep well region, wherein the gate electrode and the drain electrode sandwich the field oxide layer; a lightly doped drain is located on the drain; and a common source, the inner side of the gate is disposed In the first doped region. The laterally diffused MOS device of claim 9, wherein the gate has a playground runway layout shape. The laterally diffused MOS device of claim 9, wherein the buried layer comprises a heavily doped region or an N+ buried layer. The laterally diffused MOS device according to claim 10, wherein the interface between the second deep well region and the first deep well region comprises a playground Runway layout surface. The laterally diffused MOS device of claim 12, wherein an interface between the second deep well region and the first deep well region is directly below the gate. The laterally diffused MOS device of claim 10, wherein the interface between the first doped region and the second deep well region comprises a playground runway layout curved surface. The laterally diffused MOS device of claim 9, wherein only the second deep well region is disposed between the first deep well region and the first doped region. The laterally diffused MOS device of claim 9, wherein the common source further comprises a second doped region and a plurality of island-shaped third doped regions, and the second doped region and the The island-shaped third doped regions respectively have a first conductivity type and a second conductivity type. The laterally diffused MOS device according to claim 16, wherein the doping concentration of the second deep well region, the first doped region and the island-shaped third doped regions are high to low. The island-shaped third doped region, the first doped region, and the second deep well region. A method for fabricating a laterally diffused MOS device, comprising: providing a substrate; forming a first deep well region in the substrate, the first deep well region having a first conductivity type; forming a second deep well region on the substrate And adjacent to the first deep well region, the second deep well region has a second conductivity type; forming a drain in the first deep well region; forming at least one oxide layer on the substrate; forming a first doping In the second deep well region, the first doped region has a second conductivity type, and the doping concentration of the first doped region is higher than the doping concentration of the second deep well region; forming a gate, And surrounding the portion of the first doped region and the drain with the field oxide layer, wherein the gate and the drain sandwich the field oxide layer; forming a lightly doped gate Deuterium; and forming a common source in the first doped region. The method of fabricating a laterally diffused MOS device according to claim 18, wherein the gate has a playground runway layout shape. The method of fabricating a laterally diffused MOS device according to claim 18, wherein the substrate comprises a semiconductor substrate and one of the semiconductor layers is formed An epitaxial layer on the conductor substrate, and the first deep well region is located in the epitaxial layer. The method of fabricating a laterally diffused MOS device according to claim 20, wherein the substrate further comprises a buried layer, and the forming step of the substrate comprises: forming the buried layer in the semiconductor substrate; Forming the epitaxial layer on the semiconductor substrate, wherein the buried layer contacts the epitaxial layer. The method of fabricating a laterally diffused MOS device according to claim 21, wherein the buried layer comprises a heavily doped ion implantation process. The method for manufacturing a laterally diffused MOS device according to claim 18, wherein the step of forming the common source further comprises: forming a second doped region and a plurality of island-shaped third doped regions, The second doped region and the island-shaped third doped regions respectively have a first conductivity type and a second conductivity type.