TWI531053B - Semiconductor device and method of manufacturing the same and image sensor device - Google Patents

Description

Semiconductor device and its forming method and image sensing device

The present invention relates to semiconductor devices, and more particularly to their protective structures.

Semiconductor devices have been used in a variety of electronic devices such as personal computers, cell phones, digital cameras, and other electronic devices. The semiconductor device is generally fabricated by sequentially depositing an insulating layer or a dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, a lithographic substrate, and/or a plurality of material layers for patterning or other processes, ie, forming circuit components and The component is on it. Tens or hundreds of integrated circuits can be fabricated on a single semiconductor wafer. Individual dies can be formed by cutting the integrated circuit on the wafer along the dicing line. Individual dies can then be packaged separately, individual dies can be packaged as multiplexed wafer modules, individual dies can be packaged in other ways, or individual dies can be used directly in end applications.

The integrated circuit dies are typically formed on the front side of the semiconductor wafer. The integrated circuit component die can include a variety of electronic components such as transistors, diodes, resistors, capacitors, and other devices. The integrated circuit die can include a variety of functions, such as logic memory, processors, and/or other functions.

A complementary metal oxide half (CMOS) image sensor (CIS) device is a semiconductor device that can be used in certain cameras, cell phones, and other camera devices. The back-illuminated (BSI) image sensor is a CIS device whose mechanism is that the light is from the back of the substrate instead of Frontal incidence. In some applications, the BSI sensor has less reflected light than the orthophoto sensor, so the BSI sensor captures more image signals than the orthophoto sensor.

A semiconductor device according to an embodiment of the present invention includes: a semiconductor wafer including an array region, a peripheral region, and a through hole therein; and a protective structure between the array region and the through hole in the semiconductor wafer, or a perforation and a portion of the peripheral region between.

A method of forming a semiconductor device according to an embodiment of the present invention includes: providing a semiconductor wafer, wherein the semiconductor wafer includes an array region, a peripheral region, and a via hole therein; and forming a protection structure between the array region and the through hole in the semiconductor wafer, Or between the perforation and a portion of the perimeter area.

An image sensing device according to an embodiment of the present invention includes: a first semiconductor wafer including an array region, a peripheral region surrounding the array region, and a first via between the array region and the peripheral region; and the second semiconductor wafer bonded to the first a semiconductor wafer, the second semiconductor wafer includes a second via therein, and the second via is located in the first semiconductor wafer; and a protection structure between the array region and the first via in the first semiconductor wafer, the array region and the second Between the perforations, between a portion of the peripheral region and the first perforation, or between a portion of the peripheral region and the second perforation.

A, B‧‧‧ area

d ₁ ‧‧‧Width

d ₂ ‧‧‧ interval

d ₃ , d ₄ ‧ ‧ depth

W1, W2, Wn‧‧‧ semiconductor wafer

4-4’‧‧‧ Tangent

100‧‧‧Semiconductor device

102a, 102b‧‧‧substrate

104a, 104b‧‧‧Intermetal dielectric layer

106a, 106b‧‧‧ wires

108a, 108b‧‧‧ Guide hole

110, 110', 110a, 110b, 110c‧‧‧ perforation

112‧‧‧Array area

114‧‧‧Intermediate area

116‧‧‧The surrounding area

122‧‧‧ pixel array

124‧‧‧Color filter materials

125‧‧‧Lens material

126, 126’‧‧‧ peripheral devices

128‧‧‧ devices

130, 130’, 130” ‧ ‧ protective structure

110a, 130a‧‧‧Metal structures

130b‧‧‧p-type zone

130c‧‧‧n type area

132a, 132b, 138‧‧‧ insulating materials

136‧‧‧Barrier layer

160‧‧‧Flowchart

162, 164‧ ‧ steps

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a perspective view of a semiconductor device in some embodiments of the present invention.

Figure 2 is a partial cross-sectional view of the semiconductor device of Figure 1 in some embodiments of the present invention.

3 is a protective structure in a semiconductor device in some embodiments of the present invention The top view of the (guard structure).

Figure 4 is a partial cross-sectional view of the semiconductor device of Figure 3 in some embodiments of the present invention.

5 through 7 are top views of various shapes and configurations of protective structures for semiconductor devices in certain embodiments of the present invention.

Figure 8 is a flow diagram of a method of fabricating a semiconductor device in accordance with some embodiments of the present invention.

How to make and use the method of the embodiments of the present invention will be described in detail below. It is to be understood that the invention is not limited by the scope of the invention.

Certain embodiments of the present invention are directed to a semiconductor device, a method of forming the same, and an image sensing device. The following are novel protective structures for semiconductor devices and image sensing devices and methods of forming the same.

1 is a perspective view of a semiconductor device 100 in some embodiments of the present invention. 2 is a partial cross-sectional view of the semiconductor device 100 of FIG. 1 in some embodiments. The semiconductor device 100 includes three semiconductor wafers W1, W2, and Wn bonded together. The semiconductor wafer W1 is bonded to the second semiconductor wafer W2, and the third semiconductor wafer Wn is bonded to the second semiconductor wafer W2. Although there are only three semiconductor wafers W1, W2, and Wn in the drawing, the semiconductor device 100 includes a single semiconductor wafer such as a semiconductor wafer W1, two semiconductor wafers such as semiconductor wafers W1 and W2 (or Wn), or four or more semiconductors. Wafer (not shown).

The semiconductor wafers W1, W2, and Wn can be bonded together by suitable wafer bonding techniques. Some common bonding techniques for wafer bonding include straight Bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reactive bonding, and/or the like. After the semiconductor wafers W1, W2, and Wn are bonded together, the interface between each pair of adjacent semiconductor wafers W1, W2, Wn can provide a conductive path between the stacked semiconductor wafers W1, W2, and Wn. In some embodiments of the direct bonding process, the wires between adjacent semiconductor wafers W1, W2, and Wn may be formed by metal-to-metal bonding (eg, copper-to-copper bonding), dielectric-to-dielectric bonding. Material bonding (e.g., oxide to oxide bonding), metal to dielectric bonding (e.g., oxide to copper bonding), any combination of the foregoing, and/or the like. In some embodiments, the method of bonding at least two adjacent semiconductor wafers W1, W2, and Wn together is a suitable metal-to-dielectric bonding technique, such as a copper-niobium oxynitride bonding technique.

One or more vias 110, 110a, 110b, and 110c may be formed in the semiconductor device 100 to provide a vertical electrical connection of the semiconductor device 100. In some embodiments, semiconductor device 100 includes a plurality of vias 110, 110a, 110b, and 110c. The perforations 110 refer to generally perforations, while the perforations 110a, 110b, and 110c are perforations that extend at different depths in the semiconductor device 100, respectively. The vias 110a extend through at least a portion of the semiconductor wafer W1, such as from the uppermost layer to the lowermost layer of the semiconductor wafer W1, or between the plurality of material layers of the semiconductor wafer W1 to provide a vertical electrical connection of the semiconductor wafer W1. The vias 110b extend through the semiconductor wafer W1 and at least a portion of the semiconductor wafer W2 to provide a vertical electrical connection between the semiconductor wafers W1 and W2. The vias 110c extend through the semiconductor wafers W1 and W2 and at least a portion of the semiconductor wafers Wn to provide a vertical electrical connection between the semiconductor wafers W1 and Wn. Although there are only three perforations 110a in the drawing, 110b, 110c extend through semiconductor wafers W1, W2, and Wn, but other embodiments may have a plurality of vias 110a, 110b, and 110c extending through semiconductor wafers W1, W2, and W3.

The semiconductor wafer W1 includes an array region 112, a peripheral region 116, and at least one of the vias 110, 110a, 110b, and 110c. In some embodiments of the invention, semiconductor wafer W1 includes intermediate region 114 between vias (110, 110a, 110b, and 110c) and array region 112.

Array area 112 includes a plurality of devices formed therein. In some embodiments, the plurality of devices in array region 1120 include a plurality of pixels as shown in FIG. 2, and semiconductor device 100 can be an image sensing device. In some embodiments, semiconductor wafer W1 comprises a pixel array wafer. For example, array region 112 of semiconductor wafer W1 includes pixel array 122. In some embodiments, semiconductor wafer W1 comprises a complementary metal oxide half (CMOS) image sensing (CIS) wafer or device. In some embodiments, semiconductor device 100 includes stacked CMOS image sensing devices.

Figure 2 further illustrates details of portions of the semiconductor wafers W1 and W2. The semiconductor wafer W1 includes a substrate 102a and an inter-metal dielectric layer (IMD) 104a on the substrate 102a. The substrate 102a can be a semiconductor wafer such as germanium or other semiconductor material that can be coated with an insulating layer. The substrate 102a may also include other active components or circuits (not shown). For example, the substrate 102a can comprise yttrium oxide on a single crystal germanium. For example, a semiconductor compound such as gallium arsenide, indium phosphide, antimony alloy, or antimony carbide may be used instead of germanium. For example, the substrate 102a may comprise a germanium on insulator (SOI) or a germanium on insulator (GOI) substrate. In embodiments where the semiconductor wafer W1 includes a CIS wafer, the substrate 102a can include a variety of electronic circuits and/or devices. The electronic circuit formed on the substrate 102a can be suitable for a specific application Any kind. In some embodiments, the electronic circuit can include a plurality of n-type MOS and/or p-type MOS devices, such as transistors, capacitors, resistors, diodes, photodiodes, and fuses. Silk, and/or the like. For example, in some embodiments, semiconductor wafer W1 includes at least one peripheral device 126 (see FIG. 2) in peripheral region 116. Although there is only a single peripheral device 126 in Figure 2, a plurality of peripheral devices 126 can be formed in the peripheral region 116 (see Figure 7). Peripheral device 126 of an embodiment includes a transistor, but peripheral device 126 of other embodiments may include other types of electronic components.

The intermetal dielectric layer 104a includes a plurality of layers of insulating material including a plurality of wires 106a and vias 108a formed therein. The intermetal dielectric layer 104a, the wires 106a, and the vias 108a provide electrical connection of the semiconductor wafer W1 in the horizontal direction and the vertical direction. For example, the insulating material layer of the inter-metal dielectric layer 104a may include yttrium oxide, tantalum nitride, and a low dielectric constant (k) insulating material (having a dielectric constant less than a dielectric constant of yttrium oxide of 3.9), and an ultra-low Dielectric constant (ELK) material (having a dielectric constant less than 3.0), or other kinds of materials. The material of the wire 106a and the via hole 108a may include copper, aluminum, the above alloy, a seed layer, and/or a barrier layer, which may be formed by a damascene process and/or a subtractive etching process. In another embodiment, the intermetal dielectric layer 104a, the wires 106a, and the vias 108a may be other materials and formed by other methods.

In some embodiments, the perimeter region 116 surrounds the array region 112 as shown in FIG. For example, the array region 112 of the semiconductor wafer W1 can be located in a substantial central region of the semiconductor wafer W1, while the peripheral region 116 can be located in an edge region surrounding the array region 112 of the semiconductor wafer W1. The perforations 110, 110a, 110b, 110c are located between the array region 112 and the peripheral region 116. In another embodiment, the array area 112, the peripheral zone 116, and the arrangement of the perforations 110, 110a, 110b, and 110c have other shapes and configurations. In another embodiment, the array region 112 can be located at one corner of the semiconductor wafer W1, and the peripheral region 116 can be located in an L-shaped region adjacent to the array region 112.

In an embodiment where the array region 112 includes a pixel array, the pixel array 122 is formed in the substrate 102a as shown in FIG. In some embodiments, color filter material 124 is formed on pixel array 122 and lens material 125 is formed on color filter material 124. The pixels in the pixel array 122 are used to sense the image received by the pixel array 122. When the semiconductor device 100 is a back-illuminated image sensor, the color filter material 124 can split the light into red, blue, and green primary colors. In some embodiments, color filter material 124 comprises a photosensitive material. In certain embodiments, the lens material 125 can comprise a microlens material. In other embodiments, color filter material 124 and lens material 125 may comprise other materials. In some embodiments, color filter material 124 and/or lens material 125 may be omitted, while array region 112 may comprise other types of devices rather than pixels.

The semiconductor wafer W2 includes a substrate 102b that includes a plurality of devices 128 formed therein. For example, the substrate 102b and the substrate 102a of the semiconductor wafer W1 may comprise the same materials and devices. The semiconductor wafer W2 includes an inter-metal dielectric layer (IMD) 104b, a plurality of wires 106b, and a plurality of via holes 108b formed on the substrate 102b, the material of which is the same as that of the semiconductor wafer W1 described above. In some embodiments, before the semiconductor wafer W1 is bonded to the semiconductor wafer W2, the semiconductor wafer W1 is flipped as shown in FIG.

In some embodiments, the semiconductor wafer Wn and the semiconductor wafers W1 and W2 comprise the same material, such as a substrate, various circuits formed on the substrate, and/or Or devices, interlayer dielectric layers, wires, and vias (not shown).

In some embodiments of the present invention, the protective structure (not shown in FIGS. 1 and 2, see the protective structures 130 in FIGS. 3 and 4) is located in the array region 112 of the semiconductor wafer W1 and the vias 110, 110a, 110b. Between one of 110c, or between one of the peripheral regions 116 and one of the perforations 110, 110a, 110b, and 110c. In some embodiments, the protection structure 130 is included in the semiconductor wafer W1 between the array region 112 and one of the vias 110, 110a, 110b, and 110c, and also in a portion of the peripheral region 116 and the vias 110, 110a. Between 110b and 110c. In some embodiments, the protection structure 130 is located between the array region 112 in the semiconductor wafer W1 and one of the vias 110, 110a, 110b, and 110c (such as in the intermediate region 114), and/or is located in the peripheral region 116. The peripheral device 126 is in between and one of the perforations 110, 110a, 110b, and 110c.

For example, the protective structures 130 of FIGS. 1 and 2 are formed in the semiconductor wafer W1, in the region A of the intermediate region 114 between the array region 112 and one of the vias 110a, 110b, 110c, and 110c. The protective structure 130 is formed in the semiconductor wafer W1, in a portion of the perimeter region 116 or the peripheral device 126 in the peripheral region 116 and in the region B between one of the vias 110a, 110b, 110c, and 110c.

Figure 3 is a top plan view of a semiconductor device having a protective structure 130 therein in some embodiments. In some embodiments, the protective structure 130 includes two (Fig. 3) or more protective structures 130. In the illustrated embodiment, the top view shape of the protective structure 130 in the semiconductor wafer W1 of the semiconductor device 100 is substantially rectangular. When the semiconductor device 100 has a substantially square shape or other shape, the protective structure 130 may have a substantially square shape. In some embodiments, The protective structure 130 includes a ring of a continuous material (or a discontinuous material as shown in the embodiment of FIG. 5) surrounding a predetermined area of the semiconductor wafer 100. The protection structure 130 in FIG. 3 has two parts: the first portion of the protection structure 130 surrounds the array region 112 including the pixel array 122, and is located between the array region 112 and the via 110; the protection of the second portion Structure 130 surrounds perforation 110 and array region 112 and is located between perforation 110 and peripheral device 126 in peripheral region 116. In other embodiments, the number of protective structures 130 can be one, three, or more.

Figure 4 is a cross-sectional view of a portion of semiconductor device 100 along a tangent 4-4' in Figure 3 in some embodiments. The detailed structure of the protective structure 130 in the area A and the protective structure 130 in the area B is as shown in Fig. 4. In some embodiments, the protective structures 130 each comprise a metal structure 130a, a p-type region 130b, an n-type region 130c, or a combination thereof. In some embodiments, the protective structure 130 can comprise only a single metal structure 130a, a single n-type region 130c, a single p-type region 130b, or a combination of two or more thereof. In other embodiments, the protective structure 130 can include a plurality of metal structures 130a, a plurality of p-type regions 130b, a plurality of n-type regions 130c, or a combination thereof.

In embodiments where the protective structure 130 includes the metal structure 130a, the protective structure 130 can include trenches formed in the substrate 102a of the semiconductor wafer W1. Metal structure 130a includes a conductive material located in the trench. For example, the electrically conductive material of the electrically conductive structure 130a can comprise tungsten, copper, copper aluminum alloy, other electrically conductive materials, and/or combinations thereof.

In some embodiments, the trenches including the protective structure 130 of the metal structure 130a may be formed by a lithography process such as forming a photoresist layer (not shown) on the substrate 102a, reflecting or passing the light through the mask. Cover (not shown, with required map The energy developing photoresist layer of the above is removed by patterning the photoresist layer, developing the photoresist layer, and ashing and/or etching to expose or not expose (the end photoresist layer is a positive photoresist or a material photoresist) Part of the photoresist layer. The patterned photoresist layer is then used as an etch mask to etch away portions of the substrate 102a. For example, the patterning step of the substrate 102a of the semiconductor wafer W1 may be earlier or later than the step of bonding the semiconductor wafer W1 to another semiconductor wafer. In other embodiments, the method of forming the trench for the metal structure 130a may be direct patterning, laser drilling, or other processes.

After the step of forming the trenches on the substrate 102a, the material is filled into the trenches. In some embodiments, the material filled into the trench is an insulating material, a conductive material, or a combination thereof. For example, the trench in FIG. 4 is first padded with insulating material 132a to form a conductive material of conductive structure 130a. In some embodiments, the insulating material 132a comprises yttrium oxide, tantalum nitride, hafnium oxynitride, a carbonaceous layer such as tantalum carbide, hafnium oxide, aluminum oxide, tantalum oxide, other insulating materials, or a thickness of from about 1 nm to about 20 μm. Combination or multilayer structure as described above. In other embodiments, there is no insulating material 132a in the trench. A conductive material of the metal structure 130a is then formed on the insulating material 132a in the trench. If the trench does not have the insulating material 132a, the conductive material of the metal structure 130a can be formed directly in the trench. For example, the conductive material can be formed by a sputtering process, electrochemical plating (ECP), physical vapor deposition (PVD), or other methods. For example, the method of removing excess conductive material on the upper surface of the substrate 10a may be a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof. The barrier layer 136 can be located on the upper surface of the metal structure 130a as shown in FIG. In some embodiments, the material of the barrier layer 136 may be an insulating material to prevent the conductive material of the conductive structure 130a from diffusing out to cause contamination. dye. In other embodiments, the barrier layer 136 can be omitted.

The through hole 110a in Fig. 4 is formed in the semiconductor wafer W1. The through hole 110b is formed in the semiconductor wafer W1 and extends into the semiconductor wafer W2, as shown by the broken line. The through hole 110c is formed in the semiconductor wafer formed in the semiconductor wafer W1, extends through the semiconductor wafer W2 and extends into the semiconductor wafer Wn, as shown by the broken line.

In some embodiments, the steps of forming the vias 110a, 110b, and 110c in the semiconductor device 100 may be later than the steps of bonding the semiconductor wafers W1, W2, and Wn. The steps for forming the trenches for the vias 110a, 110b, and 110c may be later than the bonding process. For example, a conductive material such as tungsten, copper, copper aluminum alloy, other conductive materials, and/or combinations thereof, or a multilayer structure as described above, is then filled into the trenches. In some embodiments, prior to the step of forming the conductive material of the vias 110a, 110b, and 110c, the insulating material 138 having a thickness of about 0.5 μm to about 20 μm may be padded, such as hafnium oxide, tantalum nitride, hafnium oxynitride, or the like. A carbon layer such as tantalum carbide, tantalum oxide, aluminum oxide, tantalum oxide, other insulators, or a combination thereof or a multilayer structure as described above is formed in the trench.

In the process of each of the semiconductor wafers W1, W2, and Wn of the other embodiments, the partial vias 110a, 110b, and 110c may be formed earlier than the bonding process. In some embodiments, the partial vias 110a, 110b, and 110c are positioned to align the partial vias 110a, 110b, and 110c with the bonding process of the semiconductor wafers W1, W2, and W3.

In some embodiments in which the protective structure 130 includes the n-type region 130c or the p-type region 130b, the protective structure 130 may be formed by implanting the substrate 102a of the semiconductor wafer W1 and/or epitaxially growing the material in the substrate 102a. Groove to form A p-type material, an n-type material, or a combination thereof. For example, the substrate 102a of the semiconductor wafer W1 may be implanted with a dopant such as boron, arsenic, or phosphorous, or a germanium alloy implanted with boron, arsenic, or phosphorous or a trench of tantalum carbide in the substrate 102a. A protective structure containing an n-type region 130c or a p-type region 130b is formed. In other embodiments, the method of forming the n-type region 130c and the p-type region 130b may be other methods.

The semiconductor wafer W1 may include an insulating material 132b adjacent to the n-type region 130c and the p-type region 130b as shown in FIG. In some embodiments, the insulating material 132b can comprise a shallow trench isolation (STI) region. A contact (not shown) may be located on the upper surface of the n-type region 130c or the p-type region 130b for the protective structure 130 having the metal structure 130a. In some embodiments, at least a portion of the n-type region 130c and the p-type region 130b may be formed together when forming other devices of the semiconductor wafer W1, such as the peripheral device 126. In other embodiments, an additional process may be employed to form n-type region 130c or p-type region 130b.

In some embodiments, the protective structure 130 in the cross-sectional view of FIG. 4 has a width d ₁ greater than or equal to about 0.01 μm. The spacing d _{2 of the} protective structure 130 from the perforations 110a, 110b, or 110c is greater than or equal to about 0.1 μm. In some embodiments, the protective structure 130 has a depth d ₃ or d ₄ from the upper surface of the semiconductor wafer W1 that is between about 0.01 μm and about 100 μm. In the protective structure 130 includes an n-type region or the p-type region 130c 130b another embodiment, the top surface of the semiconductor wafer W1 downward depth d is between about ₃ to about 0.01μm 20μm.

In some embodiments, a voltage can be applied to the protection structure 130 when the semiconductor device 100 is operated. For example, in embodiments where the protective structure 130 includes the metal structure 130a, a voltage of about -10 V to about 10 V can be applied to the metal structure 130a when the semiconductor device 100 is operated. Implementation of the protective structure 130 including the p-type region 130b In an example, a voltage of about 0 V to about 10 V can be applied to the p-type region 130b when the semiconductor device 100 is operated. In embodiments where the protection structure 130 includes the n-type region 130c, a voltage of about 0.1 V to about 10 V can be applied to the n-type region 130c when the semiconductor device 100 is operated. In other embodiments, other voltages may be applied to the protection structure 130 when the semiconductor device 100 is operated. In some embodiments, applying a voltage to the protection structure 130 helps reduce noise of the protection structure. In other embodiments, no voltage may be applied.

There are two protective structures in Figures 3 and 4. In other embodiments, semiconductor device 100 can contain single, two, three, or more protective structures.

5 through 7 are top views of a semiconductor device 100 in certain embodiments, showing various shapes and configurations for semiconductor structures 130, 130', and 130" of semiconductor device 100. In some embodiments, semiconductors The protective structure 130 in the wafer W1 has a substantially square or rectangular shape, as shown in Figures 3, 6, and 7. In other embodiments, the protective structures 130' and 130" in the semiconductor wafer W1 are thereon. The apparent shape is substantially a continuous strip shape, a plurality of continuous strip shapes, a discontinuous strip shape, or a plurality of discontinuous strip shapes (as shown in Fig. 5). In other embodiments, the protective structures 130, 130', and 130" can be a combination of the various shapes described above.

In some embodiments, the protective structure 130 can be in close proximity to or around the array region 112 (as in the embodiments shown in Figures 3 and 5), in close proximity to or around a plurality of perforations 110 (e.g., Figures 3, 5, 6, and 7) The illustrated embodiment), immediately adjacent or surrounding the plurality of perforations 110 and the array region 112 (as in the embodiments illustrated in Figures 3 and 5), in close proximity to or surrounding one of the plurality of perforations 110 (as shown in Figure 6) Embodiments, in close proximity to or around a plurality of perforations 110 (as in the embodiment illustrated in Figure 6), in close proximity to or around one of the plurality of peripheral devices 126 (as in the embodiment illustrated in Figure 7), in close proximity Or surrounding a plurality of peripheral devices 126 One group (as in the embodiment shown in Figure 7), or a combination of the above.

In Fig. 5, the protective structure 130' is substantially in the shape of a continuous strip and is adjacent to the perforations 110. For example, the protective structure 130' extends along each column of vias 110 on each side of the semiconductor wafer 100. For example, the semiconductor device 100 includes a protective structure 130' that includes a plurality of continuous phase strips. The protective structure 130' is located between the via 110 and the array region 112 and/or between the via 110 and the peripheral region 116. In some embodiments, all or some of the protective structures 130' of the semiconductor device 100 are substantially continuous strips in shape.

The shape of the protective structure 130" is substantially a plurality of discontinuous strips and is in close proximity to one of the plurality of perforations 110. For example, the protective structure 130" extends along each column of perforations 110 on each side of the semiconductor device 100. And the protective structure 130" is located between the via 110 and the array region 112, as shown in Figure 5. In other embodiments, the protective structure 130" can be located between the via 110 and the array region 112, and/or located in the via 110. Between the peripheral area 116. In some embodiments, all or some of the protective structures 130" of the semiconductor device 100 are substantially in the shape of a plurality of discontinuous strips.

6 is a set of perforations 110 on the left side of the semiconductor device 100 in some embodiments of the present invention. The top view of the protective structure 130 is substantially rectangular. A portion of the protective structure is between the via 110 and the array region 112, and a portion of the protective structure is between the via 110 and the peripheral region 116. In some embodiments, all or some of the protective structures 130" of the semiconductor device 100 are substantially rectangular in shape and surround a set of perforations 110.

Figure 6 also shows that in some embodiments of the invention, the protective structure 130 surrounds one of the plurality of vias 110' on the upper side of the semiconductor device 100. Protective structure The top view shape of 130 is substantially square. A portion of the protective structure 130 is located between the via 110 and the array region 112, and a portion of the protective structure 130 is located between the via 110 and the peripheral region 116. In some embodiments, all or some of the protective structures 130 of the semiconductor device 100 are substantially square in shape and surround a single or all of the perforations 110.

7 is a set of peripheral devices 126 on the left side of semiconductor device 100 in some embodiments of the present invention. The top view of the protective structure 130 is substantially rectangular. A portion of the protective structure 130 is between the via 110 and the array region 112, and a portion of the protective structure 130 is between the via 110 and the peripheral device 126 in the peripheral region 116. In some embodiments, all or some of the protective structures 130 of the semiconductor device 100 are substantially rectangular in shape and surround a set of peripheral devices 126.

Figure 7 also shows that in some embodiments of the invention, the protective structure 130 surrounds one of the plurality of peripheral devices 126' on the upper side of the semiconductor device 100. The protective structure 130 has a substantially square shape. A portion of the protective structure 130 is between the via 110 and the array region 112, and a portion of the protective structure 130 is between the via 110 and the peripheral device 126 in the peripheral region 116. In some embodiments, all or some of the protective structures 130 of the semiconductor device 100 are substantially square in shape and surround a single or all of the peripheral devices 126.

In the embodiment shown in FIG. 6, the protective structure 130 may instead comprise a continuous strip, a plurality of continuous strips, a discontinuous strip, a plurality of discontinuous strips, and/or Or a combination of the above (as shown in Figure 5) and in close proximity to or around one of a set of perforations 110 or perforations 110'. Similarly, the protective structure 130 of the embodiment of FIG. 7 may instead comprise a continuous strip, a plurality of continuous strips, a discontinuous strip, a plurality of discontinuous strips, and/or Group above The combination (as shown in Figure 5) is adjacent to or surrounding one of a set of peripheral devices 126 or peripheral devices 126'.

In addition, in some embodiments, the protective structure of the semiconductor device 100 can include one or more of the novel protective structures 130, 130', and 130" on the semiconductor device.

Returning to Fig. 4, in some embodiments a combination of metal structure 130a, p-type region 130b, and n-type region 130c can be used to form protective structures 130, 130', 130", which can include a first p-type region 130b, An n-type region 130c adjacent to the first p-type region, and a second p-type region 130b adjacent to the n-type region; a first metal structure 130a, a first p-type region 130b adjacent to the first metal structure 130a, adjacent to the first p-type The n-type region 130c of the region 130b, the second p-type region 130b adjacent to the n-type region, and the second metal structure 130a adjacent to the second p-type region 130b; or the n-type region 130c, the p-type region adjacent to the n-type region 130c 130b, and metal structure 130a adjacent to p-type region 130b. In other embodiments, metal structure 130a, p-type region 130b, and n-type region 130c may be combined into other types to form protective structures 130, 130', and 130".

FIG. 8 is a flow chart 160 of a method of fabricating a semiconductor device 100 in some embodiments. In step 162, a semiconductor wafer W1 (see FIG. 1) is provided that includes an array region 112, a peripheral region 116, and a via 110a formed therein. In step 164, the protective structure 130 is formed between the array region 112 of the semiconductor wafer W1 and the via 110a, or between the via 110a and a portion of the peripheral region 116 (see FIG. 3).

Certain embodiments of the present invention include methods of fabricating the semiconductor device 100, and also include methods of fabricating the novel protective structures 130, 130', and 130". Certain embodiments of the present invention also include protective structures 130, 130', and 130. " Image sensing device.

In some embodiments, the image sensing device includes a stacked complementary gold-oxygen (CMOS) back-illuminated (BSI) image sensing device. In some embodiments, the upper surface of the semiconductor wafer W1 of FIG. 1 includes the back surface of the semiconductor device 100. In these embodiments, the perforations 110 extend from the backside surface through at least a portion of the semiconductor wafer W1. In some embodiments, the protective structure 130 extends from the backside surface through all of the substrate 102a of the semiconductor wafer W1, as shown in FIG.

Advantages of certain embodiments of the present invention include providing novel protection structures 130, 130', and 130" to improve the performance of semiconductor devices and image sensing devices. In some embodiments, protection structures 130, 130', and 130 "Conditional or discontinuous cyclic conductive materials or semiconductor materials" to reduce or improve dark current, white pixels, and noise that may occur in some image sensing applications and other semiconductor devices. The protective structures 130, 130', and 130" reduce charge accumulation due to ground path, noise, and tensile or compressive stress during the process of the via 110. In some applications, a voltage can be applied to the protection structures 130, 130' With 130" to further reduce noise. In other applications, no voltage may be applied to the protective structures 130, 130', and 130". For example, in certain embodiments in which the protective structures 130, 130', and 130" comprise the metal structure 130a, the novel protective structure 130, 130', and 130" can provide a shadowing effect to reduce radio frequency noise. In addition, the novel protective structures 130, 130', and 130" and their designs can be easily implemented in the process.

In some embodiments of the invention, a semiconductor device includes: a semiconductor wafer including an array region, a peripheral region, and a via therein; and a protective structure between the array region and the via in the semiconductor wafer, or a via and a portion Between the surrounding areas.

In some embodiments of the present invention, a method of forming a semiconductor device includes: providing a semiconductor wafer, and the semiconductor wafer includes an array region, a peripheral region, and a via therein; and forming a protective structure between the array region and the via hole in the semiconductor wafer , or between the perforation and a portion of the perimeter area.

In some embodiments of the invention, an image sensing device includes a first semiconductor wafer including an array region, a peripheral region surrounding the array region, and a first via located between the array region and the peripheral region. The image sensing device includes a second semiconductor wafer bonded to the first semiconductor wafer. The second semiconductor wafer includes a second via therein and the second via is also located in the first semiconductor wafer. The protective structure is located between the array region in the first semiconductor wafer and the first via, between the array region and the second via, between a portion of the peripheral region and the first via, or between a portion of the peripheral region and the second via.

While the present invention has been described in terms of certain embodiments and its advantages, it is understood that it is not intended to limit the invention, and may be modified in any way without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. For example, those of ordinary skill in the art may employ a variety of structures, functions, steps, and materials in the scope of the present invention. Further, the scope of the present application is not limited to the process, machine, manufacture, material composition, apparatus, method, and steps in the specific embodiments. Those of ordinary skill in the art can, in accordance with the present invention, employ processes, machines, manufacturing, material compositions, devices, methods, and processes that have substantially the same function or substantially the same results as the above-described embodiments. step. In summary, the scope of the attached patent application is intended to be such Processes, machines, manufacturing, material compositions, devices, methods, and steps are included.

A, B‧‧‧ area

d ₁ ‧‧‧Width

d ₂ ‧‧‧ interval

d ₃ , d ₄ ‧ ‧ depth

W1, W2, Wn‧‧‧ semiconductor wafer

100‧‧‧Semiconductor device

102a‧‧‧Substrate

104a‧‧Metal dielectric layer

110a, 110b, 110c‧‧‧ perforation

112‧‧‧Array area

114‧‧‧Intermediate area

116‧‧‧The surrounding area

122‧‧‧ pixel array

124‧‧‧Color filter materials

125‧‧‧Lens material

126‧‧‧ peripheral devices

130‧‧‧Protective structure

130a‧‧‧Metal structure

130b‧‧‧p-type zone

130c‧‧‧n type area

132a, 132b, 138‧‧‧ insulating materials

136‧‧‧Barrier layer

Claims (9)

A semiconductor device comprising: a semiconductor wafer including an array region, a peripheral region, and a via therein; and a protective structure between the array region and the via in the semiconductor wafer, or the via and portion Between the peripheral regions, wherein the top view shape of the protective structure in the semiconductor wafer is substantially selected from one of the following groups: square, rectangular, continuous strip, plurality of continuous strips, discontinuous strips A plurality of discontinuous strips, in combination with the above. The semiconductor device of claim 1, wherein the semiconductor wafer comprises a first semiconductor wafer, wherein the semiconductor device further comprises a second semiconductor wafer bonded to the first semiconductor wafer, wherein the via is also located at the first In a semiconductor wafer, and wherein the semiconductor device further comprises a third semiconductor wafer bonded to the second semiconductor wafer, and wherein the via is also located in the third semiconductor wafer. The semiconductor device of claim 1, wherein the protection structure comprises a first protection structure between the array region in the semiconductor wafer and the via, and a second protection structure in the semiconductor wafer The perforation is between the peripheral portion and the portion. The semiconductor device of claim 1, wherein the protective structure comprises a metal structure, an n-type region, a p-type region, or a combination thereof. The semiconductor device of claim 1, wherein the semiconductor wafer comprises a plurality of the vias, wherein the semiconductor wafer comprises a plurality of peripheral devices located in the peripheral region, and wherein the protective structure is adjacent to or surrounding the array And adjacent to or surrounding the perforations, adjacent to or surrounding the perforations and the array region, in close proximity to or around one of the perforations, immediately adjacent to or surrounding a plurality of the perforations, in close proximity to or around one of the peripheral devices, in close proximity Or around a set of peripheral devices, or a combination of the above. A method of forming a semiconductor device, comprising: providing a semiconductor wafer, and the semiconductor wafer includes an array region, a peripheral region, and a via hole therein; and forming the array structure and the via hole in the semiconductor wafer Between, or between the perforation and a portion of the peripheral region, the step of forming the protective structure includes: forming a top view shape of the protective structure in the semiconductor wafer from one of the following groups: square, Rectangular, continuous strip, multiple continuous strips, discontinuous strips, multiple discontinuous strips, in combination with the above. The method for forming a semiconductor device according to claim 6, wherein the step of forming the protective structure comprises: (1) implanting the semiconductor wafer and/or epitaxially growing a material to form a p-type material, and n a material, or a combination thereof; or (2) forming a trench in the semiconductor wafer; and filling a trench into the trench, wherein the step of filling the trench into the trench comprises: placing an insulating material, A conductive material, or a combination thereof, is filled into the trench, wherein the conductive material is substantially selected from one of the group consisting of tungsten, copper, aluminum copper alloy, or a combination thereof. An image sensing device includes: a first semiconductor wafer including an array region and a peripheral region surrounding the array And a first via is located between the array region and the peripheral region; a second semiconductor wafer is bonded to the first semiconductor wafer, the second semiconductor wafer includes a second via therein, and the second via is located In the first semiconductor wafer; and a protective structure, between the array region and the first through hole in the first semiconductor wafer, between the array region and the second through hole, and a portion of the peripheral region and the first Between a perforation, or a portion between the peripheral region and the second perforation. The image sensing device of claim 8, wherein when the protection structure comprises a metal structure, the image sensing device is operated to apply a voltage of about -10 V to about 10 V to the metal structure; wherein the protection structure When the p-type region is included, the image sensing device is operated to apply a voltage of about 0 V to about -10 V to the p-type region; or when the protective structure includes an n-type region, the image sensing device is operated to apply the approx. A voltage of 0.1 V to about 10 V is applied to the n-type region.