TWI591949B - Switching Regulator with Ripple-Based Constant ON-Time (RBCOT) and Control Circuit and Control Method Thereof - Google Patents

Description

Switching power supply device with chopping modulation and constant conduction time and control circuit and control method thereof

The invention relates to a switching power supply device with chopping modulation and constant conduction time and a control circuit and a control method thereof, in particular to a chopping modulation constant conduction according to a phase node voltage and adaptively compensating for a chopping slope Time switching power supply and its control circuit and control method.

FIG. 1A shows a schematic circuit diagram of a typical switching power supply 100 having a ripple-based constant ON-time (RBCOT). As shown in FIG. 1A, the switching power supply 100 having a chopping modulation on-time includes a control circuit 110 and a power stage 120. The control circuit 110 includes a comparator 111, a control signal generating circuit 112, and an upper bridge driving circuit 113 and a lower bridge driving circuit 114. The comparator 111 compares the feedback signal Vfb with the reference signal Vref, and generates a comparison signal Comp according to the comparison result. The feedback signal Vfb is obtained by dividing the voltage across the resistors R1 and R2 in series between the output voltage Vout and the ground potential GND. The control signal generating circuit 112 receives the comparison signal Comp and generates control signals CU and CL. The control signal CU is input to the upper bridge driving circuit 113, and the control signal CL is input to the lower bridge driving circuit 114. Control signal CL needs to avoid control signals When CU is high, it is also high. Basically, the control signals CU and CL are mutually inverted signals. The control signal CU is used to maintain a high potential during a fixed on-time (Ton). The upper bridge driving circuit 113 receives the control signal CU to generate the upper bridge driving signal GH, so that the upper bridge switch SWH is turned on in the fixed on-time (Ton) in the power stage 120. The lower bridge driving circuit 114 generates the lower bridge driving signal GL according to the control signal CL, so that the lower bridge switch SWL is not turned on during the fixed on-time (Ton), and is turned on after the fixed on-time (Ton) ends. In short, the power stage 120 switches the upper bridge switch SWH and the lower bridge switch SWL according to the upper bridge driving signal GH and the lower bridge driving signal GL to convert the input voltage Vin into the output voltage Vout. Moreover, the power stage 120 can be a synchronous or non-synchronous step-down, step-up, back-pressure, buck-boost, or step-up power stage circuit, as shown in FIG. 2A-2J.

For the description of the chopping modulation on-time (RBCOT) architecture, please refer to the 1A and 1B diagrams at the same time. The 1B diagram exemplifies the waveform of each signal in the 1A diagram. When the upper bridge driving signal GH is at a low potential and the lower bridge driving signal GL is at a high potential, the upper bridge switch SWH is not turned on, and the feedback signal Vfb related to the output voltage Vout is gradually decreased because the load circuit (not shown) consumes The output voltage Vout causes the output capacitor C1 to discharge, and the resistor R3 represents the equivalent series resistor (ESR) of the output capacitor C1. The reference signal Vref is a preset voltage level, for example, as shown in FIG. 1B, which is a fixed value. When the feedback signal Vfb gradually drops to the reference signal Vre, the comparison signal Comp outputted by the comparator 111 changes from a high potential to a low potential, so that the trigger control signal generating circuit 112 generates a control signal, so that the upper bridge driving signal GH is fixedly turned on. The time Ton is maintained at a high potential, and the upper bridge switch SWH is turned on to charge the output capacitor C1, thereby further fixing the on-time Ton to increase the output voltage Vout. After the fixed on-time Ton ends, the upper bridge driving signal GH changes from a high potential to a low potential, and the lower bridge driving signal GL changes from a low potential to a high potential, that is, the upper bridge switch SWH is not turned on and the lower bridge switch SWL is turned on. At this time, the output capacitor C1 is discharged, thereby reducing the output voltage Vout until the feedback signal Vfb gradually falls below the reference signal Vref, and the comparison signal Comp output by the comparator 111 is changed from the high potential to the low potential, and returns to the above process. , so it works round and round.

In summary, the switching power supply with the chopping modulation on-time (RBCOT) must generate the control signal based on the chopping signal on the output voltage Vout as the trigger control, and the amplitude is too large. Although the wave signal can improve the stability of the circuit, it is easy to exceed the specification limit of the chopping amplitude and the accuracy of the output voltage Vout. The chopping signal with too small amplitude may meet the chopping amplitude specification limit and the output voltage Vout. The requirements of the specification, but it is easy to damage the stability of the circuit caused by the jitter situation, so having a small enough amplitude of the chopping signal while taking into account the stability of the circuit is a challenging task.

In detail, please refer to Figures 3A and 3B. Figure 3A shows that when the ESR resistor R3 of the output capacitor C1 is relatively large, for example, when the output capacitor C1 is an electrolytic capacitor, the inductor current IL and the resistor R3 cross the inductor L. The waveform diagram of the chopping signal VR of the voltage, the chopping signal VC of the output capacitor C1 across the voltage, and the output voltage Vout. The 3B graph shows the waveform of the chopping signal when the ESR resistor R3 of the output capacitor C1 is relatively small, for example, when the output capacitor C1 is a ceramic capacitor. As shown in FIG. 3A, when the ESR resistor R3 of the output capacitor C1 is relatively large, the amplitude of the chopping signal VR across the voltage of the resistor R3 is larger than the chopping signal VC across the output capacitor C1, and thus is superposed as an output voltage. After Vout, its phase is approximately synchronous with the inductor current IL, because the phase between the chopping signal VR and the inductor current IL across the voltage of the resistor R3 is the same. In contrast, when the ESR resistor R3 of the output capacitor C1 is relatively small, as shown in FIG. 3B, the amplitude of the resistor chopping signal VR is small relative to the chopping signal VC, so the phase is superimposed as the output voltage Vout. The difference from the inductor current IL is large. This is because when the ESR resistor R3 of the output capacitor C1 is relatively small, the chopping signal VC dominates the phase of the output voltage Vout, and the chopping signal VC is generated in such a manner that the inductor current IL is greater than the load. When the current ILoad is charged, the output capacitor C1 is charged, and if the output capacitor CI is discharged, the phase difference between the output voltage Vout and the inductor current IL is generated, and the subharmonic oscillation phenomenon is generated, and the amplitude of the output voltage Vout is small. The switching power supply 100 having a chopping-on constant conduction time cannot operate under a stable condition.

As far as today is concerned, the switching power supply for Ripple-Based Constant On-Time (RBCOT) is designed to be streamlined, low cost, and light and heavy. It has high efficiency and is widely used in mobile devices. In order to meet the requirements of mobile devices, the main development goal of this technology is to replace the traditionally used electrolytic capacitors with ceramic capacitors. However, in the case where a ceramic capacitor is applied to the output capacitor, as described above, since the phase of the output capacitor voltage lags behind the inductor current, the ripple modulation on-time (RBCOT) control architecture has subharmonic oscillation. The possibility of occurrence.

In order to eliminate the above-mentioned subharmonic oscillation phenomenon, an improved structure of the applied slope compensation has been proposed by the aforementioned control structure of the chopping modulation on-time (RBCOT). The architecture enhances the voltage signal on the equivalent series resistance (ESR) of the output capacitor by applying a slope compensation method, thereby relatively reducing the phase delay of the output capacitor across the voltage chopping wave compared to the inductor current to eliminate the subharmonic oscillation phenomenon. The circuit is stable. However, the traditional applied slope compensation is designed under certain operating conditions, and the slope circuit with fixed slope is adopted. When the input, output or switching frequency of the system changes, the transient response of the system may be deteriorated, and even instability may occur. In order to solve the above problems, an adaptive slope compensation method is widely proposed, for example, U.S. Patent No. 8,869,475 B2 (hereinafter referred to as reference 1) and U.S. Patent Application No. US20140266112 A1 (hereinafter referred to as reference 2).

In reference 1, the proposed slope compensation signal generating circuit has an input terminal receiving a signal generated by the control signal generating circuit, and an output terminal providing a current signal coupled to the input end of the control signal generating circuit by a resistor. . Among them, the analog current signal flows through the falling phase of the current of the output inductor, thereby eliminating the phase delay effect of the capacitor and making the system stable. When the system works, the system is stabilized and maintains a fast transient response by adjusting the above resistance values.

In Reference 2, the proposed slope compensation signal applied to the switched power supply is generated by the system output voltage signal and the upper bridge switch trigger signal. Among them, the upper bridge switch trigger The number contains information about the system switching frequency and duty cycle. Using the above information, a resistor-capacitor (RC) time constant is controlled by a digital control circuit to generate an adaptively adjusted slope compensation signal.

It can be known from references 1 and 2 that the above adaptive slope compensation mechanism simulates the magnitude of the current flowing through the inductor, and adjusts the resistance-capacitance time constant by self-adjusting the external resistance value or by using a digital circuit to adjust the slope according to the current system operation. Compensation signal. The technical means disclosed in the second conventional invention has a complicated control structure, requires complicated calculation to achieve an adaptive adjustment effect, and cannot be realized by a simple circuit, and the manufacturing cost thereof is compared with a typical chopping modulation on-time. The switching power supply (RBCOT) is high.

Specifically, the way to adjust the external resistor requires an extra pin when designing the integrated circuit. It is not worth recommending from the perspective of cost. And the external resistance value needs to be calculated according to the system operation, which is more complicated. In addition, if the method of adjusting the resistance-capacitance time constant is adopted, it is necessary to calculate the resistance-capacitance (RC) time constant according to the digital circuit calculation, and the hardware implementation is not easy.

In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and proposes a switching power supply device with chopping modulation and constant conduction time, a control circuit thereof and a control method thereof, which can be used in a relatively low equivalent series resistance (ESR). In the case of the adaptive slope compensation circuit, the analog slope compensation circuit can be realized by analog circuit, and no external resistor is needed, no need to detect the output voltage signal, the control structure is simple, the adaptive adjustment can be realized with fewer circuits, and the stable operation is still maintained. A switching power supply device with chopping modulation and constant conduction time, a control circuit thereof and a control method thereof.

In one aspect, the present invention provides a switching power supply having a chopping modulation on-time, comprising: a power stage, switching one of the upper bridge switches according to an upper bridge driving signal, and according to the lower bridge Driving a signal, switching a bridge switch to convert an input voltage into an output voltage, wherein the upper bridge switch and the lower bridge switch are connected in series to a phase node; and a control The circuit generates the upper bridge driving signal and the lower bridge according to one feedback signal related to the output voltage, a phase node voltage of the phase node, and the upper bridge driving signal and/or the lower bridge driving signal a driving signal, wherein the control circuit comprises: a driving signal generating circuit, generating the upper bridge driving signal and the lower bridge driving signal according to the feedback signal and a chopping slope compensation signal; and a chopping slope compensation circuit, The driving signal generating circuit is coupled to generate the chopping slope compensation signal according to the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal.

In a preferred embodiment, the chopper slope compensation circuit includes: an integrator coupled to the driving signal generating circuit for using the phase node voltage and the upper bridge driving signal and/or the lower bridge Driving a signal to generate an integration signal; a sample and hold circuit coupled to the integrator for generating a sample and hold signal according to the integration signal and the upper bridge driving signal and/or the lower bridge driving signal; and a conversion The circuit is coupled to the sample and hold circuit and the driving signal generating circuit for generating the chopping slope compensation signal according to the sampling and holding signal and the upper bridge driving signal and/or the lower bridge driving signal.

In the foregoing embodiment, the integrator preferably includes: an integrating capacitor coupled to the phase node for generating the signal according to the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal An integration signal; and an integration switch, in parallel with the integration capacitor, for switching according to the upper bridge driving signal and/or the lower bridge driving signal, so that the integration signal is related to the input voltage and the on-time switch on-time product.

In a preferred embodiment, the sample and hold circuit includes: a sample and hold capacitor coupled to the integrator for generating the signal according to the integral signal and the upper bridge driving signal and/or the lower bridge driving signal. The sample-and-hold switch is coupled to the sample-and-hold capacitor for switching according to the upper bridge driving signal and/or the lower-bridge driving signal, and controlling the sampling and holding operation to make the sampling holding capacitor Sampling and maintaining the integral signal generated by the integrator.

In a preferred embodiment, the conversion circuit includes: a controlled current source circuit coupled to the sample and hold circuit for generating a charging current according to the sample and hold signal; and a charging circuit The controlled current source circuit is coupled to charge according to the charging current and the upper bridge driving signal and/or the lower bridge driving signal to generate the chopping slope compensation signal.

In another aspect, the present invention provides a control circuit for a switching power supply having a chopping modulation on-time, the switching power supply having a chopping modulation on-time comprising a power stage, Switching one of the upper bridge switches according to an upper bridge driving signal, and switching the lower bridge switch according to the lower bridge driving signal to convert an input voltage into an output voltage, wherein the upper bridge switch is connected in series with the lower bridge switch a phase node; the control circuit generates the upper bridge driver according to one feedback signal related to the output voltage, a phase node voltage of the phase node, and the upper bridge driving signal and/or the lower bridge driving signal a signal and the lower bridge driving signal; the control circuit includes: a driving signal generating circuit, generating the upper bridge driving signal and the lower bridge driving signal according to the feedback signal and a chopping slope compensation signal; and a chopping slope The compensation circuit is coupled to the driving signal generating circuit for using the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal. The raw slope ripple compensation signal.

In a preferred embodiment, the chopper slope compensation circuit includes: an integrator coupled to the driving signal generating circuit for using the phase node voltage and the upper bridge driving signal and/or the lower bridge Driving a signal to generate an integration signal; a sample and hold circuit coupled to the integrator for generating a sample and hold signal according to the integration signal and the upper bridge driving signal and/or the lower bridge driving signal; and a conversion The circuit is coupled to the sample and hold circuit and the driving signal generating circuit for generating the chopping slope compensation signal according to the sampling and holding signal and the upper bridge driving signal and/or the lower bridge driving signal.

In the foregoing embodiment, the integrator preferably includes: an integrating capacitor coupled to the phase node for using the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal No., the integral signal is generated; and an integral switch is connected in parallel with the integral capacitor for switching according to the upper bridge driving signal and/or the lower bridge driving signal, so that the integral signal is related to the input voltage and the upper bridge The product of the switch on time.

In a preferred embodiment, the sample and hold circuit includes: a sample and hold capacitor coupled to the integrator for generating the signal according to the integral signal and the upper bridge driving signal and/or the lower bridge driving signal. The sample-and-hold switch is coupled to the sample-and-hold capacitor for switching according to the upper bridge driving signal and/or the lower-bridge driving signal, and controlling the sampling and holding operation to make the sampling holding capacitor Sampling and maintaining the integral signal generated by the integrator.

In a preferred embodiment, the conversion circuit includes: a controlled current source circuit coupled to the sample and hold circuit for generating a charging current according to the sample and hold signal; and a charging circuit The control current source circuit is coupled to charge according to the charging current and the upper bridge driving signal and/or the lower bridge driving signal to generate the chopping slope compensation signal.

In another aspect, the present invention provides a control method for a switching power supply having a chopping modulation on-time, comprising: switching one of the upper bridge switches according to an upper bridge driving signal, and driving according to the lower bridge a signal, switching a bridge switch to convert an input voltage into an output voltage, wherein the upper bridge switch and the lower bridge switch are connected in series to a phase node; and according to a feedback signal associated with the output voltage, the And generating, by the one of the phase node, the phase node voltage, the uplink drive signal, and/or the lower bridge drive signal, the upper bridge drive signal and the lower bridge drive signal; wherein the feedback is performed according to one of the output voltages And generating, by the signal, the phase node voltage of the phase node, and the uplink driving signal and/or the lower bridge driving signal, the step of generating the upper bridge driving signal and the lower bridge driving signal, including: according to the feedback signal a chopping slope compensation signal, generating the upper bridge driving signal and the lower bridge driving signal; and according to the phase node voltage and the upper bridge driving signal and/or the lower Driving signal generating the ripple compensation signal slope.

In a preferred embodiment, the step of generating the chopping slope compensation signal according to the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal comprises: according to the phase node voltage and the The upper bridge driving signal and/or the lower bridge driving signal generates an integration signal; generating a sample and hold signal according to the integration signal and the upper bridge driving signal and/or the lower bridge driving signal; and maintaining the signal according to the sampling The upper bridge driving signal and/or the lower bridge driving signal generate the chopping slope compensation signal.

In the foregoing embodiment, the step of generating an integration signal according to the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal preferably includes: according to the phase node voltage and the upper bridge driving And generating the integration signal by the signal and/or the lower bridge driving signal; and switching according to the upper bridge driving signal and/or the lower bridge driving signal, so that the integral signal is related to the input voltage and the on-time switch on-time product.

In a preferred embodiment, the step of generating a sample and hold signal according to the phase node voltage and the integrated signal comprises: generating, according to the integrated signal and the upper bridge driving signal and/or the lower bridge driving signal The sampling and holding signal; and switching according to the upper bridge driving signal and/or the lower bridge driving signal, and controlling the sampling and holding operation, so that the sampling holding capacitor samples and maintains the integral signal generated by the integrator.

In a preferred embodiment, the step of generating the chopping slope compensation signal according to the sample and hold signal and the upper bridge driving signal and/or the lower bridge driving signal comprises: generating a signal according to the sampling and holding signal Charging current; and charging according to the charging current and the upper bridge driving signal and/or the lower bridge driving signal to generate the chopping slope compensation signal.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

10‧‧‧Load circuit

20‧‧‧Return circuit

100,200‧‧‧Switching power supply with chopping and turn-on time

110,210‧‧‧Control circuit

111‧‧‧ comparator

112‧‧‧Control signal generation circuit

113‧‧‧Upper bridge drive circuit

114‧‧‧Bridge drive circuit

120,220‧‧‧Power level

211‧‧‧Drive signal generation circuit

213‧‧‧Chopper slope compensation circuit

2111‧‧‧Comparative circuit

2113‧‧‧ drive circuit

2131‧‧‧ integrator

2133‧‧‧Sampling and holding circuit

2135‧‧‧Transition circuit

2136‧‧‧Charging circuit

C1‧‧‧ output capacitor

CCS‧‧‧ controlled current source circuit

CL, CU‧‧‧ control signal

Comp‧‧‧ comparison signal

CPH‧‧‧ integral capacitor

Cr‧‧‧ capacitor

CSH‧‧‧Sampling and holding capacitor

DPH, DSH‧‧‧ drive

GH‧‧‧Upper Bridge Drive Signal

GL‧‧‧Bridge Drive Signal

GND‧‧‧ Ground potential

IL‧‧‧Inductor Current

ILoad‧‧‧Load current

Kr‧‧ parameters

L‧‧‧Inductance

PH‧‧‧ phase node

R1, R2, R3, Rr‧‧‧ resistance

RPH‧‧‧ integral resistance

SPH‧‧·integral switch

SWR‧‧ switch

V1‧‧·point signal

V2‧‧‧Sampling and Keeping Signals

VC, VR‧‧‧ chopping signal

Vfb‧‧‧ feedback signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

VPH‧‧‧phase node voltage

Vramp‧‧‧ chop slope compensation signal

Vref‧‧‧ reference signal

SSH‧‧‧Sampling hold switch

SWH‧‧‧Upper Bridge Switch

SWL‧‧‧Bridge switch

FIG. 1A shows a schematic circuit diagram of a typical switching power supply 100 having a ripple-based constant ON-time (RBCOT).

Fig. 1B shows an example of the waveform of each signal in Fig. 1A.

2A-2J shows a synchronous or non-synchronous step-down, step-up, back-pressure type, buck-boost type, and step-up type conversion circuit.

3A and 3B respectively show a typical switching power supply 100 having a chopping modulation on-time, when the ESR resistance R3 of the output capacitor C1 is relatively large (electrolyte capacitance) and small (ceramic capacitance), A schematic diagram of the waveform of each chopping signal.

Figure 4 shows an embodiment of a switched power supply 200 having chopping modulation on-time according to the present invention.

5A-5D show the waveforms of the signals in the switching power supply 200 of the present invention having the chopping modulation on-time.

6A-6B shows a more specific embodiment of the switching power supply 200 of the present invention having a chopping modulation on-time.

Figures 7A-7C show the waveforms of the signals during operation in Figures 6A-6B.

The drawings in the present invention are schematic, mainly intended to indicate the coupling relationship between the circuits, and the relationship between the signal waveforms, and the circuit, signal waveform and frequency are not drawn to scale.

Figure 4 shows an embodiment of a switched power supply 200 having chopping modulation on-time according to the present invention. The AC voltage is rectified via a rectifying circuit to produce an input voltage Vin (not shown, which is well known to those of ordinary skill in the art and will not be described herein). The rectifier circuit is, for example, a bridge rectifier circuit. As shown in FIG. 4, the switching power supply 200 having the chopping modulation on-time includes control Circuitry 210 and power stage 220. The power stage 220 can be a synchronous or non-synchronous step-down, step-up, back-pressure, buck-boost, or step-up power stage circuit, as shown in Figure 2A-2J. The power stage 220 switches the upper bridge switch SWH according to the upper bridge driving signal GH; the power stage 220 switches the lower bridge switch SWL according to the lower bridge driving signal SWL to convert the input voltage Vin into the output voltage Vout. As shown in FIG. 4, the upper bridge switch SWH and the lower bridge switch SWL are connected in series to the phase node PH. It should be noted that the so-called upper bridge switch SWH and the lower bridge switch SWL are connected in series with the phase node PH, that is, the upper bridge switch SWH and the lower bridge switch SWL are connected to each other along a single current path, and the phase node PH is the upper bridge switch SWH and The connection point between the lower bridge switches SWL. The control circuit 210 generates the upper bridge driving signal GH and the lower bridge driving according to the feedback signal Vfb related to the output voltage Vout, the phase node voltage VPH of the phase node PH, and the upper bridge driving signal SWH and/or the lower bridge driving signal SWL. Signal GL. It should be noted that the upper bridge driving signal SWH and the lower bridge driving signal SWL are substantially mutually inverted signals, and the lower bridge driving signal SWL is substantially generated after the upper bridge driving signal SWH is inverted; When the switch SWH is turned on, the lower bridge switch SWL is not turned on (depending on the need, a double dead time between the upper bridge switch SWH and the lower bridge switch SWL can be arranged to avoid the penetration time (to avoid penetration) Shoot through)), which is well known to those of ordinary skill in the art, and will not be described herein.

The control circuit 210 includes a drive signal generating circuit 211 and a chopping slope compensation circuit 213. As shown in the figure, the driving signal generating circuit 211 generates the upper bridge driving signal GH and the lower bridge driving signal GL according to the feedback signal Vfb and the chopping slope compensation signal Vramp. The chopper slope compensation circuit 213 is coupled to the driving signal generating circuit 211 for generating a chopping slope compensation signal Vramp according to the phase node voltage VPH and the upper bridge driving signal GH. The chopping slope compensation circuit 213 can also generate the chopping slope compensation signal Vramp according to the phase node voltage VPH and the upper bridge driving signal GH and/or the lower bridge driving signal GL. As described above, the upper bridge driving signal SWH and the lower bridge driving signal SWL are substantially mutually inverted signals. Therefore, the chopping slope compensation circuit 213 can also be connected to the upper bridge driving signal GH and/or according to the phase node voltage VPH. The lower bridge driving signal GL generates a chopping slope compensation signal Vramp. It should be noted that with the output voltage Vout The associated feedback signal Vfb does not have to be generated by the voltage divider circuit receiving the output voltage Vout, and may also be the output voltage Vout itself.

5A-5D shows the phase node voltage VPH, the integrated signal V1, the sample and hold signal V2, and the chopping slope compensation signal Vramp in the switching power supply 200 having the chopping modulation on-time. Signal waveform diagram. As shown, the switched power supply 200 with chopping modulation on-time according to the present invention has a ripple-based constant ON-time (RBCOT) architecture when related to the output. When the feedback signal Vfb of the voltage Vout is subtracted from the level of the wave slope compensation signal Vramp and gradually drops to the reference signal Vref, the upper bridge driving signal GH is changed from a low potential to a high potential, for example, and is maintained at a fixed on-time Ton. The high potential turns on the upper bridge switch SWH to charge the output capacitor C1, and further increases the output voltage Vout by the fixed on-time Ton. At this fixed on-time Ton, the integral signal V1 also rises, and the sample-and-hold signal V2 also rises after resetting, as will be detailed later. After the fixed on-time Ton ends, the upper bridge driving signal GH changes from a high potential to a low potential, and the lower bridge driving signal GL changes from a low potential to a high potential, that is, the upper bridge switch SWH is not turned on and the lower bridge switch SWL is turned on. At this time, the output capacitor C1 is discharged, thereby reducing the output voltage Vout, until the feedback signal Vfb minus the level of the chopping slope compensation signal Vramp, and gradually falling below the reference signal Vref, so that the upper bridge driving signal GH is again low-level, for example. Change to high potential, go back to the above process, and work back and forth. The invention obtains the phase node voltage VPH on the phase node PH, and converts the time point according to the level of the upper bridge driving signal GH and/or the lower bridge driving signal GL to adaptively adjust the chopping slope compensation signal Vramp, thereby generating the upper bridge. The drive signal GH and the lower bridge drive signal GL.

6A-6B shows a more specific embodiment of the switching power supply 200 of the present invention having a chopping modulation on-time. As shown in FIG. 6A, the drive signal generating circuit 211 includes a comparison circuit 2111 and a drive circuit 2113. The comparison circuit 2111 compares the feedback signal Vfb, the chop slope compensation signal Vramp, and the reference signal Vref related to the output voltage Vout, and inputs the comparison result to the drive circuit 2113. The driving circuit 2113 generates an upper bridge driving signal GH and a lower bridge driving signal GL according to the comparison result.

As shown in FIG. 6B, the chopper slope compensation circuit 213 includes an integrator 2131, a sample hold circuit 2133, and a conversion circuit 2135. The integrator 2131 is coupled to the driving signal generating circuit 211 for generating the integral signal V1 according to the phase node voltage VPH and the upper bridge driving signal GH and/or the lower bridge driving signal GL; the sampling and holding circuit 2133 is coupled with the integrator 2131. Connected to generate a sample and hold signal V2 according to the upper bridge driving signal GH and the integral signal V1; and a conversion circuit 2135 coupled to the sample and hold circuit 2133 and the driving signal generating circuit 211 for maintaining the signal V2 and the upper bridge according to the sample The driving signal GH and/or the lower bridge driving signal GL generates a chopping slope compensation signal Vramp.

As shown in FIG. 6B, the integrator 2131 includes an integrating capacitor CPH, an integrating switch SPH, an integrating resistor RPH, and a driver DPH. The integrating capacitor CPH is coupled to the phase node PH for generating the integral signal V1 according to the phase node voltage VPH and the upper bridge driving signal GH and/or the lower bridge driving signal GL. The integrating switch SPH is connected in parallel with the integrating capacitor CPH for switching according to the upper bridge driving signal GH and/or the lower bridge driving signal GL, so that the integral signal V1 is related to the product of the input voltage Vout and the fixed on-time Ton of the upper bridge switch SWH. The node voltage VPH is input to the integrating capacitor CPH through the integral resistor RPH. In the embodiment, the integrating switch SPH is switched according to, for example, the lower bridge driving signal GL, so that the integrating capacitor CPH is charged according to the time when the lower bridge switch SWL is not turned on (substantially That is, charging is performed for the time when the upper bridge switch SWH is turned on, and the result of the integration is passed through the driver DPH to be input to the sample hold circuit 2133.

As shown in FIG. 6B, the sample hold circuit 2133 includes a sample hold capacitor CSH, a sample hold switch SSH, and a driver DSH. The sample and hold capacitor CSH is coupled to the integrator 2131 for generating the sample and hold signal V2 according to the integral signal V1 and the upper bridge drive signal GH and/or the lower bridge drive signal GL. The sample and hold switch SSH is coupled to the sample and hold capacitor CSH for switching according to the upper bridge drive signal GH and/or the lower bridge drive signal GL, and controls the sampling and holding operation, so that the sample and hold capacitor CSH samples and maintains the integrator 2131. The resulting integral signal V1. As shown in the figure, the sample and hold capacitor CSH is coupled to the sample hold switch SSH, wherein the sample hold switch SSH is operated according to the upper bridge drive signal GH, so that the sample is saved. Holding the capacitor CSH at the time when the upper bridge switch SWH is turned on, the sample keeps the integral signal V1 generated by the integrator 2131, and generates the sample hold signal V2.

As shown in FIG. 6B, the conversion circuit 2135 includes a controlled current source circuit CCS and a charging circuit 2136. Wherein, the controlled current source circuit CCS, such as but not limited to the current control current source as shown, the potential difference between the sample and hold signal V2 and the ground potential GND, the current generated by the resistor Rr, via the parameter Kr and a current source The generated current is controlled by the switch SWR in the charging circuit 2136 according to the upper bridge driving signal GH, thereby charging the capacitor Cr in the charging circuit 2136, thereby generating a chopping slope compensation signal Vramp. The controlled current source circuit CCS is coupled to the sample and hold circuit 2133 for generating a charging current according to the sample hold signal V2. The charging circuit 2136 is coupled to the controlled current source circuit CCS for charging according to the charging current and the upper bridge driving signal GH and/or the lower bridge driving signal GL to generate the chopping slope compensation signal Vramp.

Figures 7A-7C show the waveforms of the signals during operation in Figures 6A-6B. FIG. 7A is a schematic diagram showing the signal waveform of the feedback signal Vfb corresponding to the output voltage Vout, the feedback signal Vfb minus the chopping slope compensation signal Vramp, and the reference signal Vref. When the result of the feedback signal Vfb minus the chopping slope compensation signal Vramp falls to the reference signal Vref, as shown in FIG. 7C, the upper bridge driving signal GH changes from a low level to a high level, and is maintained at a high level for a fixed on time. Ton. After the upper bridge driving signal GH is changed from the high level to the low level, the chopping slope compensation circuit 213 continues to generate the chopping slope compensation signal Vramp according to the phase voltage VPH, so that the chopping slope compensation signal Vramp is subtracted from the feedback signal Vfb. The level is gradually lowered to be lower than the reference signal Vref, so that the upper bridge driving signal GH is changed from a low potential to a high potential, for example, and returns to the foregoing process, so that it operates repeatedly.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, in the embodiments, two circuits or components that are directly connected are interposed, and other circuits or elements that do not affect the main function can be inserted. Therefore, "coupling" should be considered to include both direct and indirect connections. For another example, the resistor or the voltage dividing circuit is not limited to the resistor element, and may be replaced by other circuits such as a transistor circuit. For another example, the positive and negative terminals of the comparison circuit can be interchanged, and only need to modify the meaning of the relevant circuit or the level of the signal; and, for example, the signal outside the control circuit (such as but not limited to the feedback signal) is taken in. When the control circuit performs processing or calculation, it may undergo voltage-current conversion, current-voltage conversion, proportional conversion, etc. Therefore, the term "processing or operation according to a signal" as used in the present invention is not limited to the signal itself, but is also included in If necessary, the signal is subjected to the above conversion, and then processed or calculated according to the converted signal. As another example, variations in all embodiments can be employed interchangeably, and the like. All such modifications may be made in accordance with the teachings of the present invention, and the scope of the present invention should be construed to cover the above and other equivalents.

10‧‧‧Load circuit

20‧‧‧Return circuit

200‧‧‧Switching power supply with chopping and turn-on time

210‧‧‧Control circuit

211‧‧‧Drive signal generation circuit

213‧‧‧Chopper slope compensation circuit

220‧‧‧Power level

2131‧‧‧ integrator

2133‧‧‧Sampling and holding circuit

2135‧‧‧Transition circuit

GH‧‧‧Upper Bridge Drive Signal

GL‧‧‧Bridge Drive Signal

GND‧‧‧ Ground potential

IL‧‧‧Inductor Current

L‧‧‧Inductance

PH‧‧‧ phase node

V1‧‧·point signal

V2‧‧‧Sampling and Keeping Signals

Vfb‧‧‧ feedback signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

VPH‧‧‧phase node voltage

Vramp‧‧‧ chop slope compensation signal

SWH‧‧‧Upper Bridge Switch

SWL‧‧‧Bridge switch

Claims (12)

A switching power supply device with chopping modulation and constant conduction time, comprising: a power level, switching one of the upper bridge switches according to an upper bridge driving signal, and switching the lower bridge switch according to the lower bridge driving signal, Converting an input voltage into an output voltage, wherein the upper bridge switch and the lower bridge switch are connected in series to a phase node; and a control circuit, according to one of the feedback signals associated with the output voltage, one phase of the phase node Generating the upper bridge driving signal and the lower bridge driving signal by the node voltage, the upper bridge driving signal and/or the lower bridge driving signal; wherein the control circuit comprises: a driving signal generating circuit, according to the feedback signal And a chopping slope compensation signal, generating the upper bridge driving signal and the lower bridge driving signal; and a chopping slope compensation circuit coupled to the driving signal generating circuit for driving according to the phase node voltage and the upper bridge The signal and/or the lower bridge driving signal generates the chopping slope compensation signal; wherein the chopping slope compensation circuit comprises: an integrator, and the driving The signal generating circuit is coupled to generate an integral signal according to the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal; a sample and hold circuit coupled to the integrator for a signal and the upper bridge driving signal and/or the lower bridge driving signal to generate a sample and hold signal; and a conversion circuit coupled to the sample and hold circuit and the driving signal generating circuit for maintaining the signal according to the sampling The chopping slope compensation signal is generated by the upper bridge driving signal and/or the lower bridge driving signal. A switching power supply having a chopping modulation on-time as described in claim 1 wherein the integrator comprises: An integrating capacitor coupled to the phase node for generating the integrated signal according to the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal; and an integrating switch connected in parallel with the integrating capacitor Switching according to the upper bridge driving signal and/or the lower bridge driving signal, so that the integral signal is related to the product of the input voltage and the on-switch open time. A switching power supply device having a chopping modulation on-time as described in claim 1, wherein the sample-and-hold circuit includes: a sample-and-hold capacitor coupled to the integrator for receiving the integrated signal And the upper bridge driving signal and/or the lower bridge driving signal generating the sampling and holding signal; and a sampling and holding switch coupled to the sampling and holding capacitor for driving the signal according to the upper bridge and/or the lower bridge driving The signal is switched, and the sampling and holding operations are controlled such that the sample-and-hold capacitor samples and maintains the integral signal generated by the integrator. A switching power supply device having a chopping modulation on-time as described in claim 1, wherein the conversion circuit includes: a controlled current source circuit coupled to the sample and hold circuit for And sampling a hold signal to generate a charging current; and a charging circuit coupled to the controlled current source circuit for charging according to the charging current and the upper bridge driving signal and/or the lower bridge driving signal to generate the Chopper slope compensation signal. A control circuit for a switching power supply having a chopping modulation on-time, the switching power supply having a chopping modulation on-time includes a power stage that switches one of the signals according to an upper bridge driving signal The upper bridge switch, and according to the bridge driving signal, switching the lower bridge switch to convert an input voltage into an output voltage, wherein the upper bridge switch and the lower bridge switch are connected in series to a phase node; the control circuit is based on One of the output voltage correlations a signal, a phase node voltage of the phase node, and the upper bridge driving signal and/or the lower bridge driving signal to generate the upper bridge driving signal and the lower bridge driving signal; the control circuit comprises: a driving signal generating circuit And generating, according to the feedback signal and a chopping slope compensation signal, the upper bridge driving signal and the lower bridge driving signal; and a chopping slope compensation circuit coupled to the driving signal generating circuit for using the phase node according to the phase node The chopping slope compensation signal is generated by the voltage and the upper bridge driving signal and/or the lower bridge driving signal; wherein the chopping slope compensation circuit includes: an integrator coupled to the driving signal generating circuit for The phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal generate an integration signal; a sample and hold circuit coupled to the integrator for using the integral signal and the upper bridge driving signal and/or The lower bridge driving signal generates a sample and hold signal; and a conversion circuit coupled to the sample and hold circuit and the driving signal generating circuit for sampling according to the sampling The chopping slope compensation signal is generated by the hold signal and the upper bridge drive signal and/or the lower bridge drive signal. A control circuit for a switching power supply having a chopping modulation on-time as described in claim 5, wherein the integrator comprises: an integrating capacitor coupled to the phase node for The node voltage and the upper bridge driving signal and/or the lower bridge driving signal generate the integral signal; and an integrating switch connected in parallel with the integrating capacitor for using the upper bridge driving signal and/or the lower bridge driving signal Switching so that the integration signal is related to the product of the input voltage and the on-time of the upper bridge switch. A control circuit for a switching power supply having a chopping modulation on-time as described in claim 5, wherein the sample-and-hold circuit comprises: a sample-and-hold capacitor coupled to the integrator for generating the sample-and-hold signal according to the integrated signal and the upper-bridge driving signal and/or the lower-bridge driving signal; and a sample-and-hold switch, and the sample-and-hold capacitor The coupling is configured to switch according to the upper bridge driving signal and/or the lower bridge driving signal, and control the sampling and holding operation, so that the sampling holding capacitor samples and maintains the integral signal generated by the integrator. The control circuit of the switching power supply with the chopping modulation on-time as described in claim 5, wherein the conversion circuit comprises: a controlled current source circuit coupled to the sample-and-hold circuit, And generating a charging current according to the sampling and holding signal; and a charging circuit coupled to the controlled current source circuit for charging according to the charging current and the upper bridge driving signal and/or the lower bridge driving signal, To generate the chopping slope compensation signal. A control method for a switching power supply device with chopping modulation and constant conduction time, comprising: switching one of the upper bridge switches according to an upper bridge driving signal, and switching one of the lower bridge switches according to the lower bridge driving signal, so as to An input voltage is converted to an output voltage, wherein the upper bridge switch and the lower bridge switch are connected in series to a phase node; and a feedback signal associated with the output voltage, a phase node voltage of the phase node, and the And generating, by the upper bridge driving signal and/or the lower bridge driving signal, the upper bridge driving signal and the lower bridge driving signal; wherein, according to the output voltage, one feedback signal, one phase node voltage of the phase node And the step of generating the upper bridge driving signal and the lower bridge driving signal with the upper bridge driving signal and/or the lower bridge driving signal, comprising: generating the signal according to the feedback signal and a chopping slope compensation signal Bridge drive signal and the lower bridge drive signal; Generating the chopping slope compensation signal according to the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal; wherein the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal are generated according to the phase node voltage The step of generating the chopping slope compensation signal includes: generating an integration signal according to the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal; and according to the integration signal and the upper bridge driving signal and/or The lower bridge driving signal generates a sample and hold signal; and generates the chopping slope compensation signal according to the sample and hold signal and the upper bridge driving signal and/or the lower bridge driving signal. The method for controlling a switching power supply having a chopping modulation on-time according to the ninth application of the patent application, wherein the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal are generated according to the phase node voltage The step of integrating the signal includes: generating the integrated signal according to the phase node voltage and the upper bridge driving signal and/or the lower bridge driving signal; and switching according to the upper bridge driving signal and/or the lower bridge driving signal The integration signal is related to the product of the input voltage and the on-time of the upper bridge switch. The method for controlling a switching power supply having a chopping modulation on-time according to the ninth aspect of the patent application, wherein the step of generating a sample-and-hold signal according to the phase node voltage and the integration signal comprises: The integration signal and the upper bridge driving signal and/or the lower bridge driving signal generate the sampling and holding signal; and switch according to the upper bridge driving signal and/or the lower bridge driving signal, and control sampling and holding operation, so that the The sample and hold capacitor samples and maintains the integral signal generated by the integrator. The method for controlling a switching power supply having a chopping modulation on-time according to the ninth application of the patent application, wherein the sampling and holding signal and the upper bridge driving signal and/or the lower bridge driving signal are generated according to the method The step of the chopping slope compensation signal includes: generating a charging current according to the sampling and holding signal; and charging according to the charging current and the upper bridge driving signal and/or the lower bridge driving signal to generate the chopping slope compensation Signal.