[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TWI591737B - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

Info

Publication number
TWI591737B
TWI591737B TW105126197A TW105126197A TWI591737B TW I591737 B TWI591737 B TW I591737B TW 105126197 A TW105126197 A TW 105126197A TW 105126197 A TW105126197 A TW 105126197A TW I591737 B TWI591737 B TW I591737B
Authority
TW
Taiwan
Prior art keywords
semiconductor package
semiconductor
package
conductive
disposed
Prior art date
Application number
TW105126197A
Other languages
English (en)
Other versions
TW201712765A (zh
Inventor
林子閎
連錡晉
劉乃瑋
彭逸軒
蕭景文
黃偉哲
Original Assignee
聯發科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW201712765A publication Critical patent/TW201712765A/zh
Application granted granted Critical
Publication of TWI591737B publication Critical patent/TWI591737B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

半導體封裝結構
本發明涉及封裝技術領域，特別係涉及一種高成本效應的扇出的覆晶封裝結構，並且該封裝結構具有嵌入的封裝基底。
於半導體封裝產業中，業界期望降低半導體晶粒的封裝成本。為了達到該期望，已開發了各種封裝結構設計。覆晶封裝結構為當前使用的一種封裝結構設計。
在覆晶封裝結構中，由複數個焊料凸塊(solder bump)形成的一半導體晶粒(也被稱作“積體電路晶片”或“晶片”)一般直接接合至一封裝基底的複數個金屬接墊。該等焊料凸塊固定至半導體晶粒的I/O(input/output；輸入/輸出)接合墊。在封裝期間，“翻轉”半導體晶粒以便焊料凸塊形成半導體晶粒與封裝基底之間的電性互連。由於覆晶封裝技術顯著地縮短了半導體晶粒與封裝基底之間的互連路徑，因此覆晶封裝技術能夠提供比早期的線接合技術更快速度的電性能。
為了確保電子產品之小型化及多功能性，期望一種小尺寸、高運行速度以及具有高功能的半導體封裝。相應地，半導體晶粒需要將更多的I/O接墊放進更小的區域，並且需要使用封裝基底來作為扇出層(fan out layer)。
但是，為了響應I/O接墊的增長，於封裝基底中形成復雜的多層互連結構。如此，顯著地增加了封裝基底的尺寸與製造成本，同時降低了封裝基底的良品率。這些導致了半導體封裝結構的穩定性、良品率及生產量的減少，同時增加了半導體封裝結構的製造成本。
因此，期望一種新式的半導體封裝結構。
因此，本發明之主要目的即在於提供一種半導體封裝結構，可以降低成本。
根據本發明至少一個實施例的一種半導體封裝結構，包括：一第一半導體封裝，包括：一第一半導體晶粒，具有一第一表面及一相對於該第一表面的第二表面；一第一封裝基底，設置在該第一半導體晶粒的該第一表面上；一第一模塑料，圍繞該第一半導體晶粒與該第一封裝基底；以及一第一重分佈層結構，設置在該第一模塑料上，其中該第一封裝基底係插入在並電性耦接在該第一半導體晶粒與該第一重分佈層結構之間。
以上的半導體封裝結構，將第一封裝基底設置在第一半導體晶粒與第一重分佈層結構之間，並與第一重分佈層結構一起來作為半導體封裝結構的扇出層，因此可以降低封裝基底中的互連層的數量，從而簡化半導體封裝的結構。
10a~10d、20a~20f、30a~10c、40a~40e、50a~50e‧‧‧半導體封裝結構
175‧‧‧第三導電結構
100‧‧‧第一半導體晶粒
100a‧‧‧第一表面
100b‧‧‧第二表面
102‧‧‧互連結構
104、115、215‧‧‧導電接墊
110‧‧‧第一封裝基底
112‧‧‧絕緣基座
111、121‧‧‧第一導電線路
113、123‧‧‧第二導電線路
108a、108b‧‧‧第一導電結構
109‧‧‧底部填充材料層
130‧‧‧第一模塑料
120‧‧‧第一RDL結構
140a、140b‧‧‧第二導電結構
122‧‧‧IMD層
124、125‧‧‧接墊部分
150‧‧‧黏合層
160‧‧‧第一保護層
170‧‧‧通孔
155‧‧‧第二保護層
165‧‧‧導熱界面材料層
180‧‧‧散熱器
400、500‧‧‧第二半導體晶粒
210‧‧‧第二封裝基底
220‧‧‧接合線
270、370、470‧‧‧第四導電結構
204‧‧‧第五導電結構
230‧‧‧第二模塑料
370b‧‧‧焊料
370a‧‧‧銅球
通過閱讀接下來的詳細描述與參考所附圖示所做之實施例，可以更容易地理解本發明，其中：第1A圖為根據本發明一些實施例的半導體封裝結構之橫截面示意圖；第1B圖為根據本發明一些實施例的半導體封裝結構之橫截面示意圖；第1C圖為根據本發明一些實施例的半導體封裝結構之橫截面示意圖；第1D圖為根據本發明一些實施例的半導體封裝結構之橫截面示意圖；第2A圖為根據本發明一些實施例的具有通孔的半導體封裝結構之橫截面示意圖；第2B圖為根據本發明一些實施例的具有通孔的半導體封裝結構之橫截面示意圖；第2C圖為根據本發明一些實施例的具有通孔的半導體封裝結構之橫截面示意圖；第2D圖為根據本發明一些實施例的具有通孔的半導體封裝結構之橫截面示意圖；第2E圖為根據本發明一些實施例的具有通孔的半導體封裝結構之橫截面示意圖；第2F圖為根據本發明一些實施例的具有通孔的半導體封裝結構之橫截面示意圖；第3A圖為根據本發明的具有散熱器的半導體封裝結構之橫截面示意圖； 第3B圖為根據本發明的具有散熱器的半導體封裝結構之橫截面示意圖；第3C圖為根據本發明的具有散熱器的半導體封裝結構之橫截面示意圖；第4A圖為根據本發明的具有PoP(Package-on-Package；封裝上封裝)結構的半導體封裝結構之橫截面示意圖；第4B圖為根據本發明的具有PoP結構的半導體封裝結構之橫截面示意圖；第4C圖為根據本發明的具有PoP結構的半導體封裝結構之橫截面示意圖；第4D圖為根據本發明的具有PoP結構的半導體封裝結構之橫截面示意圖；第4E圖為根據本發明的具有PoP結構的半導體封裝結構之橫截面示意圖；第5A圖為根據本發明的具有PoP結構的半導體封裝結構之橫截面示意圖；第5B圖為根據本發明的具有PoP結構的半導體封裝結構之橫截面示意圖；第5C圖為根據本發明的具有PoP結構的半導體封裝結構之橫截面示意圖；第5D圖為根據本發明的具有PoP結構的半導體封裝結構之橫截面示意圖；第5E圖為根據本發明的具有PoP結構的半導體封裝結構之橫截面示意圖。
以下描述為預期的實現本發明的模式。該描述僅係說明本發明的一般原理的目的，而不應視為限制。本發明的範圍僅通過參考所附的申請專利範圍來確定。
通過參考特定實施例及參考確定的圖式來描述本發明，但是本發明不限制於此，並且本發明僅受申請專利範圍的限制。描述的圖式僅為原理圖而非限制。在圖式中，出於說明目的而跨大了某些元件的尺寸並且元件並非按比例繪制。尺寸及相對尺寸不對應本發明實踐中的實際尺寸。
第1A圖為根據本發明一些實施例的半導體封裝結構10a的橫截面示意圖。在一些實施例中，該半導體封裝結構10a為一晶圓級半導體封裝結構，例如扇出(fan-out)晶圓級半導體封裝結構。在一實施例中，該扇出晶圓級半導體封裝結構可以包括：一SOC(System-On-Chip，系統單晶片)封裝結構。
參考第1A圖，該半導體封裝結構10a包括：一第一半導體封裝(如扇出晶圓級半導體封裝)，可以安裝於一基座(未示出)上，諸如PCB(Printed Circuit Board；印刷電路板)，可以由PP(polypropylene；聚丙烯)、PBO(polybenzoxazole；聚苯並惡唑)或聚酰亞胺組成。在一些實施例中，該基座可以為一單層或一多層結構。電性耦接至該基座的導電接墊與導電線路一般設置在該基座的頂面上和/或該基座中。在此情形中，導電線路可以用於該半導體封裝結構10a的I/O連接。在一些實施例中，該半導體封裝結構10a的第一 半導體封裝通過接合製程安裝於該基座上。例如，該第一半導體封裝包括：第三導電結構(如凸塊)175，通過接合製程安裝於該基座上並且電性耦接至該基座。
在本實施例中，該半導體封裝結構10a的該第一半導體封裝包括：一第一半導體晶粒100。該第一半導體晶粒100具有一第一表面100a及相對於該第一表面的一第二表面100b。另外，該第一半導體晶粒100可以包括：一互連結構102，電性連接至該第一半導體晶粒100的電路(未示出)，並且包括：位於其上的導電接墊104。其中，該互連結構之下表面即為該第一半導體晶粒100的該第一表面100a。該互連結構102，諸如一RDL結構，包括：一條或複數條導電線路，設置在一絕緣層中，並且導電接墊104設置在該絕緣層中。在一些實施例中，該第一半導體晶粒100(諸如SOC晶粒)可以包括：一邏輯晶粒，該邏輯晶粒可以包括：CPU(Central Processing Unit；中央處理單元)、GPU(Graphics Processing Unit；圖像處理單元)、DRAM(Dynamic Random Access Memory；動態隨機存取記憶體)控制器或者他們的任意組合。可選地，該第一半導體晶粒100可以包括：一數據機晶粒(modem die)。
在本實施例中，該半導體封裝結構10a的該第一半導體封裝進一步包括：一第一封裝基底110，設置在該第一半導體晶粒100的該第一表面100a上，以作为扇出层。在本实施例中，该第一封裝基底110包括：一條或複數條导电线路以及一個或複數個導電接墊，設置在一絕緣基座112內或者之上。例如，第一導電線路111設置在該絕緣基座112的第一層 級(first layer-level)處。一條或複數條第一導電線路111電性耦接至對應的導電接墊115。另外，第二導電線路113設置在該絕緣基座112的一第二層級處，該第二層級不同於該絕緣基座112的第一層級。在一些實施例中，該絕緣基座112可以由有機材料組成，該有機材料包括：聚合物基材料(例如PP、PBP、或者聚酰亞胺)，或者類似物。需要注意，第1A圖所示的第一封裝基底110中的導電線路的數量以及導電接墊的數量僅是示例而不是對本發明的限制。
在本實施例中，該第一封裝基底110經由第一導電結構108a(諸如焊料球)電性耦接至該第一半導體晶粒100，並且該第一導電結構108a嵌入於一底部填充材料層109中。例如，該第一封裝基底110的導電接墊115連接至對應的第一導電結構108a，並且該第一導電結構108a連接至第一半導體晶粒100的互連結構102的對應的導電接墊104。
在本實施例中，該半導體封裝結構10a的第一半導體封裝進一步包括：一第一模塑料(molding compound)130，圍繞該第一半導體晶粒100、該第一封裝基底110以及該第一半導體晶粒100與該第一封裝基底110之間的該底部填充材料層109。該第一半導體晶粒100的第二表面100b從該第一模塑料130中露出。在一些實施例中，該第一模塑料130可以由環氧樹脂、樹脂、可塑聚合物或者類似物組成。在該第一模塑料130實質為液體時應用，接著通過化學反應固化該第一模塑料130，諸如在環氧樹脂或者樹脂中。在其他一些實施例中，該第一模塑料130可以為UV(ultraviolet；紫外)或者熱固化 的聚合物，並且作為能夠設置在第一半導體晶粒100的周圍的凝膠或者可塑固定而應用，並且接著可以通過UV或者熱固化製程來固化。該第一模塑料可以按照模型(未示出)來固化。
在本實施例中，該半導體封裝結構10a的第一半導體封裝進一步包括：一第一RDL結構120，設置在該第一模塑料130上，使得該第一封裝基底110插入在該第一半導體晶粒100與該第一RDL結構120之間。另外，該第一RDL結構120經由第二導電結構140a電性耦接至該第一封裝基底110，諸如焊料球。在一些實施例中，該第一RDL結構120，也被稱為扇出結構，具有與該第一模塑料130的側壁實質上垂直對齊的一側壁。
在本實施例中，該第一RDL結構120具有類似於該第一封裝基底110的結構，以便於作為第二扇出層。該第一RDL結構120包括：一條或複數條導電線路，設置在一IMD(Inter-Metal Dielectric；金屬間介電)層122中。例如，第一導電線路121設置在IMD層122的第一層級處。至少一條第一導電線路121具有電性耦接至對應的第二導電結構140a的接墊部分124。另外，第二導電線路123設置在該IMD層122的第二層級處，該第二層級不同於第一層級。在一些實施例中，該IMD層122可以為由有機材料或無機材料形成的單層或者多層結構，該有機材料包括：聚合物基材料，該無機材料包括：SiNx(氮化矽)，SiOx(氧化矽)，石墨烯或者類似物。在一些實施例中，該IMD層122為高k值介電層(k為介電層的介電常數)。在其他一些實施例中，該IMD層122可以由光 敏材料組成，該光敏材料包括：乾膜光阻，或者貼膜(taping film)。
第二導電線路123的接墊部分125在IMD層122上並且連接至第三導電結構175(諸如凸塊)，因此第三導電結構175設置在該第一RDL結構120上並且電性耦接至該第一RDL結構120，並且該第一RDL結構120係位於該第一封裝基底110與該第三導電結構175之間。另外，需要注意，第1A圖所示的第一RDL結構120的導電線路的數量以及接墊部分的數量僅是示例而不是對本發明的限制。
在本實施例中，該半導體封裝10a的第一半導體封裝進一步包括：一黏合層150及一第一保護層160。在本實施例中，該黏合層150(有時也稱為DAF(Die-Attach Film；晶粒黏結薄膜))用於在半導體封裝結構10a的製造期間，將第一半導體晶粒100黏結在載體(未示出)上。該第一保護層160(也時也稱為BSF(Back Side Film，背面薄膜))係設置在第一半導體晶粒100的第二表面100b及該第一模塑料130的上方，使得黏合層150設置在該第一保護層160與該第一半導體晶粒100之間。在本實施例中，該第一保護層160直接接觸該黏合層150，以便於保護該第一半導體晶粒100與該第一模塑料130免受損傷。
第1B圖為根據本發明一些實施例的半導體封裝結構10b的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第1A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構10b類似於第1A圖所 示的半導體封裝結構10a。如第1B圖所示，不同於該半導體封裝結構10a，該半導體封裝結構10b的第一半導體封裝包括：第二導電結構140b，諸如銅柱或者凸塊，該第二導電結構140b電性耦接在該第一RDL結構120與該第一封裝基底110之間。
第1C圖為根據本發明一些實施例的半導體封裝結構10c的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第1A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構10c類似於第1A圖所示的半導體封裝結構10a。如第1C圖所示，不同於該半導體封裝結構10a，在該半導體封裝結構10c的第一半導體封裝中，該第一封裝基底110直接接觸該第一RDL結構120。在本實施例中，例如，第一封裝基底110中的第二導電線路113的接墊部分(未示出)接合至該第一RDL結構120中的第一導電線路121的對應的接墊部分124。
第1D圖為根據本發明一些實施例的半導體封裝結構10d的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第1C圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構10d類似於第1C圖所示的半導體封裝結構10c。如第1D圖所示，不同於該半導體封裝結構10c，在該半導體封裝結構10d的第一半導體封裝包括：第一導電結構108b(諸如銅凸塊或者銅柱)，電性耦接在該第一封裝基底110與該第一半導體晶粒100之間。在本實施例中，例如，該第一封裝基底110的導電接墊115連接至對應 的銅凸塊或者銅柱(即第一導電結構108b)，並且該銅凸塊或者銅柱連接至該第一半導體晶粒100的互連結構102的對應的導電接墊104。在本實施例中，儘管該第一封裝基底110直接接觸該第一RDL結構120，但是該半導體封裝結構10d可以包括：第二導電結構140a(如第1A圖所示)或者第二導電結構140b(如第1B圖所示)，以便於實現該第一RDL結構120與該第一封裝基底110之間的電性耦接。
第2A圖為根據本發明一些實施例的具有通孔(through vias)的半導體封裝結構20a的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第1A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構20a類似於第1A圖所示的半導體封裝結構10a。如第2A圖所示，不同於該半導體封裝結構10a，該半導體封裝結構20a的第一半導體封裝進一步包括：通孔170(有時也稱為“TPV(Trough Package Vias；穿過封裝通孔)”或者“TIV(Through Interposer Vias；穿過插入層通孔)”)，穿過第一模塑料130並經由第一導電線路121的接墊部分124電性耦接至該第一RDL結構120。在一些實施例中，該通孔170可以圍繞該第一半導體晶粒100。另外，該通孔170可以由銅組成。
在本實施例中，該半導體封裝結構20a的第一半導體封裝進一步包括：一第二保護層155，設置在第一保護層160與黏合層150之間。在此情形中，該第一模塑料130可以圍繞該黏合層150。該第二保護層155保護其下面的黏合層150在形成該通孔170的期間免受損傷。在一些實施例中，該第一 與第二保護層160與155具有複數開口，以露出第一模塑料130中的通孔170。另外，可選的焊料(未示出)可以填充這些開口，以接觸該露出的通孔170，從而利於用於PoP製造的接合製程。
第2B圖為根據本發明一些實施例的具有通孔的半導體封裝結構20b的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第2A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構20b類似於第2A圖所示的半導體封裝結構20a。如第2B圖所示，不同於半導體封裝結構20a，該半導體封裝結構20b的第一半導體封裝包括：第二導電結構140b，諸如銅柱或者銅凸塊，電性耦接在該第一RDL結構120與該第一封裝基底110之間。
第2C圖為根據本發明一些實施例的具有通孔的半導體封裝結構20c的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第2A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構20c類似於第2A圖所示的半導體封裝結構20a。如第2C圖所示，不同於該半導體封裝結構20a，在該半導體封裝結構20c的第一半導體封裝中，該第一封裝基底110直接接觸該第一RDL結構120。在本實施例中，例如，第一封裝基底110中的第二導電線路113的接墊部分(未示出)接合至該第一RDL結構120中的第一導電線路121的對應的接墊部分124。
第2D圖為根據本發明一些實施例的具有通孔的半導體封裝結構20d的橫截面示意圖。以下描述的該實施例的元 件，有相同或者類似於參考第2C圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構20d類似於第2C圖所示的半導體封裝結構20c。如第2D圖所示，不同於該半導體封裝結構20c，該半導體封裝結構20d的第一半導體封裝包括：第一導電結構108b(諸如銅凸塊或者銅柱)，電性耦接在該第一封裝基底110與該第一半導體晶粒100之間。在本實施例中，例如，該第一封裝基底110的導電接墊115連接至對應的銅凸塊或者銅柱(即第一導電結構108b)，並且該銅凸塊或者銅柱連接至該第一半導體晶粒100的互連結構102的對應的導電接墊104。
第2E圖為根據本發明一些實施例的具有通孔的半導體封裝結構20e的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第2D圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構20e類似於第2D圖所示的半導體封裝結構20d。如第2E圖所示，不同於該半導體封裝結構20d，該半導體封裝結構20e的第一半導體封裝包括：第二導電結構140b，諸如銅柱或者銅凸塊，電性耦接在該第一RDL結構120與該第一封裝基底110之間。
第2F圖為根據本發明一些實施例的具有通孔的半導體封裝結構20f的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第2D圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構20f類似於第2D圖所示的半導體封裝結構20d。如第2F圖所示，不同於該半導體封裝結構20d，該半導體封裝結構20f的第一半導體封 裝包括：第二導電結構140a，諸如焊料球，電性耦接在該第一RDL結構120與該第一封裝基底110之間。
第3A圖為根據本發明一些實施例的具有散熱器(heat sink)的半導體封裝結構30a的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第1A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構30a類似於第1A圖所示的半導體封裝結構10a。如第3A圖所示，不同於該半導體封裝結構10a，該半導體封裝結構30a的第一半導體封裝進一步包括：一導熱界面材料(Thermal Interface Material；TIM)層165與一散熱器180。在本實施例中，該散熱器180設置在第一保護層160的上方，且該TIM層165設置在該第一保護層160與該散熱器180之間。
在本實施例中，不同於半導體封裝結構10a，該半導體封裝結構30a的第一半導體封裝包括：第一導電結構108b(諸如銅凸塊或者銅柱)，電性耦接在第一封裝基底110與該第一半導體晶粒100之間。在本實施例中，例如，該第一封裝基底110的導電接墊115連接至對應的銅凸塊或者銅柱(即第一導電結構108b)，並且銅凸塊或者銅柱連接至該第一半導體晶粒100的互連結構102的對應的導電接墊104。在一些實施例中，如第1A圖所示的嵌入在底部填充材料層109中的第一導電結構108a(如為焊料球)，可以用來替代該導電結構108b。
第3B圖為根據本發明一些實施例的具有散熱器的半導體封裝結構30b的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第3A圖已描述了的元件的，出 於簡潔而省略。在本實施例中，該半導體封裝結構30b類似於第3A圖所示的半導體封裝結構30a。如第3B圖所示，不同於半導體封裝結構30a，該半導體封裝結構30b的第一半導體封裝包括：第二導電結構140b，諸如銅柱或者銅凸塊，電性耦接在該第一RDL結構120與該第一封裝基底110之間。
類似地，在一些實施例中，如第1A圖所示的嵌入在底部填充材料層109中的第一導電結構108a(如為焊料球)可以用來替代該第一導電結構108b。
第3C圖為根據本發明一些實施例的具有散熱器的半導體封裝結構30c的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第3A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構30c類似於第3A圖所示的半導體封裝結構30a。如第3C圖所示，不同於該半導體封裝結構30a，在該半導體封裝結構30c的第一半導體封裝中，該第一封裝基底110直接接觸該第一RDL結構120。例如，第一封裝基底110中的第二導電線路113的接墊部分(未示出)接合至該第一RDL結構120中的第一導電線路121的對應的接墊部分124。
類似地，在一些實施例中，如第1A圖所示的嵌入在底部填充材料層109中的第一導電結構108a(如焊料球)可以用來替代該第一導電結構108b。
第4A圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構40a的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第2A圖已描述了的元件的， 出於簡潔而省略。在本實施例中，該半導體封裝結構40a類似於第2A圖所示的半導體封裝結構20a。如第4A圖所示，不同於半導體封裝結構20a，沒有通孔170設置在第一模塑料130中。在本實施例中，該半導體封裝結構40a的第一半導體封裝包括：一第二半導體封裝，設置在第一半導體封裝上。在一些實施例中，該第一半導體封裝為一SOC封裝，且該第二半導體封裝為一DRAM封裝。在本實施例中，該第一半導體晶粒100在該第一RDL結構120上的投影與第二半導體封裝在該第一RDL結構120上的投影係分隔開的。在一些實施例，該第一半導體晶粒100在該第一RDL結構120上的投影可與該第二半導體封裝在該第一RDL結構120上的投影重疊。
在本實施例中，該第二半導體封裝包括：一個或複數個第二半導體晶粒，設置在該第一半導體封裝的第一模塑料130的上方。例如，兩個堆疊的第二半導體晶粒400與500(諸如DRAM晶粒)設置在第一模塑料130的上方。
另外，該第二半導體封裝進一步包括：一第二封裝基底210，位於該第二半導體晶粒400、500與該第一模塑料130之間。在本實施例中，該封裝基底210包括：位於其上的導電接墊215並且具有類似於第一封裝基底110的結構。另外，第二封裝基底210電性耦接在第二半導體晶粒400、500與該第一封裝基底110之間。例如，第二半導體晶粒400與500經由導電接墊215與接合線220而電性耦接至該第二封裝基底210。
另外，在本實施例中，該第一半導體封裝進一步 包括：第四導電結構270(諸如焊料球)，嵌入於該第一模塑料130中，以便於電性耦接至該第一封裝基底110的導電接墊115。在此情形中，第一與第二保護層160、155具有複數開口，以露出第一模塑料130中的第四導電結構270。可選的焊料(未示出)可以填充這些開口，以接觸該露出的第四導電結構270。
另外，在本實施例中，該第二半導體封裝進一步包括：一第五導電結構(如為凸塊)204，係設置在第二封裝基底210上並且可以嵌入至底部填充材料層209中。第五導電結構204電性耦接至第二封裝基底210與該露出的第四導電結構270。
在本實施例中，第二半導體封裝進一步包括：第二模塑料230，覆蓋該第二半導體晶粒400與500、接合線220、以及第二封裝基底210。在本實施例中，第二模塑料230由相同或者類似於第一模塑料130的材料製成。
第4B圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構40b的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第4A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構40b類似於第4A圖所示的半導體封裝結構40a。如第4B圖所示，不同於半導體封裝結構40a，該半導體封裝結構40b的第一半導體封裝包括：第二導電結構140b，諸如銅柱或者銅凸塊，電性耦接在該第一RDL結構120與該第一封裝基底110之間。
第4C圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構40c的橫截面示意圖。以下描述的該實施例 的元件，有相同或者類似於參考第4A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構40c類似於第4A圖所示的半導體封裝結構40a。如第4C圖所示，不同於該半導體封裝結構40a，在該半導體封裝結構40c的第一半導體封裝中，該第一封裝基底110直接接觸該第一RDL結構120。在本實施例中，例如，第一封裝基底110中的第二導電線路113的接墊部分(未示出)接合至該第一RDL結構120中的第一導電線路121的對應的接墊部分124。
第4D圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構40d的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第4C圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構40d類似於第4C圖所示的半導體封裝結構40c。如第4D圖所示，不同於半導體封裝結構40c，該半導體封裝結構40d的第一半導體封裝進一步包括：一第四導電結構370，嵌入於該第一模塑料130中，以便於電性耦接至該第一封裝基底110的導電接墊115。在此情形中，第四導電結構370可以為由焊料370b覆蓋的銅球370a。另外，第一與第二保護層160與155具有複數開口，以露出第一模塑料130中的第四導電結構370。可選的焊料(未示出)可以填充該些開口，以接觸該露出的第四導電結構370。
第4E圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構40d的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第4C圖已描述了的元件的， 出於簡潔而省略。在本實施例中，該半導體封裝結構40e類似於第4C圖所示的半導體封裝結構40c。如第4E圖所示，不同於半導體封裝結構40c，該半導體封裝結構40e的第一半導體封裝進一步包括：第四導電結構470，嵌入於該第一模塑料130中，以便於電性耦接至該第一封裝基底110的導電接墊115。在此情形中，該第四導電結構470可以為銅柱。另外，第一與第二保護層160與155具有複數開口，以露出第一模塑料130中的第四導電結構470。可選的焊料(未示出)可以填充該些開口，以接觸露出的第四導電結構470。
在第4D與4E圖所示的實施例中，儘管第一封裝基底110係直接接觸該第一RDL結構120，但是該半導體封裝40d與40e的第一半導體封裝可以包括：第二導電結構140a(如第4A圖所示)或者第二導電結構140b(如第4B圖所示)，以便於電性耦接在第一RDL結構120與該第一封裝基底110之間。
第5A圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構50a的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第4A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構50a類似於第4A圖所示的半導體封裝結構40a。如第5A圖所示，不同於半導體封裝結構40a，該半導體封裝結構50a的第一半導體封裝進一步包括：第四導電結構470，嵌入於該第一模塑料130中，以便於電性耦接該第一封裝基底110的導電接墊115。在此情形中，該第四導電結構470可以為銅柱。另外，該第一與 第二保護層160與155具有開口，以露出該第一模塑料130中的第四導電結構470。可選的焊料(未示出)可以填充這些開口，以接觸該露出的第四導電結構470。
另外，在本實施例中，該半導體封裝結構50a的第一半導體封裝包括：導電結構108b(諸如銅凸塊或者銅柱)，電性耦接在第一封裝基底110與第一半導體晶粒100之間。在本實施例中，例如，第一封裝基底110的導電接墊115連接至對應的銅凸塊或者銅柱(即第一導電結構108b)，且該銅凸塊或者銅柱連接至該第一半導體晶粒100的互連結構102的對應的導電接墊104。
第5B圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構50b的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第5A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構50b類似於第5A圖所示的半導體封裝結構50a。如第5B圖所示，不同於半導體封裝結構50a，該半導體封裝結構50b的第一半導體封裝包括：第二導電結構140b，諸如銅柱或者銅凸塊，電性耦接在該第一RDL結構120與該第一封裝基底110之間。
第5C圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構50c的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第5A圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構50c類似於第5A圖所示的半導體封裝結構50a。如第5C圖所示，不同於該半導體封裝結構50a，在該半導體封裝結構50c的第一半 導體封裝中，該第一封裝基底110直接接觸該第一RDL結構120。在本實施例中，例如，該第一封裝基底110中的第二導電線路113的接墊部分(未示出)接合至該第一RDL結構120中的第一導電線路121的對應的接墊部分124。
第5D圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構50d的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第5C圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構50d類似於第5C圖所示的半導體封裝結構50c。如第5D圖所示，不同於半導體封裝結構50c，該半導體封裝結構50d的第一半導體封裝進一步包括：第四導電結構270(諸如焊料球)，嵌入於該第一模塑料130中，以便於電性耦接至該第一封裝基底110的導電接墊115。在此情形中，第一與第二保護層160與155具有開口，以露出第一模塑料130中的第四導電結構270。可選的焊料(未示出)可以填充該些開口，以接觸該露出的第四導電結構270。
第5E圖為根據本發明一些實施例的具有PoP結構的半導體封裝結構50e的橫截面示意圖。以下描述的該實施例的元件，有相同或者類似於參考第5C圖已描述了的元件的，出於簡潔而省略。在本實施例中，該半導體封裝結構50d類似於第5C圖所示的半導體封裝結構50c。如第5E圖所示，不同於半導體封裝結構50c，該半導體封裝結構50e的第一半導體封裝進一步包括：第四導電結構370，嵌入於該第一模塑料130中，以便於電性耦接至該第一封裝基底110的導電接墊115。 在此情形中，該第四導電結構370可以為被焊料370b覆蓋的銅球370a。另外，第一與第二保護層160與155具有開口，以露出第一模塑料130中的第四導電結構370。可選的焊料(未示出)可以填充該些開口，以接觸該露出的第四導電結構370。
在第5D與5E圖所示的實施例中，儘管第一封裝基底110直接接觸該第一RDL結構120，但是該半導體封裝結構50d與50e的第一半導體封裝可以包括：第二導電結構140a(如第5A圖所示)或者第二導電結構140b(如第5B圖所示)，以便於電性耦接在第一RDL結構120與該第一封裝基底110之間。
根據前述實施例，由於半導體封裝使用嵌入式(embedded-type)封裝基底與RDL結構的組合來作為半導體封裝結構的扇出層，因此相比於習知的半導體封裝結構(該習知的半體封裝結構僅於其中使用具有複雜多層結構的封裝基底來作為扇出層)，可以降低嵌入式封裝基底中的互連層的數量，從而簡化半導體封裝的結構。另外，由於由於通過額外的RDL的使用來降低嵌入式封裝基底中的必需的互連層，因此半導體封裝結構中的翹曲問題可以減輕或改善。如此，可以降低封裝基底的尺寸，從而降低半導體封裝結構的製造成本，降低半體封裝結構的尺寸，以及增加封裝基底的良率。另外，增加半導體封裝結構的穩定性、良率與生產量。
另外，相比於習知的半導體封裝，可以維持使用嵌入式封裝基底與RDL來作為扇出層的半導體封裝結構的I/O接墊的間距(pitch)。因此，沒有必要修改安裝於半導體封裝 結構上的PCB。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
10a‧‧‧半導體封裝結構
175‧‧‧第三導電結構
100‧‧‧第一半導體晶粒
100a‧‧‧第一表面
100b‧‧‧第二表面
102‧‧‧互連結構
104、115‧‧‧導電接墊
110‧‧‧第一封裝基底
112‧‧‧絕緣基座
111、121‧‧‧第一導電線路
113、123‧‧‧第二導電線路
108a‧‧‧第一導電結構
109‧‧‧底部填充材料層
130‧‧‧第一模塑料
120‧‧‧第一RDL結構
140a‧‧‧第二導電結構
122‧‧‧IMD層
124、125‧‧‧接墊部分
150‧‧‧黏合層
160‧‧‧第一保護層

Claims (17)

  1. 一種半導體封裝結構，包括：一第一半導體封裝，包括：一第一半導體晶粒，具有一第一表面及一相對於該第一表面的第二表面；一第一封裝基底，設置在該第一半導體晶粒的該第一表面之上；一第一模塑料，圍繞該第一半導體晶粒與該第一封裝基底；以及一第一重分佈層結構，設置在該第一模塑料上，其中該第一封裝基底係設置在並電性耦接在該第一半導體晶粒與該第一重分佈層結構之間。
  2. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該第一半導體晶粒包括：一互連結構，該互連結構之一表面即為該第一半導體晶粒的該第一表面。
  3. 根據申請專利範圍第2項所述的半導體封裝結構，其中，該互連結構為一重分布層結構。
  4. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該第一封裝基底係通過至少一個嵌入於一底部填充材料層中的第一導電結構電性耦接至該第一半導體晶粒。
  5. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該第一封裝基底係通過至少一個第二導電結構電性耦接至該第一重分佈層結構。
  6. 根據申請專利範圍第1項所述的半導體封裝結構，其中， 該第一封裝基底係直接接觸該第一重分佈層結構。
  7. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：至少一個第三導電結構，設置在該第一重分佈層結構上並且電性耦接至該第一重分佈層結構，其中該第一重分佈層結構位於該第一封裝基底與複數個第三導電結構之間。
  8. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：至少一個通孔，穿過該第一模塑料並電性耦接至該第一重分佈層結構。
  9. 根據申請專利範圍第1項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：一第一保護層，設置在該第一半導體晶粒的該第二表面及該第一模塑料的上方；以及一黏合層，設置在該第一保護層與該第一半導體晶粒之間。
  10. 根據申請專利範圍第9項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：一散熱器，設置在該第一保護層的上方；以及一導熱界面材料層，設置在該第一保護層與該散熱器之間。
  11. 根據申請專利範圍第9項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：一第一保護層，設置在該第一半導體晶粒的該第二表面及該第一模塑料的上方；一黏合層，設置在該第一保護層與該第一半導體晶粒之 間，並且被該第一模塑料圍繞；一第二保護層，設置在該第一保護層與該黏合層之間，用於保護該黏合層。
  12. 根據申請專利範圍第1項所述的半導體封裝結構，其中，還包括：一第二半導體封裝，設置在該第一半導體封裝上，並且包括：至少一個第二半導體晶粒，設置在該第一模塑料的上方；一第二封裝基底，設置在該至少一個第二半導體晶粒與該第一模塑料之間，並且電性耦接在該至少一個第二半導體晶粒與該第一封裝基底之間；以及一第二模塑料，覆蓋該至少一個第二半導體晶粒與該第二封裝基底。
  13. 根據申請專利範圍第12項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：複數個第四導電結構，嵌入於該第一模塑料中，並且電性耦接在該第二封裝基底與該第一封裝基底之間。
  14. 根據申請專利範圍第13項所述的半導體封裝結構，其中，至少一個第四導電結構包括：銅柱，焊球，或者由焊料覆蓋的銅球。
  15. 根據申請專利範圍第13項所述的半導體封裝結構，其中，該第二半導體封裝進一步包括：複數個第五導電結構，設置在該第二封裝基底上並且電性耦接在該第二封裝基底與該複數個第四導電結構之間。
  16. 根據申請專利範圍第12項所述的半導體封裝結構，其中，該第一半導體晶粒在該第一重分佈層結構上的投影與該第二半導體封裝在該第一重分佈層結構上的投影係分隔開的或者重疊的。
  17. 根據申請專利範圍第12項所述的半導體封裝結構，其中，該第一半導體封裝為一系統單晶片封裝，且該第二半導體封裝為一動態隨機存取記憶體封裝。
TW105126197A 2015-09-16 2016-08-17 半導體封裝結構 TWI591737B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562219240P 2015-09-16 2015-09-16
US201562264949P 2015-12-09 2015-12-09
US15/203,418 US9941260B2 (en) 2015-09-16 2016-07-06 Fan-out package structure having embedded package substrate

Publications (2)

Publication Number Publication Date
TW201712765A TW201712765A (zh) 2017-04-01
TWI591737B true TWI591737B (zh) 2017-07-11

Family

ID=56893715

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105126197A TWI591737B (zh) 2015-09-16 2016-08-17 半導體封裝結構

Country Status (4)

Country Link
US (1) US9941260B2 (zh)
EP (1) EP3154083B1 (zh)
CN (1) CN106548999A (zh)
TW (1) TWI591737B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102008342B1 (ko) * 2017-07-18 2019-08-07 삼성전자주식회사 팬-아웃 반도체 패키지 및 패키지 기판
US11322449B2 (en) * 2017-10-31 2022-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package with fan-out structures
US11380616B2 (en) * 2018-05-16 2022-07-05 Intel IP Corporation Fan out package-on-package with adhesive die attach
US11342267B2 (en) * 2018-11-23 2022-05-24 Mediatek Inc. Semiconductor package structure and method for forming the same
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 芯片封装结构及其制作方法
US10777518B1 (en) * 2019-05-16 2020-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
KR102584991B1 (ko) * 2019-06-14 2023-10-05 삼성전기주식회사 반도체 패키지
KR102574409B1 (ko) * 2019-07-01 2023-09-04 삼성전기주식회사 반도체 패키지
CN111180426B (zh) * 2019-12-31 2023-09-22 江苏长电科技股份有限公司 一种带石墨烯层散热的封装结构及其制造方法
US11469216B2 (en) * 2020-03-27 2022-10-11 Nanya Technology Corporation Dual-die semiconductor package and manufacturing method thereof
KR20230158584A (ko) * 2021-03-19 2023-11-20 후아웨이 테크놀러지 컴퍼니 리미티드 패키징 어셈블리 및 전자 장치
US20230110957A1 (en) * 2021-10-13 2023-04-13 Mediatek Inc. Electronic device with stacked printed circuit boards

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004140286A (ja) * 2002-10-21 2004-05-13 Nec Semiconductors Kyushu Ltd 半導体装置及びその製造方法
CN1497715A (zh) * 2002-10-21 2004-05-19 恩益禧电子股份有限公司 带有改进的散热器结构的半导体装置
JP4185499B2 (ja) * 2005-02-18 2008-11-26 富士通マイクロエレクトロニクス株式会社 半導体装置
JPWO2007126090A1 (ja) 2006-04-27 2009-09-17 日本電気株式会社 回路基板、電子デバイス装置及び回路基板の製造方法
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US9224647B2 (en) * 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
KR101767108B1 (ko) 2010-12-15 2017-08-11 삼성전자주식회사 하이브리드 기판을 구비하는 반도체 패키지 및 그 제조방법
EP2745317A4 (en) * 2011-08-16 2015-08-12 Intel Corp OFFSET INTERPOSTERS FOR LARGE BOTTOM HOUSINGS AND LARGE CHIP STRUCTURES HOUSING ON HOUSING
US8699232B2 (en) 2011-09-20 2014-04-15 Stats Chippac Ltd. Integrated circuit packaging system with interposer and method of manufacture thereof
US8716065B2 (en) * 2011-09-23 2014-05-06 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation and method of manufacture thereof
SG190487A1 (en) * 2011-11-14 2013-06-28 United Test & Assembly Ct Lt Semiconductor packages and methods of packaging semiconductor devices
US8928134B2 (en) * 2012-12-28 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package bonding structure and method for forming the same
KR20150104467A (ko) * 2014-03-05 2015-09-15 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스

Also Published As

Publication number Publication date
EP3154083A2 (en) 2017-04-12
US20170077073A1 (en) 2017-03-16
TW201712765A (zh) 2017-04-01
EP3154083B1 (en) 2024-08-07
US9941260B2 (en) 2018-04-10
CN106548999A (zh) 2017-03-29
EP3154083A3 (en) 2017-07-26

Similar Documents

Publication Publication Date Title
TWI591737B (zh) 半導體封裝結構
US10692789B2 (en) Stacked fan-out package structure
TWI689055B (zh) 半導體封裝
US9607947B2 (en) Reliable microstrip routing for electronics components
TWI597815B (zh) 半導體封裝結構
US9831214B2 (en) Semiconductor device packages, packaging methods, and packaged semiconductor devices
US10903198B2 (en) Semiconductor package assembly and method for forming the same
TWI685071B (zh) 半導體封裝結構
US20210272930A1 (en) Semiconductor package
US10515887B2 (en) Fan-out package structure having stacked carrier substrates and method for forming the same
US11908759B2 (en) Semiconductor device
TW201530729A (zh) 層疊封裝元件及其製造方法
TWI652787B (zh) 電子封裝件及其製法
TWI849224B (zh) 中介層及具有其的半導體封裝
US11955401B2 (en) Package structure
TW202303881A (zh) 電子封裝件及其製法
TWI676248B (zh) 半導體裝置
TWI793962B (zh) 半導體封裝件和半導體元件
TW516197B (en) Heat sink structure of semiconductor package