TWI587496B - Resistance random access memory - Google Patents
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- TWI587496B TWI587496B TW104103720A TW104103720A TWI587496B TW I587496 B TWI587496 B TW I587496B TW 104103720 A TW104103720 A TW 104103720A TW 104103720 A TW104103720 A TW 104103720A TW I587496 B TWI587496 B TW I587496B
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 14
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 229910052582 BN Inorganic materials 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 89
- 230000015572 biosynthetic process Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- DAIXJPRSBARELR-UHFFFAOYSA-N [N].[B]=O Chemical compound [N].[B]=O DAIXJPRSBARELR-UHFFFAOYSA-N 0.000 description 1
- QEZIKGQWAWNWIR-UHFFFAOYSA-N antimony(3+) antimony(5+) oxygen(2-) Chemical compound [O--].[O--].[O--].[O--].[Sb+3].[Sb+5] QEZIKGQWAWNWIR-UHFFFAOYSA-N 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- -1 oxygen ion Chemical class 0.000 description 1
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- Semiconductor Memories (AREA)
Description
本發明係關於一種電阻式記憶體；特別是關於一種含有不同介電係數材質的電阻式記憶體。 The invention relates to a resistive memory; in particular to a resistive memory containing materials of different dielectric constants.
記憶體(Memory)廣泛的使用在各種電子產品上，隨著資料儲存需求與日俱增，對於記憶體容量以及性能的要求也越來越高，在各種記憶體元件中，電阻式記憶體(RRAM)具有極低的操作電壓、極快的讀寫速度以及高度的元件尺寸可微縮性等優點，有機會取代傳統的快閃記憶體(Flash Memory)以及動態隨機存取記憶體(DRAM)，成為下個世代的記憶體元件主流。 Memory is widely used in various electronic products. As data storage requirements increase, the memory capacity and performance requirements are also increasing. Among various memory components, resistive memory (RRAM) has Extremely low operating voltage, extremely fast read/write speed, and high component size and miniaturization, the opportunity to replace the traditional flash memory and dynamic random access memory (DRAM), the next The mainstream of memory components of generations.
請參閱第1圖所示，其係習知電阻式記憶體之側面剖視圖。其中，習知電阻式記憶體9具有二電極層91及一換阻層92，該換阻層92設置於該二電極層91之間，習知電阻式記憶體具有一形成電壓(約為10伏特，如第2圖所示)，該二電極層91可外加一工作電壓，當該工作電壓大於一形成電壓(Forming Voltage)時，該換阻層92可切換為低阻態(LRS)；當該工作電壓小於該形成電壓時，該換阻層92可切換為高阻態(HRS)，用以儲存兩種邏輯狀態(如：0或1)。 Please refer to FIG. 1 , which is a side cross-sectional view of a conventional resistive memory. The conventional resistive memory 9 has a two-electrode layer 91 and a resistive layer 92. The resistive layer 92 is disposed between the two electrode layers 91. The conventional resistive memory has a forming voltage (about 10). Volt, as shown in FIG. 2, the two electrode layer 91 can be externally applied with an operating voltage, and when the operating voltage is greater than a forming voltage, the resistive layer 92 can be switched to a low resistance state (LRS); When the operating voltage is less than the forming voltage, the resistive layer 92 can be switched to a high resistance state (HRS) for storing two logic states (eg, 0 or 1).
其中，隨著資料處理裝置的體積日趨縮小，記憶體所佔的體積勢必要隨著微縮。惟，習知電阻式記憶體的形成電壓會隨元件體積(via size)縮小而升高，若形成電壓過高則會造成記憶體元件在集成電路中操作上的問題(如：耗電量大等)，為了避免形成電壓過高，雖可將電阻式記憶 體的換阻層厚度降低，但換阻層厚度降低將造成記憶體元件的工作穩定度降低(如：讀取電流變動量大)，可能會導致資料讀取錯誤或其他不可回復性之損害。 Among them, as the volume of the data processing device shrinks, the volume occupied by the memory must be reduced. However, the formation voltage of the conventional resistive memory increases as the via size decreases. If the voltage is too high, the memory component operates in the integrated circuit (eg, the power consumption is large). Etc.), in order to avoid the formation of excessive voltage, although resistive memory The thickness of the body's resistive layer is reduced, but the reduced thickness of the resistive layer will result in a decrease in the operational stability of the memory device (eg, a large amount of read current variation), which may result in data reading errors or other non-recoverable damage.
有鑑於此，上述先前技術在實際使用時確有不便之處，亟需進一步改良，以提升其實用性。 In view of this, the above prior art has inconvenience in actual use, and further improvement is needed to improve its practicability.
本發明係提供一種電阻式記憶體，可降低操作時的形成電壓。 The present invention provides a resistive memory that reduces the formation voltage during operation.
本發明揭示一種電阻式記憶體，包含：一第一電極層；一第一介電層，設於該第一電極層；一第二介電層，設於該第一介電層，該第二介電層的介電常數與該第一介電層的介電常數不同；及一第二電極層，設於該第二介電層；其中，該第一介電層及該第二介電層中的一層係由氮化硼、氮硼氧化物或四氮化三矽構成，該第一介電層及該第二介電層中的另一層係由二氧化鉿構成。 The present invention discloses a resistive memory comprising: a first electrode layer; a first dielectric layer disposed on the first electrode layer; and a second dielectric layer disposed on the first dielectric layer, the first The dielectric constant of the second dielectric layer is different from the dielectric constant of the first dielectric layer; and a second electrode layer is disposed on the second dielectric layer; wherein the first dielectric layer and the second dielectric layer One of the layers of the electrical layer is composed of boron nitride, boron oxynitride or tetra-nitride, and the other of the first dielectric layer and the second dielectric layer is composed of hafnium oxide.
所述第二介電層的介電常數可大於該第一介電層的介電常數。 The dielectric constant of the second dielectric layer may be greater than the dielectric constant of the first dielectric layer.
所述第二介電層的介電常數可小於該第一介電層的介電常數。 The dielectric constant of the second dielectric layer may be less than the dielectric constant of the first dielectric layer.
所述第一介電層的介電常數範圍可為2至25。 The first dielectric layer may have a dielectric constant ranging from 2 to 25.
所述第二介電層的介電常數範圍可為5至50。 The second dielectric layer may have a dielectric constant ranging from 5 to 50.
所述第一介電層的介電常數範圍可為5至50。 The first dielectric layer may have a dielectric constant ranging from 5 to 50.
所述第二介電層的介電常數範圍可為2至25。 The second dielectric layer may have a dielectric constant ranging from 2 to 25.
所述第一電極層可由氮化鈦或鉑構成。 The first electrode layer may be composed of titanium nitride or platinum.
所述第二電極層可由銦錫氧化物或鉑構成。 The second electrode layer may be composed of indium tin oxide or platinum.
上揭電阻式記憶體，利用不同介電常數的材料共同構成該換 阻層，利用該第一、二電極層間的換阻層介電常數的變化，可於切換高/低阻態時，降低其形成電壓，並維持操作穩定性。故，本發明電阻式記憶體實施例可以達成「降低形成電壓」功效，改善習知電阻式記憶體之形成電壓降低導致工作穩定度不佳問題。 Removing the resistive memory, using materials with different dielectric constants to form the replacement The resist layer can change the formation voltage and maintain the operational stability when switching the high/low resistance state by using the change of the dielectric constant of the resistance layer between the first and second electrode layers. Therefore, the resistive memory embodiment of the present invention can achieve the effect of "reducing the voltage formation" and improving the formation voltage of the conventional resistive memory, resulting in poor work stability.
1‧‧‧第一電極層 1‧‧‧First electrode layer
2‧‧‧第一介電層 2‧‧‧First dielectric layer
3‧‧‧第二介電層 3‧‧‧Second dielectric layer
4‧‧‧第二電極層 4‧‧‧Second electrode layer
9‧‧‧習知電阻式記憶體 9‧‧‧Looking Resistive Memory
91‧‧‧電極層 91‧‧‧Electrical layer
92‧‧‧換阻層 92‧‧‧Replacement layer
第1圖：係習知電阻式記憶體之側面剖視圖。 Fig. 1 is a side cross-sectional view showing a conventional resistive memory.
第2圖：係習知電阻式記憶體之電性曲線圖。 Figure 2: Electrical diagram of a conventional resistive memory.
第3圖：係本發明電阻式記憶體實施例之側面剖視圖。 Figure 3 is a side cross-sectional view showing an embodiment of the resistive memory of the present invention.
第4圖：係本發明電阻式記憶體實施例之電性曲線圖。 Fig. 4 is an electrical graph of an embodiment of the resistive memory of the present invention.
為讓本發明之上述及其他目的、特徵及優點能更明顯易懂，下文特舉本發明之較佳實施例，並配合所附圖式，作詳細說明如下：請參閱第3圖所示，其係本發明電阻式記憶體實施例的側面剖視圖。其中，該電阻式記憶體實施例可包含一第一電極層1、一第一介電層2、一第二介電層3及一第二電極層4，該第一介電層2設於該第一電極層1，該第二介電層3設於該第一介電層2，該第二電極層4設於該第二介電層3，該第二介電層3的介電常數(K2)與該第一介電層2的介電常數(K1)不同。 The above and other objects, features and advantages of the present invention will become more <RTIgt; It is a side cross-sectional view of an embodiment of a resistive memory of the present invention. The resistive memory embodiment may include a first electrode layer 1, a first dielectric layer 2, a second dielectric layer 3, and a second electrode layer 4. The first dielectric layer 2 is disposed on The first electrode layer 1 is disposed on the first dielectric layer 2, the second electrode layer 4 is disposed on the second dielectric layer 3, and the dielectric of the second dielectric layer 3 is The constant (K2) is different from the dielectric constant (K1) of the first dielectric layer 2.
在此實施例中，該第一電極層1可由導電材料構成，如：氮化鈦(TiN)或鉑(Pt)等，該第二電極層4可由導電材料構成，如：銦錫氧化物(ITO)或鉑(Pt)等，該第二電極層4與第一電極層1可用以施加一工作電壓至該電阻式記憶體；該第一介電層2與第二介電層3可由不同介電材構成，該第二介電層3的介電常數可大於該第一介電層2的介電常數，該第二介電層3的介電常數亦可小於該第一介電層2的介電常數，例 如：該第一介電層2可由低介電常數(如：K值為2~25)之材料構成，如：氮化硼(BN)、氮硼氧化物(BNO)、二氧化矽(SiO2)或四氮化三矽(Si3N4)等；該第二介電層3可由高介電常數(如：K值為5~50)之材料構成，如：二氧化鉿(HfO2)等，惟不以此為限。此外，該第二介電層3與該第一介電層2的材料或位置亦可互換，使該第一電極層1與第二電極層4間的材料具有不同介電常數。 In this embodiment, the first electrode layer 1 may be composed of a conductive material such as titanium nitride (TiN) or platinum (Pt), etc., and the second electrode layer 4 may be composed of a conductive material such as indium tin oxide ( ITO) or platinum (Pt), etc., the second electrode layer 4 and the first electrode layer 1 can be used to apply an operating voltage to the resistive memory; the first dielectric layer 2 and the second dielectric layer 3 can be different. The second dielectric layer 3 has a dielectric constant greater than a dielectric constant of the first dielectric layer 2, and the second dielectric layer 3 may have a lower dielectric constant than the first dielectric layer. The dielectric constant of 2, for example, the first dielectric layer 2 may be composed of a material having a low dielectric constant (for example, a K value of 2 to 25), such as boron nitride (BN) or nitrogen boron oxide (BNO). , SiO 2 or Si 3 N 4 , etc.; the second dielectric layer 3 may be composed of a material having a high dielectric constant (for example, a K value of 5 to 50), such as: Antimony dioxide (HfO 2 ), etc., but not limited to this. In addition, the material or position of the second dielectric layer 3 and the first dielectric layer 2 may be interchanged, so that the materials between the first electrode layer 1 and the second electrode layer 4 have different dielectric constants.
請再參閱第3圖所示，本發明電阻式記憶體實施例使用時，可於該第一電極層1及第二電極層4施加一外在電場(圖未繪示)，利用該第二介電層3與該第一介電層2共同構成一換阻層，用以切換該電阻式記憶體實施例為高阻態(HRS)或低阻態(LRS)，以便利用電阻式記憶體之形成效應(Forming Effect)作用時所產生的崩潰(breakdown)行為，在該第二介電層3與該第一介電層2中介電常數較低者(即一較快崩潰層)崩潰時，產生出大量氧離子遷移，使該第二介電層3與該第一介電層2中介電常數較高者(即一較慢崩潰層)亦崩潰，於是崩潰電壓將以該較快崩饋層為主，以降低形成電壓。 Referring to FIG. 3 again, when the resistive memory embodiment of the present invention is used, an external electric field (not shown) may be applied to the first electrode layer 1 and the second electrode layer 4, and the second The dielectric layer 3 and the first dielectric layer 2 together form a resistive layer for switching the resistive memory embodiment to a high resistance state (HRS) or a low resistance state (LRS) for utilizing a resistive memory The breakdown behavior generated when the forming effect acts, when the second dielectric layer 3 and the first dielectric layer 2 have lower dielectric constants (ie, a faster collapse layer) Producing a large amount of oxygen ion migration, so that the dielectric constant of the second dielectric layer 3 and the first dielectric layer 2 is higher (ie, a slower collapse layer), and the breakdown voltage will collapse faster. The feed layer is dominant to reduce the formation voltage.
請參閱第4圖所示，其係本發明電阻式記憶體實施例之電性曲線圖。其中，由於該電阻式記憶體實施例之換阻層係由不同介電常數的材料共同構成，利用該介電常數的變化，可於高/低阻態切換時，降低其形成電壓(約為5.8伏特)，相較習知電阻式記憶體之電性曲線圖(如第2圖所示)，本發明電阻式記憶體實施例可大幅降低元件操作時的形成電壓。 Please refer to FIG. 4, which is an electrical graph of an embodiment of the resistive memory of the present invention. Wherein, since the resistive layer of the resistive memory embodiment is composed of materials having different dielectric constants, the change in the dielectric constant can be used to reduce the formation voltage when switching between high and low resistance states (about 5.8 volts, compared to the electrical graph of a conventional resistive memory (as shown in FIG. 2), the resistive memory embodiment of the present invention can significantly reduce the formation voltage during component operation.
藉由前揭之技術手段，本發明電阻式記憶體實施例的主要特點列舉如下：該電阻式記憶體實施例利用不同介電常數的材料共同構成該換阻層，利用該第一、二電極層間的換阻層介電常數的變化，可於切換高/低阻態時，降低其形成電壓，並維持操作穩定性。故，本發明電阻式記憶體實施例可以達成「降低形成電壓」功效，可改善習知電阻式記憶體的形 成電壓降低導致工作穩定度不佳問題。 The main features of the resistive memory embodiment of the present invention are as follows: The resistive memory embodiment uses the materials of different dielectric constants to jointly form the resistive layer, and the first and second electrodes are utilized. The change in the dielectric constant of the interlayer resistance layer can reduce the formation voltage and maintain the operational stability when switching the high/low resistance state. Therefore, the resistive memory embodiment of the present invention can achieve the effect of "reducing the voltage formation" and can improve the shape of the conventional resistive memory. The reduced voltage results in poor work stability.
雖然本發明已利用上述較佳實施例揭示，然其並非用以限定本發明，任何熟習此技藝者在不脫離本發明之精神和範圍之內，相對上述實施例進行各種更動與修改仍屬本發明所保護之技術範疇，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the invention has been described in connection with the preferred embodiments described above, it is not intended to limit the scope of the invention. The technical scope of the invention is protected, and therefore the scope of the invention is defined by the scope of the appended claims.
1‧‧‧第一電極層 1‧‧‧First electrode layer
2‧‧‧第一介電層 2‧‧‧First dielectric layer
3‧‧‧第二介電層 3‧‧‧Second dielectric layer
4‧‧‧第二電極層 4‧‧‧Second electrode layer
Claims (9)
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200931523A (en) * | 2007-10-22 | 2009-07-16 | Applied Materials Inc | Methods and systems for forming at least one dielectric layer |
| TW201424010A (en) * | 2012-10-31 | 2014-06-16 | Hewlett Packard Development Co | Memory cell to prevent charge loss |
| TW201505219A (en) * | 2013-07-17 | 2015-02-01 | Winbond Electronics Corp | Resistive memory and fabricating method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200931523A (en) * | 2007-10-22 | 2009-07-16 | Applied Materials Inc | Methods and systems for forming at least one dielectric layer |
| TW201424010A (en) * | 2012-10-31 | 2014-06-16 | Hewlett Packard Development Co | Memory cell to prevent charge loss |
| TW201505219A (en) * | 2013-07-17 | 2015-02-01 | Winbond Electronics Corp | Resistive memory and fabricating method thereof |
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