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TWI584264B - Display control circuit and operation method thereof - Google Patents

Display control circuit and operation method thereof Download PDF

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Publication number
TWI584264B
TWI584264B TW105133524A TW105133524A TWI584264B TW I584264 B TWI584264 B TW I584264B TW 105133524 A TW105133524 A TW 105133524A TW 105133524 A TW105133524 A TW 105133524A TW I584264 B TWI584264 B TW I584264B
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Taiwan
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switch
phase
capacitor
coupled
unit
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TW105133524A
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Chinese (zh)
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TW201816760A (en
Inventor
林志隆
陳柏勳
賴柏君
洪嘉澤
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友達光電股份有限公司
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Priority to TW105133524A priority Critical patent/TWI584264B/en
Priority to CN201611079532.4A priority patent/CN106652935B/en
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Publication of TWI584264B publication Critical patent/TWI584264B/en
Publication of TW201816760A publication Critical patent/TW201816760A/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • G09G3/3688Details of drivers for data electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3696Generation of voltages supplied to electrode drivers

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Description

顯示控制電路及其操作方法Display control circuit and operation method thereof

本發明係關於一種顯示控制電路,尤指一種包含充電單元、寫入單元、維持單元,從而可控制對於液晶電容之充電狀態的顯示控制電路。The present invention relates to a display control circuit, and more particularly to a display control circuit including a charging unit, a writing unit, and a holding unit so as to control the state of charge of the liquid crystal capacitor.

於液晶顯示領域,顯示控制電路(例如液晶顯示器的畫素控制電路)中,作為源極隨耦器(source follower)之驅動電晶體可控制資料電壓是否寫入液晶電容。然而,此驅動電晶體易隨長時間使用而老化,導致影響液晶顯示的灰階準確度。In the field of liquid crystal display, in a display control circuit (for example, a pixel control circuit of a liquid crystal display), a driving transistor serving as a source follower can control whether a data voltage is written to a liquid crystal capacitor. However, this driving transistor is prone to ageing with long-term use, resulting in an influence on the gray scale accuracy of the liquid crystal display.

目前本領域可見六電晶體-二電容(又稱6T2C)架構之顯示控制電路,其可偵測源極隨耦器之電晶體的臨界電壓漂移,予以補償,從而緩解電晶體老化的影響。6T2C架構的顯示控制電路包含六個電晶體及二個電容,四條控制線及三條參考電源線,共七條訊號線。At present, the display control circuit of the six-transistor-two-capacitor (also known as 6T2C) architecture can be seen in the art, which can detect the threshold voltage drift of the source follower transistor and compensate it, thereby alleviating the influence of the aging of the transistor. The display control circuit of the 6T2C architecture consists of six transistors and two capacitors, four control lines and three reference power lines, for a total of seven signal lines.

此外,目前本領域可見六電晶體-三電容(又稱6T3C)架構的顯示控制電路,其亦可用以補償驅動電晶體的臨界電壓漂移。6T3C架構之顯示控制電路包含六個電晶體及三個電容,三條控制線及二條參考電源線,共五條訊號線。In addition, at present, a display control circuit of a six-transistor-three capacitor (also known as 6T3C) architecture can be seen in the art, which can also be used to compensate for the threshold voltage drift of the driving transistor. The display control circuit of the 6T3C architecture consists of six transistors and three capacitors, three control lines and two reference power lines, for a total of five signal lines.

如上述,當前的顯示控制電路,通常至少包含六個電晶體、及五至七條訊號線。上述6T2C架構及6T3C架構之顯示控制電路,結構皆較為複雜、元件及訊號線數目過多,導致開口率(aperture ratio)過低,透光效果不佳。因此,液晶顯示領域仍須更佳解決方案,以提高開口率、簡化電路結構、降低元件及訊號線之數量、並避免電晶體老化導致顯示灰階準確度不良。As mentioned above, current display control circuits typically include at least six transistors and five to seven signal lines. The display control circuits of the above 6T2C architecture and 6T3C architecture are complicated in structure, and the number of components and signal lines is too large, resulting in an aperture ratio being too low and a light transmission effect being poor. Therefore, there is still a need for a better solution in the field of liquid crystal display to increase the aperture ratio, simplify the circuit structure, reduce the number of components and signal lines, and avoid the deterioration of display gray scale due to aging of the transistor.

本發明一實施例提供一種顯示控制電路,包含一液晶電容、一充電單元、一寫入單元、一維持單元及一第一電容。液晶電容包含一第一端及一第二端,液晶電容之第二端係耦接於一共電壓端,用以根據一資料電壓顯示。充電單元包含第一端、控制端及第二端,充電單元之第二端係耦接於液晶電容之第一端。寫入單元包含第一端、第二端及控制端,寫入單元的第一端係用以接收資料電壓。維持單元包含第一端、第二端及控制端,維持單元的第一端耦接於寫入單元之第二端,維持單元的第二端耦接於液晶電容之第一端。第一電容包含第一端及第二端,第一電容的第一端耦接於充電單元之控制端,第一電容的第二端耦接於寫入單元之第二端。An embodiment of the present invention provides a display control circuit including a liquid crystal capacitor, a charging unit, a writing unit, a sustaining unit, and a first capacitor. The liquid crystal capacitor includes a first end and a second end, and the second end of the liquid crystal capacitor is coupled to a common voltage terminal for displaying according to a data voltage. The charging unit includes a first end, a control end and a second end, and the second end of the charging unit is coupled to the first end of the liquid crystal capacitor. The writing unit includes a first end, a second end, and a control end, and the first end of the writing unit is configured to receive the data voltage. The sustaining unit includes a first end, a second end, and a control end. The first end of the holding unit is coupled to the second end of the writing unit, and the second end of the maintaining unit is coupled to the first end of the liquid crystal capacitor. The first capacitor includes a first end and a second end. The first end of the first capacitor is coupled to the control end of the charging unit, and the second end of the first capacitor is coupled to the second end of the writing unit.

本發明另一實施例提供一種顯示控制電路之操作方法。顯示控制電路包含液晶電容、充電單元、寫入單元、維持單元、開關及第一電容,充電單元之第一端用以接收操作電壓,液晶電容之第一端耦接於充電單元之第二端,液晶電容之第二端耦接於共電壓端,開關具有第一關及第二端,充電單元之控制端耦接於開關之第二端,第一電容之第一端耦接於充電單元之控制端,第一電容之第二端耦接於寫入單元之第二端,寫入單元之第一端用以接收資料電壓,操作方法包含:於重置階段,維持寫入單元的關閉狀態,開啟開關及維持單元,調整開關之第一端之準位以開啟充電單元,及調整操作電壓以重置液晶電容之第一端之準位;於重置階段之後的補償階段,調整操作電壓以透過充電單元對液晶電容之第一端充電,使液晶電容之第一端被充電到預定準位;於補償階段之後的寫入階段,關閉維持單元及開關,及開啟寫入單元,以使第一電容之第一端被抬升至資料電壓及臨界電壓之和;於寫入階段之後的維持階段,關閉寫入單元,以使液晶電容之第一端的準位實質上對應於資料電壓;以及於維持階段之後的顯示階段,調整開關之第一端之準位,以關閉充電單元。Another embodiment of the present invention provides a method of operating a display control circuit. The display control circuit includes a liquid crystal capacitor, a charging unit, a writing unit, a maintaining unit, a switch and a first capacitor. The first end of the charging unit is configured to receive an operating voltage, and the first end of the liquid crystal capacitor is coupled to the second end of the charging unit The second end of the liquid crystal capacitor is coupled to the common voltage terminal, the switch has a first switch and a second end, and the control end of the charging unit is coupled to the second end of the switch, and the first end of the first capacitor is coupled to the charging unit The second end of the first capacitor is coupled to the second end of the write unit, and the first end of the write unit is configured to receive the data voltage, and the operation method comprises: maintaining the write unit off during the reset phase State, open the switch and the maintenance unit, adjust the level of the first end of the switch to turn on the charging unit, and adjust the operating voltage to reset the level of the first end of the liquid crystal capacitor; during the compensation phase after the reset phase, the adjustment operation The voltage is charged to the first end of the liquid crystal capacitor through the charging unit, so that the first end of the liquid crystal capacitor is charged to a predetermined level; in the writing stage after the compensation phase, the maintaining unit and the switch are turned off, and the opening is performed. Writing the unit such that the first end of the first capacitor is raised to the sum of the data voltage and the threshold voltage; in the sustain phase after the writing phase, the writing unit is turned off to make the level of the first end of the liquid crystal capacitor substantially The upper portion corresponds to the data voltage; and during the display phase after the sustain phase, the level of the first end of the switch is adjusted to turn off the charging unit.

本發明另一實施例提供一種顯示控制電路之操作方法,顯示控制電路包含一充電單元,一寫入單元,一維持單元,一第一電容,一第三開關及一液晶電容,充電單元包含一第一開關及一第二開關,第二開關之一第一端用以接收一操作電壓,第二開關之一第二端耦接於第一開關之一第一端及第三開關之一第一端,第一開關之一控制端耦接於第三開關之一第二端及第一電容之一第一端,第一開關之一第二端耦接於液晶電容之一第一端及維持單元之一第二端,液晶電容之一第二端耦接於一共電壓端,維持單元之一第一端耦接於第一電容之一第二端、及寫入單元之一第二端,寫入單元之一第一端用以接收一資料電壓,操作方法包含:於一重置階段,開啟第二、第三開關、寫入單元及維持單元,以將第一電容之第二端及第一開關之第二端重置到一預定準位,以使第一開關之控制端及第二端的準位差大於一門檻值,進而開啟第一開關;於重置階段之後的一補償階段,關閉寫入單元,以將第一電容之第一端充電到一第一電位,及將第一電容之第二端被充電到第一電位及門檻值之差值;於補償階段之後的一寫入階段,關閉第三開關及維持單元,及開啟寫入單元,以使資料電壓寫入第一電容之第二端,及將第一電容之第一端的準位抬升到資料電壓及門檻值之和;於寫入階段之後的一維持階段,關閉寫入單元,以使第一開關之第二端的準位對應於資料電壓;以及於維持階段之後的一顯示階段,關閉第二開關。Another embodiment of the present invention provides a method for operating a display control circuit. The display control circuit includes a charging unit, a writing unit, a maintaining unit, a first capacitor, a third switch, and a liquid crystal capacitor. The charging unit includes a charging unit. a first switch and a second switch, the first end of the second switch is configured to receive an operating voltage, and the second end of the second switch is coupled to the first end of the first switch and the third switch One end of the first switch is coupled to the second end of the first switch and the first end of the first switch, and the second end of the first switch is coupled to the first end of the liquid crystal capacitor and The second end of one of the liquid crystal capacitors is coupled to a common voltage terminal, and the first end of the one of the sustaining units is coupled to the second end of the first capacitor and the second end of the writing unit The first end of the writing unit is configured to receive a data voltage, and the operating method includes: turning on the second and third switches, the writing unit, and the maintaining unit to reset the second end of the first capacitor during a reset phase And resetting the second end of the first switch to a predetermined level, The level difference between the control end and the second end of the first switch is greater than a threshold value, thereby turning on the first switch; in a compensation phase after the reset phase, the writing unit is turned off to charge the first end of the first capacitor Go to a first potential, and charge the second end of the first capacitor to a difference between the first potential and the threshold; in a write phase after the compensation phase, turn off the third switch and the sustain unit, and turn on the write a unit, wherein the data voltage is written to the second end of the first capacitor, and the level of the first end of the first capacitor is raised to a sum of the data voltage and the threshold value; and the write phase is turned off during a sustain period after the writing phase The unit is input such that the level of the second end of the first switch corresponds to the data voltage; and the second switch is turned off during a display phase subsequent to the sustain phase.

本發明實施例提供之顯示控制電路可具有較簡化的結構、更少的元件數及訊號數,故可使開口率提高,改善顯示功效,此外,本發明實施例提供之顯示控制電路仍可補償電晶體的臨界電壓漂移。The display control circuit provided by the embodiment of the present invention can have a simplified structure, a smaller number of components, and a smaller number of signals, so that the aperture ratio can be improved and the display efficiency can be improved. In addition, the display control circuit provided by the embodiment of the present invention can still compensate. The critical voltage drift of the transistor.

第1圖係本發明實施例之顯示控制電路100的示意圖。顯示控制電路100包含液晶電容110、充電單元120、寫入單元130、維持單元140、第一電容150及第二電容160。液晶電容110包含第一端及第二端,第二端耦接於共電壓端VCOM,用以根據資料電壓Vd顯示。充電單元120可包含第一端,控制端,及第二端,耦接於液晶電容110之第一端。寫入單元130可包含第一端、第二端,及控制端,第一端可用以接收資料電壓Vd。維持單元140可包含第一端、第二端及控制端,維持單元140的第一端耦接於寫入單元130之第二端,第二端耦接於液晶電容110之第一端。第一電容150可包含第一端及第二端,第一端耦接於充電單元120之控制端,第二端耦接於寫入單元130之第二端。第二電容160可包含第一端及第二端,第一端耦接於第一電容150之第二端。 1 is a schematic diagram of a display control circuit 100 in accordance with an embodiment of the present invention. The display control circuit 100 includes a liquid crystal capacitor 110, a charging unit 120, a writing unit 130, a sustaining unit 140, a first capacitor 150, and a second capacitor 160. The liquid crystal capacitor 110 includes a first end and a second end, and the second end is coupled to the common voltage terminal V COM for displaying according to the data voltage Vd. The charging unit 120 can include a first end, a control end, and a second end coupled to the first end of the liquid crystal capacitor 110. The writing unit 130 can include a first end, a second end, and a control end, and the first end can be used to receive the data voltage Vd. The sustaining unit 140 can include a first end, a second end, and a control end. The first end of the holding unit 140 is coupled to the second end of the writing unit 130, and the second end is coupled to the first end of the liquid crystal capacitor 110. The first capacitor 150 can include a first end and a second end. The first end is coupled to the control end of the charging unit 120 , and the second end is coupled to the second end of the writing unit 130 . The second capacitor 160 can include a first end and a second end, and the first end is coupled to the second end of the first capacitor 150.

第2圖係本發明另一實施例之顯示控制電路100a的示意圖。顯示控制電路100a的架構相似於顯示控制電路100,但更可包含維持電容170。維持電容170可包含第一端及第二端,第一端耦接於液晶電容110之第一端,第二端耦接於共電壓端VCOM。維持電容170可幫助液晶電容110維持準位,可視需求使用。液晶電容110係用以表示液晶元件對應之電容,液晶元件係用以發光顯示。 Fig. 2 is a schematic diagram of a display control circuit 100a according to another embodiment of the present invention. The display control circuit 100a has an architecture similar to the display control circuit 100, but may further include a sustain capacitor 170. The sustaining capacitor 170 can include a first end and a second end. The first end is coupled to the first end of the liquid crystal capacitor 110, and the second end is coupled to the common voltage terminal V COM . The sustain capacitor 170 can help the liquid crystal capacitor 110 maintain the level, which can be used as needed. The liquid crystal capacitor 110 is used to indicate the capacitance corresponding to the liquid crystal element, and the liquid crystal element is used for light-emitting display.

第3圖是本發明一實施例之顯示控制電路300的示意圖。顯示控制電路300可基於第1及2圖之架構,以多個開關、電容及訊號線組成。顯示控制電路300中,充電單元120可包含第一開關T1,其可包含第一端,用以接收操作電壓VDD、及第二端,耦接於液晶電容110之第一端。寫入單元130可包含第二開關T2,第二開關T2可包含第一端、控制端以及第二端,第一端用以接收資料電壓Vd,控制端由控制訊號S2控制,第二端耦接於第二電容160之第一端。維持單元140可包含第三開關T3,維持單元140可包含第一端、第二端及控制端,第一端耦接於第二開關T2之第二端,控制端用以接收控制訊號S1,第二端耦接於第一開關T1之第二端。顯示控制電路300可另包含第四開關T4。第四開關T4可包含第一端、第二端及控制端,第一端耦接於第二電容160之第二端,控制端耦接於第三開關T3之控制端且亦由控制訊號S1控制,第二端耦接於第一開關T1之控制端。於本實施例,第四開關T4之第一端及第二電容160之第二端可耦接於參考電位V REFFIG. 3 is a schematic diagram of a display control circuit 300 in accordance with an embodiment of the present invention. The display control circuit 300 can be composed of a plurality of switches, capacitors, and signal lines based on the architectures of FIGS. 1 and 2. In the display control circuit 300, the charging unit 120 can include a first switch T1, which can include a first end for receiving the operating voltage V DD and a second end coupled to the first end of the liquid crystal capacitor 110. The writing unit 130 can include a second switch T2. The second switch T2 can include a first end, a control end, and a second end. The first end is configured to receive the data voltage Vd, the control end is controlled by the control signal S2, and the second end is coupled. Connected to the first end of the second capacitor 160. The maintenance unit 140 may include a third switch T3, the maintenance unit 140 may include a first end, a second end, and a control end, the first end is coupled to the second end of the second switch T2, and the control end is configured to receive the control signal S1, The second end is coupled to the second end of the first switch T1. The display control circuit 300 may further include a fourth switch T4. The fourth switch T4 can include a first end, a second end, and a control end. The first end is coupled to the second end of the second capacitor 160. The control end is coupled to the control end of the third switch T3 and is also controlled by the control signal S1. Control, the second end is coupled to the control end of the first switch T1. In this embodiment, the first end of the fourth switch T4 and the second end of the second capacitor 160 are coupled to the reference potential V REF .

第4圖為第3圖實施例之顯示控制電路300的操作波形圖。第5至9圖可為第3圖的實施例之顯示控制電路300的操作說明圖。第4圖中,控制訊號S1、S2,操作電壓V DD、參考電位V REF之波形係對應於重置階段P1、補償階段P2、寫入階段P3、維持階段P4及顯示階段P5。此五階段可循環進行。 Fig. 4 is an operational waveform diagram of the display control circuit 300 of the embodiment of Fig. 3. 5 to 9 are operational explanatory views of the display control circuit 300 of the embodiment of Fig. 3. In Fig. 4, the waveforms of the control signals S1, S2, the operating voltage V DD , and the reference potential V REF correspond to the reset phase P1, the compensation phase P2, the writing phase P3, the sustain phase P4, and the display phase P5. This five stages can be cycled.

第5圖可對應於顯示階段P5之後的重置階段P1。其中打叉(符號□)之元件表示關閉(off),未打叉之元件表示開啟(on),以下各圖亦同理。於重置階段P1可用控制訊號S2關閉第二開關T2,可用控制訊號S1開啟第三開關T3及第四開關T4,進而使此時高準位V REF_H的參考電位V REF開啟第一開關T1,以重置液晶電容110之第一端(節點C)之準位。此時操作電壓V DD可調整為低準位V DDL,故液晶電容110之第一端(節點C)之準位可透過導通的第一開關T1,被重置到低準位V DDL,第三開關T3的第一端(節點B)也可透過導通的第三開關T3被重置到低準位V DDLThe fifth map may correspond to the reset phase P1 after the display phase P5. The components of the cross (symbol □) indicate off (off), and the uncrossed components indicate on (on), and the following figures are similar. In the reset phase P1, the second switch T2 can be turned off by the control signal S2, and the third switch T3 and the fourth switch T4 can be turned on by the control signal S1, so that the reference potential V REF of the high level V REF_H is turned on at the first switch T1. To reset the level of the first end (node C) of the liquid crystal capacitor 110. At this time, the operating voltage V DD can be adjusted to the low level V DDL , so the level of the first end (node C) of the liquid crystal capacitor 110 can be reset to the low level V DDL through the first switch T1 that is turned on, The first end (node B) of the three switch T3 can also be reset to the low level V DDL through the turned-on third switch T3.

第6圖可對應於重置階段P1之後的補償階段P2。於補償階段,可調整操作電壓V DD為高準位V DDH,並可藉由控制訊號S2持續關閉第二開關T2,藉由控制訊號S1持續開啟第三開關T3及第四開關T4,進而使此時高準位V REF_H的參考電位V REF持續開啟第一開關T1,以透過第一開關T1對液晶電容110之第一端(節點C)充電,使液晶電容110之第一端(節點C)及第三開關T3的第一端(節點B)被充電到使第一開關T1關閉的預定準位。此預定準位可為參考電位V REF及第一開關T1的臨界電壓V TH之差值,即(V REF-V TH)。此階段的參考電位V REF可為高準位V REF_H,故液晶電容110之第一端(節點C)及第三開關T3的第一端(節點B)可被充電到(V REF _H- V TH)之準位,此時第一電容150之第一端(節點A)與第三開關T3的第一端(節點B)的電位差即為臨界電壓V THFigure 6 may correspond to the compensation phase P2 after the reset phase P1. In the compensation phase, the operating voltage V DD can be adjusted to a high level V DDH , and the second switch T2 can be continuously turned off by the control signal S2, and the third switch T3 and the fourth switch T4 can be continuously turned on by the control signal S1, thereby At this time, the reference potential V REF of the high level V REF — H continues to turn on the first switch T1 to charge the first end (node C) of the liquid crystal capacitor 110 through the first switch T1 to make the first end of the liquid crystal capacitor 110 (node C) And the first end (node B) of the third switch T3 is charged to a predetermined level at which the first switch T1 is turned off. The predetermined level can be the difference between the reference potential V REF and the threshold voltage V TH of the first switch T1, that is, (V REF -V TH ). The reference potential V REF at this stage can be the high level V REF — H , so the first end of the liquid crystal capacitor 110 (node C) and the first end of the third switch T3 (node B) can be charged to (V REF _H - V The potential of TH ), at this time, the potential difference between the first end (node A) of the first capacitor 150 and the first end (node B) of the third switch T3 is the threshold voltage V TH .

第7圖可對應於補償階段P2之後的寫入階段P3。於寫入階段P3,可調整控制訊號S1、S2以關閉第三開關T3及第四開關T4,及開啟第二開關T2。由於第一電容150已存有臨界電壓V TH之電位差,故可使第一電容150之第一端(節點A)被抬升至資料電壓Vd及臨界電壓V TH之和,即(Vd+V TH)。 Figure 7 may correspond to the write phase P3 after the compensation phase P2. In the writing phase P3, the control signals S1, S2 can be adjusted to turn off the third switch T3 and the fourth switch T4, and turn on the second switch T2. Since the first capacitor 150 already has a potential difference of the threshold voltage V TH , the first end (node A) of the first capacitor 150 can be raised to the sum of the data voltage Vd and the threshold voltage V TH , that is, (Vd+V TH ).

第8圖可對應於寫入階段P3之後的維持階段P4。於維持階段P4,可調整控制訊號S2以關閉第二開關T2,並可藉由控制訊號S1持續關閉第三開關T3及第四開關T4。此時,第一開關T1的控制端及第二端可具有臨界電壓V TH之壓差,故第一開關T1的第二端(節點C)之準位可為節點A的準位減去臨界電壓V TH。操作電壓V DD可維持在高準位V DDH,以透過第一開關T1持續對節點C充電,從而使維持階段P4中,節點C的準位充到 [(Vd+V TH)-V TH],亦即資料電壓Vd。因此,根據本發明實施例,可於維持階段P4使液晶電容110之第一端(節點C)的準位實質上對應於資料電壓Vd,以使液晶電容110根據資料電壓Vd顯示。 The eighth figure may correspond to the sustain phase P4 after the writing phase P3. In the sustaining phase P4, the control signal S2 can be adjusted to turn off the second switch T2, and the third switch T3 and the fourth switch T4 can be continuously turned off by the control signal S1. At this time, the control terminal and the second terminal of the first switch T1 may have a voltage difference of the threshold voltage V TH , so the level of the second end (node C) of the first switch T1 may be the level of the node A minus the threshold. Voltage V TH . The operating voltage V DD can be maintained at a high level V DDH to continuously charge the node C through the first switch T1, so that the level of the node C is charged to [(Vd+V TH )-V TH in the sustain phase P4] , that is, the data voltage Vd. Therefore, according to the embodiment of the present invention, the level of the first end (node C) of the liquid crystal capacitor 110 can be substantially corresponding to the data voltage Vd in the sustaining phase P4, so that the liquid crystal capacitor 110 is displayed according to the data voltage Vd.

第9圖係可對應於維持階段P4之後的顯示階段P5。於顯示階段P5,可調整參考準位V REF至低準位V REF_L,並可藉由控制訊號S1及控制訊號S2持續關閉第二開關T2、第三開關T3及第四開關T4,使節點B透過第二電容160被耦合到低準位。由於此時節點A、B係透過第一電容150互相浮接,故實質上可視作節點A、B串連。故節點A亦可透過第一電容150被耦合至低準位,從而可關閉第一開關T1。如第9圖所示,顯示階段P5中,液晶電容110可根據資料電壓Vd控制其間所夾之液晶分子的,進而控制通過液晶分子的光的偏極性,進而達到控制畫素灰階的效果。且第一開關T1至第四開關T4皆為關閉,故可減緩開關內的電晶體之老化、並可抑制節點C漏電。 The ninth figure may correspond to the display phase P5 after the maintenance phase P4. In the display phase P5, the reference level V REF can be adjusted to the low level V REFL , and the second switch T2, the third switch T3 and the fourth switch T4 can be continuously turned off by the control signal S1 and the control signal S2 to make the node B The second capacitor 160 is coupled to a low level. Since nodes A and B are floating to each other through the first capacitor 150 at this time, they can be regarded as nodes A and B in series. Therefore, the node A can also be coupled to the low level through the first capacitor 150, so that the first switch T1 can be turned off. As shown in FIG. 9, in the display phase P5, the liquid crystal capacitor 110 can control the liquid crystal molecules sandwiched therebetween according to the data voltage Vd, thereby controlling the polarization of the light passing through the liquid crystal molecules, thereby achieving the effect of controlling the gray scale of the pixels. Moreover, the first switch T1 to the fourth switch T4 are all turned off, so that the aging of the transistor in the switch can be slowed down, and the leakage of the node C can be suppressed.

第10圖係第3至9圖之實施例的量測結果圖。第10圖的橫軸可為時間,其單位可為微秒(μsec),縱軸可為電壓,其單位可為伏特(Volt)。曲線VA0、VA3、VA3’ 可分別為第3、5-9圖之節點A的電壓變化。曲線VC0、VC3、VC3’ 可分別為第3、5-9圖之節點C的電壓變化。其中,曲線VA0、VC0可為電晶體之臨界電壓V TH與預定準位的差值為0伏特,亦即臨界電壓沒有偏移時的量測結果,曲線VA3、VC3可為電晶體之臨界電壓V TH與預定準位的差值為+3伏特,亦即臨界電壓偏移+3伏特時的量測結果,曲線VA3’、VC3’ 可為電晶體之臨界電壓V TH與預定準位的差值為-3伏特,亦即臨界電壓偏移-3伏特時的量測結果。此外,第10圖之波形圖亦可見控制訊號S2,控制訊號S2為高態時可對應於寫入階段P3。由第10圖可見,當臨界電壓V TH於-3至+3伏特的範圍變動,曲線VC0、VC3、VC3’ 的準位,於維持階段P4之後期及顯示階段P5係幾乎相同。換言之,根據本發明之第3至9圖的實施例,液晶電容110的第一端(節點C)的準位可對應於資料電壓Vd發光,而可降低受到臨界電壓V TH之漂移變動影響。 Fig. 10 is a graph showing the measurement results of the examples of Figs. 3 to 9. The horizontal axis of Fig. 10 may be time, the unit may be microseconds (μsec), the vertical axis may be voltage, and the unit may be Volt. The curves VA0, VA3, VA3' can be the voltage changes of node A of the third, fifth, and fifth diagrams, respectively. The curves VC0, VC3, VC3' can be the voltage changes of node C of the third, fifth, and fifth diagrams, respectively. The curves VA0 and VC0 may be the difference between the threshold voltage V TH of the transistor and the predetermined level being 0 volts, that is, the measurement result when the threshold voltage is not offset, and the curves VA3 and VC3 may be the threshold voltage of the transistor. The difference between V TH and the predetermined level is +3 volts, that is, the measurement result when the threshold voltage is shifted by +3 volts, and the curves VA3' and VC3' may be the difference between the threshold voltage V TH of the transistor and the predetermined level. The value is -3 volts, which is the measurement result when the threshold voltage is shifted by -3 volts. In addition, the waveform diagram of FIG. 10 can also be seen as the control signal S2, and the control signal S2 can be corresponding to the writing phase P3 when it is in the high state. As can be seen from Fig. 10, when the threshold voltage VTH varies from -3 to +3 volts, the levels of the curves VC0, VC3, and VC3' are almost the same in the post-maintenance phase P4 and the display phase P5. In other words, according to the embodiments of the third to ninth embodiments of the present invention, the level of the first end (node C) of the liquid crystal capacitor 110 can be illuminated corresponding to the data voltage Vd, and can be reduced by the drift variation of the threshold voltage VTH .

觀之第3至9圖,可見此實施例中,若第一開關T1至第四開關T4皆為電晶體,則顯示控制電路300共有四個電晶體。由於維持電容170可選擇性使用或省略,故顯示控制電路300包含液晶電容110、第一電容150、第二電容160共三個電容。因此,第3至9圖的實施例可提供四電晶體-三電容(可簡稱4T3C)架構的顯示控制電路。訊號線則共有對應於操作電壓V DD、參考電位V REF、控制訊號S1及控制訊號S2等四條訊號線。故相較於前述之6T2C架構(須至少七條訊號線)、或6T3C架構(須至少五條訊號線),本發明之實施例提供的顯示控制電路的元件數及訊號線數皆較少,可提高開口率,且仍具有補償臨界電壓V TH之漂移變動的功效,從而可保持顯示之灰階準確度。 In the third to ninth views, it can be seen that in this embodiment, if the first switch T1 to the fourth switch T4 are all transistors, the display control circuit 300 has four transistors. Since the sustain capacitor 170 can be selectively used or omitted, the display control circuit 300 includes three capacitors of the liquid crystal capacitor 110, the first capacitor 150, and the second capacitor 160. Therefore, the embodiments of FIGS. 3 to 9 can provide a display control circuit of a four-transistor-three-capacitor (referred to as 4T3C) architecture. The signal line has four signal lines corresponding to the operating voltage V DD , the reference potential V REF , the control signal S1 and the control signal S2. Therefore, the number of components and the number of signal lines of the display control circuit provided by the embodiments of the present invention are small compared to the foregoing 6T2C architecture (at least seven signal lines are required) or the 6T3C architecture (at least five signal lines are required). The aperture ratio, and still has the effect of compensating for the drift variation of the threshold voltage VTH , thereby maintaining the grayscale accuracy of the display.

第11圖係本發明實施例的顯示控制電路300之操作步驟流程圖。步驟1110至1150可分別對應第5至9圖之階段:Figure 11 is a flow chart showing the operational steps of the display control circuit 300 of the embodiment of the present invention. Steps 1110 to 1150 may correspond to the stages of Figures 5 to 9, respectively:

步驟1110:於顯示階段P5之後的重置階段P1,維持第二開關T2的關閉狀態,開啟第三開關T3及第四開關T4,調整參考準位V REF至高準位V REF_H以開啟第一開關T1,及調整操作電壓V DD至低準位V DDL以重置液晶電容110之第一端之準位; Step 1110: In the reset phase P1 after the display phase P5, maintaining the closed state of the second switch T2, turning on the third switch T3 and the fourth switch T4, adjusting the reference level V REF to the high level V REF_H to turn on the first switch T1, and adjusting the operating voltage V DD to the low level V DDL to reset the level of the first end of the liquid crystal capacitor 110;

步驟1120:於重置階段P1之後的補償階段P2,調整操作電壓V DD至高準位V DDH,以透過第一開關T1對液晶電容110之第一端充電,使液晶電容110之第一端被充電到預定準位; Step 1120: Adjust the operating voltage V DD to the high level V DDH during the compensation phase P2 after the reset phase P1 to charge the first end of the liquid crystal capacitor 110 through the first switch T1, so that the first end of the liquid crystal capacitor 110 is Charging to a predetermined level;

步驟1130:於補償階段P2之後的寫入階段P3,關閉第三開關T3及第四開關T4,及開啟第二開關T2,以使第一電容110之第一端被抬升至約為資料電壓Vd及臨界電壓V TH之和; Step 1130: In the writing phase P3 after the compensation phase P2, the third switch T3 and the fourth switch T4 are turned off, and the second switch T2 is turned on, so that the first end of the first capacitor 110 is raised to approximately the data voltage Vd. And the sum of the threshold voltages V TH ;

步驟1140:於寫入階段P3之後的維持階段P4,關閉第二開關T2,以使液晶電容110之第一端的準位實質上對應於資料電壓Vd;及Step 1140: In the sustain phase P4 after the writing phase P3, the second switch T2 is turned off, so that the level of the first end of the liquid crystal capacitor 110 substantially corresponds to the data voltage Vd;

步驟1150:於維持階段P4之後的顯示階段P5,調整參考準位V REF至低準位V REF_L,以關閉充電單元120以防止漏電。 Step 1150: In the display phase P5 after the sustain phase P4, the reference level V REF is adjusted to the low level V REFL to turn off the charging unit 120 to prevent leakage.

第12圖係本發明另一實施例的顯示控制電路1100的示意圖。顯示控制電路1100可基於第1及2圖之架構,以多個開關、電容及訊號線組成。如第1、2及11圖所示,顯示控制電路1100中,充電單元120可包含第一開關T1及第二開關T2。第一開關T1可包含第一端、第二端以及控制端,第一開關T1的第二端可為充電單元120之第二端,第一開關T1的控制端可為充電單元120之控制端。第二開關T2可包含第一端、第二端以及控制端,第二開關T2的第一端可為充電單元120之第一端、第二開關T2的第二端可耦接於第一開關T1之第一端、第二開關T2的控制端可由控制訊號S1控制。寫入單元130包含第五開關T5。第五開關T5可包含第一端、第二端以及控制端,第五開關T5的第一端可用以接收資料電壓Vd、第五開關T5的控制端可由控制訊號S3控制、第五開關T5的第二端可耦接於第一電容150之第二端。維持單元140可包含第四開關T4,第四開關T4的控制端可由控制訊號S2控制。顯示控制電路1100可另包含第三開關T3,第三開關T3可包含第一端、第二端以及控制端,第三開關T3的第一端可耦接於第一電晶體T1之第一端,第三開關T3的控制端可耦接於維持單元140之控制端,也由控制訊號S2控制、第三開關T3的第二端可耦接於第一電容150之第一端。根據本發明實施例,顯示控制電路1100的第二電容160之第二端可(但不限於)耦接於共電壓端V COMFigure 12 is a schematic illustration of a display control circuit 1100 in accordance with another embodiment of the present invention. The display control circuit 1100 can be composed of a plurality of switches, capacitors, and signal lines based on the architectures of FIGS. 1 and 2. As shown in the first, second and eleventh diagrams, in the display control circuit 1100, the charging unit 120 may include a first switch T1 and a second switch T2. The first switch T1 can include a first end, a second end, and a control end. The second end of the first switch T1 can be the second end of the charging unit 120, and the control end of the first switch T1 can be the control end of the charging unit 120. . The second switch T2 can include a first end, a second end, and a control end. The first end of the second switch T2 can be the first end of the charging unit 120, and the second end of the second switch T2 can be coupled to the first switch. The first end of T1 and the control end of the second switch T2 can be controlled by the control signal S1. The writing unit 130 includes a fifth switch T5. The fifth switch T5 can include a first end, a second end, and a control end. The first end of the fifth switch T5 can be used to receive the data voltage Vd, and the control end of the fifth switch T5 can be controlled by the control signal S3, and the fifth switch T5. The second end is coupled to the second end of the first capacitor 150. The maintaining unit 140 may include a fourth switch T4, and the control end of the fourth switch T4 may be controlled by the control signal S2. The display control circuit 1100 can further include a third switch T3. The third switch T3 can include a first end, a second end, and a control end. The first end of the third switch T3 can be coupled to the first end of the first transistor T1. The control terminal of the third switch T3 is coupled to the control terminal of the maintenance unit 140, and is also controlled by the control signal S2. The second end of the third switch T3 can be coupled to the first end of the first capacitor 150. According to an embodiment of the invention, the second end of the second capacitor 160 of the display control circuit 1100 can be coupled to the common voltage terminal V COM , but not limited to.

第13圖係第12圖實施例之顯示控制電路1100的操作波形圖。第14至18圖可為第12圖的實施例之顯示控制電路1100的操作說明圖。第13圖中,控制訊號S1、S2及S3、操作電壓V DD之波形可被調整以對應重置階段P1、重置階段P1、補償階段P2、寫入階段P3、維持階段P4及顯示階段P5。此五階段可循環進行。 Fig. 13 is an operation waveform diagram of the display control circuit 1100 of the embodiment of Fig. 12. 14 to 18 are operational explanatory diagrams of the display control circuit 1100 of the embodiment of Fig. 12. In Fig. 13, the waveforms of the control signals S1, S2 and S3 and the operating voltage V DD can be adjusted to correspond to the reset phase P1, the reset phase P1, the compensation phase P2, the write phase P3, the sustain phase P4, and the display phase P5. . This five stages can be cycled.

第14圖可對應於顯示階段P5之後的重置階段P1。於重置階段P1,可開啟第二至第五開關T2-T5,資料電壓Vd可將第二電容160之第一端(節點C)及第一開關T1之第二端(節點B)重置到預定準位,例如足夠低的準位。當節點A及節點B的電位差達到第一開關T1之臨界電壓VTH,則可使第一開關T1導通。 The 14th figure may correspond to the reset phase P1 after the display phase P5. In the reset phase P1, the second to fifth switches T2-T5 may be turned on, and the data voltage Vd may reset the first end (node C) of the second capacitor 160 and the second end (node B) of the first switch T1 To a predetermined level, such as a sufficiently low level. When the potential difference between the node A and the node B reaches the threshold voltage V TH of the first switch T1, the first switch T1 can be turned on.

第15圖可對應於重置階段P1之後的補償階段P2。補償階段P2中,可調整控制訊號S3以關閉第五開關T5,以使操作電壓VDD將第一電容150之第一端(節點A)被充電到第一電位(如操作電壓VDD的高準位VDDH),及將第一電容150之第二端(節點C)被充電到第一電位及門檻值VTH1之差值。因此,操作電壓VDD可透過第一開關T1、第二開關T2,將節點B、C之電位充電至(VDDH-VTH1)的準位,從而使第一電容150儲存門檻值VTH1之電位差。門檻值VTH1可為第一開關T1的臨界電壓VTHFigure 15 may correspond to the compensation phase P2 after the reset phase P1. In the compensation phase P2, the control signal S3 can be adjusted to turn off the fifth switch T5, so that the operating voltage V DD charges the first end (node A) of the first capacitor 150 to the first potential (eg, the operating voltage V DD is high) The level V DDH ), and the second end (node C) of the first capacitor 150 is charged to a difference between the first potential and the threshold value V TH1 . Therefore, the operating voltage V DD can pass through the first switch T1 and the second switch T2 to charge the potentials of the nodes B and C to the level of (V DDH -V TH1 ), so that the first capacitor 150 stores the threshold value V TH1 . Potential difference. The threshold value V TH1 may be the threshold voltage V TH of the first switch T1.

第16圖可對應於補償階段P2之後的寫入階段P3。寫入階段P3中,可控制控制訊號S2、S3,以關閉第三開關T3及第四開關T4,及開啟第五開關T5,從而使資料電壓Vd寫入第一電容150之第二端(節點C),及將第一電容150之第一端(節點A)的準位抬升到資料電壓Vd及門檻值VTH1之和。此時操作電壓VDD可調整為低準位VDDL,故節點B可透過第一開關T1及第二開關T2被拉至低準位VDDL,以使第一開關T1的控制端及第二端的電壓差足以確保第一開關T1開啟。 Figure 16 may correspond to the write phase P3 after the compensation phase P2. In the writing phase P3, the control signals S2, S3 can be controlled to turn off the third switch T3 and the fourth switch T4, and turn on the fifth switch T5, so that the data voltage Vd is written to the second end of the first capacitor 150 (node C), and raising the level of the first end (node A) of the first capacitor 150 to the sum of the data voltage Vd and the threshold value V TH1 . At this time, the operating voltage V DD can be adjusted to the low level V DDL , so the node B can be pulled to the low level V DDL through the first switch T1 and the second switch T2 to make the control end and the second end of the first switch T1 The voltage difference at the terminals is sufficient to ensure that the first switch T1 is turned on.

第17圖可對應於寫入階段P3之後的維持階段P4。此階段可調整控制 訊號S3以關閉第五開關T5。操作電壓VDD可調整為高準位VDDH,以透過第一開關T1及第二開關T2對液晶電容110之第一端(節點B)充電。此時,第一開關T1與第二開關T2可為源極隨耦器(source follower),節點B可由寫入階段P3的低位準VDDL,被充電到節點A的位準及門檻值VTH1之差值,即{(Vd+VTH1)-VTH1},也就是資料電壓Vd。因此,維持階段P4可控制對於節點B充電的時間長度,且可使第一開關T1之第二端的準位對應於資料電壓Vd。 The 17th figure may correspond to the sustaining phase P4 after the writing phase P3. At this stage, the control signal S3 can be adjusted to turn off the fifth switch T5. The operating voltage V DD can be adjusted to a high level V DDH to charge the first end (node B) of the liquid crystal capacitor 110 through the first switch T1 and the second switch T2. At this time, the first switch T1 and the second switch T2 may be source followers, and the node B may be charged to the level of the node A and the threshold value V TH1 by the low level V DDL of the writing phase P3. The difference, ie {(Vd+V TH1 )-V TH1 }, is the data voltage Vd. Therefore, the sustain phase P4 can control the length of time for charging the node B, and can make the level of the second end of the first switch T1 correspond to the data voltage Vd.

第18圖可對應於維持階段P4之後的顯示階段P5。於顯示階段P5可調整控制訊號S1以關閉第二開關T2,以防止節點B的漏電。從而達到抑制電晶體老化的功效。 The figure 18 may correspond to the display phase P5 after the maintenance phase P4. In the display phase P5, the control signal S1 can be adjusted to turn off the second switch T2 to prevent leakage of the node B. Thereby achieving the effect of inhibiting the aging of the transistor.

第19圖係第11至17圖之實施例的量測結果圖。同理於第10圖,其橫軸可為時間(單位係微秒),縱軸可為電壓(單位為伏特)。曲線VA0、VB0、VC0分別為第12圖的節點A、B、C的準位變化,其可對應於開關之臨界電壓VTH與預定準位的差值是0伏特(即臨界電壓沒有偏移)的電晶體之電路。曲線VA3、VB3、VC3分別為第12圖的節點A、B、C的準位變化,其可對應於開關的臨界電壓VTH與預定準位的差值是+3伏特(即臨界電壓偏移+3伏特)的電晶體之電路。根據第18圖,曲線VB0、VB3於維持階段P4後段至顯示階段P5係幾乎疊合,故節點B的位準可不受門檻電壓VTH的漂移影響,從而可保持液晶電容110的發光灰階準確度。第12至19圖之實施例的顯示控制電路1100包含五個電晶體(T1至T5)、及三個電容(110、150、160),可簡稱5T3C架構,其訊號線至少須四條(對應於控制訊號S1-S3及操作電壓VDD),因此,相較於習知的6T2C架構(須至少七條訊號線)、或6T3C架構(須至少五條訊號線),本發明實施例提供的顯示控制電路之元件數及訊號線數皆較少,可提高開口率,且仍具有補償臨界電壓VTH之 漂移變動的功效,從而可保持顯示之灰階準確度。 Fig. 19 is a graph showing the measurement results of the examples of Figs. 11 to 17. Similarly, in Figure 10, the horizontal axis can be time (in microseconds) and the vertical axis can be voltage (in volts). The curves VA0, VB0, and VC0 are the level changes of the nodes A, B, and C of FIG. 12, respectively, which may correspond to the threshold voltage V TH of the switch and the difference of the predetermined level is 0 volts (ie, the threshold voltage is not offset) The circuit of the transistor. The curves VA3, VB3, and VC3 are the level changes of the nodes A, B, and C of FIG. 12, respectively, which may correspond to the threshold voltage V TH of the switch and the difference of the predetermined level is +3 volts (ie, the threshold voltage offset) +3 volt) circuit of the transistor. According to FIG. 18, the curves VB0 and VB3 are almost superposed in the latter stage of the sustaining phase P4 to the display phase P5, so that the level of the node B can be prevented from being affected by the drift of the threshold voltage VTH , thereby maintaining the accurate gray scale of the liquid crystal capacitor 110. degree. The display control circuit 1100 of the embodiment of FIGS. 12 to 19 includes five transistors (T1 to T5) and three capacitors (110, 150, 160), which may be referred to as a 5T3C architecture, and the signal lines must be at least four (corresponding to Control signal S1-S3 and operating voltage V DD ), therefore, the display control circuit provided by the embodiment of the present invention is compared with the conventional 6T2C architecture (at least seven signal lines are required) or the 6T3C architecture (at least five signal lines are required) The number of components and the number of signal lines are small, the aperture ratio can be increased, and the effect of compensating for the drift variation of the threshold voltage V TH can be maintained, thereby maintaining the gray scale accuracy of the display.

第20圖係第12至18圖所示的顯示控制電路1100之操作方法流程圖。步驟2010至2050可對應於第14至18圖:步驟2010:於顯示階段P5之後的重置階段P1,開啟第二至第五開關T2-T5,以將第二電容160之第一端及第一開關T1之第二端重置到預定準位,以使第一開關T1之控制端及第二端的準位差大於門檻值VTH1,進而開啟第一開關T1;步驟2020:於重置階段P1之後的補償階段P2,關閉第五開關T5以將第一電容150之第一端被充電到第一電位(如高準位VDDH),及將第一電容150之第二端被充電到第一電位及門檻值VTH1之差值,如(VDDH-VTH1);步驟2030:於補償階段P2之後的寫入階段P3,關閉第三開關T3及第四開關T4,及開啟第五開關T5,以使資料電壓Vd寫入第一電容150之第二端,及將第一電容150之第一端的準位抬升到約為資料電壓Vd及門檻值VTH1之和;步驟2040:於寫入階段P3之後的維持階段P4,關閉第五開關T5,以使第一開關T1之第二端的準位對應於資料電壓Vd;及步驟2050:於維持階段P4之後的顯示階段P5,關閉第二開關T2,以防止漏電。 Figure 20 is a flow chart showing the operation of the display control circuit 1100 shown in Figures 12 to 18. Steps 2010 to 2050 may correspond to the 14th to 18th drawings: Step 2010: In the reset phase P1 after the display phase P5, the second to fifth switches T2-T5 are turned on to set the first end of the second capacitor 160 and the first The second end of the switch T1 is reset to a predetermined level, so that the level difference between the control end and the second end of the first switch T1 is greater than the threshold value V TH1 , thereby turning on the first switch T1; step 2020: in the reset phase In the compensation phase P2 after P1, the fifth switch T5 is turned off to charge the first end of the first capacitor 150 to the first potential (such as the high level V DDH ), and the second end of the first capacitor 150 is charged to The difference between the first potential and the threshold value V TH1 , such as (V DDH -V TH1 ); Step 2030: In the writing phase P3 after the compensation phase P2, the third switch T3 and the fourth switch T4 are turned off, and the fifth is turned on. The switch T5 is configured to write the data voltage Vd to the second end of the first capacitor 150, and raise the level of the first end of the first capacitor 150 to a sum of the data voltage Vd and the threshold value V TH1 ; step 2040: In the sustain phase P4 after the writing phase P3, the fifth switch T5 is turned off, so that the level of the second end of the first switch T1 corresponds to Voltage Vd is material; and Step 2050: in stage P5 after displaying the maintenance phase P4, turn off the second switch T2, to prevent leakage.

上述各開關,可採用常關型(normally-OFF)或常開型(normally-ON)電晶體,並可依研發者之需求挑選N型金氧半場效電晶體、P型金氧半場效電晶體、雙載子接面電晶體或其他相似原理之開關元件。本發明實施例提供之顯示控制電路可適用於一般液晶顯示,亦可適用於藍相液晶。For each of the above switches, a normally-off or normally-on transistor can be used, and the N-type gold-oxygen half-field effect transistor and the P-type gold-oxygen half-field effect transistor can be selected according to the needs of the developer. Crystal, bipolar junction transistor or other switching element of similar principle. The display control circuit provided by the embodiment of the invention can be applied to a general liquid crystal display, and can also be applied to a blue phase liquid crystal.

綜上,本發明實施例提供之顯示控制電路可具有較簡化的結構、更少的元件數及訊號數,故可使開口率提高,改善顯示功效,此外,本發明實施例提供之顯示控制電路仍可補償電晶體的臨界電壓漂移,故可保持液晶顯示之灰階準確度,對於改善本領域習知的顯示控制電路之缺失,實有助益。   以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。In summary, the display control circuit provided by the embodiment of the present invention can have a simplified structure, a smaller number of components, and a smaller number of signals, so that the aperture ratio can be improved and the display efficiency can be improved. In addition, the display control circuit provided by the embodiment of the present invention is provided. The threshold voltage drift of the transistor can still be compensated, so that the gray scale accuracy of the liquid crystal display can be maintained, which is helpful for improving the lack of the display control circuit known in the art. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100、100a、300、1100‧‧‧顯示控制電路100, 100a, 300, 1100‧‧‧ display control circuit

110‧‧‧液晶電容110‧‧‧Liquid Crystal Capacitor

120‧‧‧充電單元120‧‧‧Charging unit

130‧‧‧寫入單元130‧‧‧Write unit

140‧‧‧維持單元140‧‧‧Maintenance unit

150‧‧‧第一電容150‧‧‧first capacitor

160‧‧‧第二電容160‧‧‧second capacitor

170‧‧‧維持電容170‧‧‧Maintenance capacitor

Vd‧‧‧資料電壓Vd‧‧‧ data voltage

VCOM‧‧‧共電壓端V COM ‧‧‧Common voltage terminal

VDD‧‧‧操作電壓V DD ‧‧‧ operating voltage

VDDH、VREF_H‧‧‧高準位V DDH , V REF_H ‧‧‧ high level

VDDL、VREF_L‧‧‧低準位V DDL , V REF_L ‧‧‧ low level

S1、S2、S3‧‧‧控制訊號S1, S2, S3‧‧‧ control signals

VREF‧‧‧參考電位V REF ‧‧‧ reference potential

VA0、VA3、VA3’、VC0、VC3、VC3’、VB0、VB3‧‧‧曲線VA0, VA3, VA3', VC0, VC3, VC3', VB0, VB3‧‧‧ curves

VTH‧‧‧臨界電壓V TH ‧‧‧ threshold voltage

VTH1‧‧‧門檻值V TH1 ‧‧‧ threshold

A、B、C‧‧‧節點A, B, C‧‧‧ nodes

P1‧‧‧重置階段P1‧‧‧Reset phase

P2‧‧‧補償階段P2‧‧‧ Compensation phase

P3‧‧‧寫入階段P3‧‧‧writing stage

P4‧‧‧維持階段P4‧‧‧Maintenance phase

P5‧‧‧顯示階段P5‧‧‧ display stage

T1‧‧‧第一開關T1‧‧‧ first switch

T2‧‧‧第二開關T2‧‧‧ second switch

T3‧‧‧第三開關T3‧‧‧ third switch

T4‧‧‧第四開關T4‧‧‧fourth switch

T5‧‧‧第五開關T5‧‧‧ fifth switch

1110至1150、2010至2050‧‧‧步驟1110 to 1150, 2010 to 2050‧‧ steps

第1圖係本發明實施例之顯示控制電路的示意圖。 第2圖係本發明另一實施例之顯示控制電路的示意圖。 第3圖是本發明一實施例之顯示控制電路的示意圖。 第4圖係第3圖實施例之顯示控制電路的操作波形圖。 第5-9圖可為第3圖的實施例之顯示控制電路的操作說明圖。 第10圖係第3至9圖之實施例的量測結果圖。 第11圖係本發明實施例的顯示控制電路之操作步驟流程圖。 第12圖係本發明另一實施例的顯示控制電路的示意圖。 第13圖係第12圖實施例之顯示控制電路的操作波形圖。 第14-18圖係第12圖的實施例之之顯示控制電路的操作說明圖。 第19圖係第11至17圖之實施例的量測結果圖。 第20圖係第12至18圖所示的顯示控制電路之操作方法流程圖。Figure 1 is a schematic diagram of a display control circuit in accordance with an embodiment of the present invention. Figure 2 is a schematic diagram of a display control circuit in accordance with another embodiment of the present invention. Figure 3 is a schematic diagram of a display control circuit in accordance with an embodiment of the present invention. Fig. 4 is a waveform diagram showing the operation of the display control circuit of the embodiment of Fig. 3. Figures 5-9 may be operational illustrations of the display control circuit of the embodiment of Figure 3. Fig. 10 is a graph showing the measurement results of the examples of Figs. 3 to 9. Figure 11 is a flow chart showing the operational steps of the display control circuit of the embodiment of the present invention. Figure 12 is a schematic diagram of a display control circuit in accordance with another embodiment of the present invention. Fig. 13 is an operation waveform diagram of the display control circuit of the embodiment of Fig. 12. Fig. 14-18 is an operation explanatory diagram of the display control circuit of the embodiment of Fig. 12. Fig. 19 is a graph showing the measurement results of the examples of Figs. 11 to 17. Figure 20 is a flow chart showing the operation of the display control circuit shown in Figures 12 to 18.

100‧‧‧顯示控制電路 100‧‧‧Display control circuit

110‧‧‧液晶電容 110‧‧‧Liquid Crystal Capacitor

120‧‧‧充電單元 120‧‧‧Charging unit

130‧‧‧寫入單元 130‧‧‧Write unit

140‧‧‧維持單元 140‧‧‧Maintenance unit

150‧‧‧第一電容 150‧‧‧first capacitor

160‧‧‧第二電容 160‧‧‧second capacitor

Vd‧‧‧資料電壓 Vd‧‧‧ data voltage

VCOM‧‧‧共電壓端 V COM ‧‧‧Common voltage terminal

VDD‧‧‧操作電壓 V DD ‧‧‧ operating voltage

Claims (9)

一種顯示控制電路,包含:一液晶電容,包含一第一端,及一第二端,耦接於一共電壓端,用以根據一資料電壓顯示;一充電單元,包含一第一端,一控制端,及一第二端,耦接於該液晶電容之該第一端;一寫入單元,包含一第一端,用以接收該資料電壓,一第二端,及一控制端;一維持單元,包含一第一端,耦接於該寫入單元之該第二端,一第二端,耦接於該液晶電容之該第一端,及一控制端;一第一電容,包含一第一端,耦接於該充電單元之該控制端,及一第二端,耦接於該寫入單元之該第二端;以及一第二電容,該第二電容包含一第一端,耦接於該第一電容之該第二端,及一第二端耦接於該共電壓端。 A display control circuit comprising: a liquid crystal capacitor, comprising a first end, and a second end coupled to a common voltage terminal for displaying according to a data voltage; a charging unit comprising a first end, a control And the second end is coupled to the first end of the liquid crystal capacitor; the writing unit includes a first end for receiving the data voltage, a second end, and a control end; The unit includes a first end coupled to the second end of the write unit, a second end coupled to the first end of the liquid crystal capacitor, and a control end; a first capacitor comprising The first end is coupled to the control end of the charging unit, and the second end is coupled to the second end of the writing unit; and a second capacitor, the second capacitor includes a first end, The second end of the first capacitor is coupled to the second end, and the second end is coupled to the common voltage terminal. 如請求項1所述的顯示控制電路,另包含一維持電容,該維持電容包含一第一端,耦接於該液晶電容之該第一端,及一第二端,耦接於該共電壓端。 The display control circuit of claim 1, further comprising a sustaining capacitor, the sustaining capacitor comprising a first end coupled to the first end of the liquid crystal capacitor, and a second end coupled to the common voltage end. 如請求項1或2所述的顯示控制電路,其中:該充電單元包含一第一開關,該第一開關具有一第一端,用以接收一操作電壓、一第二端,耦接於該液晶電容之該第一端、以及一控制端;該寫入單元包含一第二開關,該第二開關具有一第一端,用以接收該資料電壓、以及一第二端;該維持單元包含一第三開關,該第三開關具有一第一端,耦接於該第二開關 之該第二端、及一第二端耦接於該第一開關之該第二端、及一控制端;以及該顯示控制電路另包含一第四開關,該第四開關具有一第一端,用以接收一參考電位、一控制端,耦接於該第三開關之該控制端、以及一第二端,耦接於該第一開關之該控制端。 The display control circuit of claim 1 or 2, wherein the charging unit comprises a first switch, the first switch has a first end for receiving an operating voltage, and a second end coupled to the a first end of the liquid crystal capacitor and a control end; the write unit includes a second switch, the second switch has a first end for receiving the data voltage, and a second end; the maintenance unit includes a third switch having a first end coupled to the second switch The second end and the second end are coupled to the second end of the first switch and a control end; and the display control circuit further includes a fourth switch, the fourth switch has a first end The control terminal, the control terminal coupled to the third switch, and the second terminal are coupled to the control terminal of the first switch. 如請求項3所述的顯示控制電路,其中:該第二開關係用以於一重置階段、一補償階段、一維持階段及一顯示階段被關閉,及於一寫入階段被開啟;該第三開關係用於該重置階段及該補償階段被開啟,及於該寫入階段、該維持階段及該顯示階段被關閉;及該第四開關係用以於該重置階段及該補償階段被開啟,及於該寫入階段、該維持階段及該顯示階段被關閉。 The display control circuit of claim 3, wherein the second open relationship is used for a reset phase, a compensation phase, a sustain phase, and a display phase to be turned off, and is turned on in a write phase; The third open relationship is used for the reset phase and the compensation phase is turned on, and is closed during the write phase, the maintenance phase and the display phase; and the fourth open relationship is used for the reset phase and the compensation The phase is turned on and is turned off during the write phase, the sustain phase, and the display phase. 如請求項1或2所述的顯示控制電路,其中:該充電單元包含:一第一開關,包含一第一端、一第二端及一控制端,該第一開關的第二端係用以作為該充電單元之該第二端,該第一開關的控制端係該充電單元之該控制端;及一第二開關,包含一第一端、一第二端及一控制端,該第二開關之該第一端係用以作為該充電單元之該第一端,該第二開關之該第二端耦接於該第一開關之該第一端;該寫入單元包含一第五開關,該第五開關包含一第一端及一第二端,該第五開關之該第一端用以接收該資料電壓,該第五開關之該第二端耦接於該 第一電容之該第二端;該維持單元包含一第四開關;及該顯示控制電路另包含一第三開關,該第三開關包含一第一端、一控制端及一第二端,該第三開關之該第一端耦接於該第一電晶體之該第一端,該第三開關之該控制端耦接於該該維持單元之該控制端,該第三開關之該第二端耦接於該第一電容之該第一端。 The display control circuit of claim 1 or 2, wherein the charging unit comprises: a first switch comprising a first end, a second end and a control end, wherein the second end of the first switch is used The second end of the charging unit is the control end of the charging unit; and the second switch includes a first end, a second end, and a control end. The first end of the second switch is used as the first end of the charging unit, the second end of the second switch is coupled to the first end of the first switch; the writing unit includes a fifth end a switch, the fifth switch includes a first end and a second end, the first end of the fifth switch is configured to receive the data voltage, and the second end of the fifth switch is coupled to the The second terminal of the first capacitor; the display unit further includes a third switch, the third switch includes a first end, a control end and a second end, The first end of the third switch is coupled to the first end of the first transistor, the control end of the third switch is coupled to the control end of the third unit, and the second end of the third switch The end is coupled to the first end of the first capacitor. 如請求項5所述的顯示控制電路,其中:該第二開關係用以於一重置階段、一補償階段、一寫入階段及一維持階段被開啟,及於一顯示階段被關閉;該第三開關係用以於該重置階段及該補償階段被開啟,及於該寫入階段、該維持階段及該顯示階段被關閉;該第四開關係用以於該重置階段及該補償階段被開啟,及於該寫入階段、該維持階段及該顯示階段被關閉;及該第五開關係用以於該重置階段及該寫入階段被開啟,及於該補償階段、該維持階段及該顯示階段被關閉。 The display control circuit of claim 5, wherein the second open relationship is used for a reset phase, a compensation phase, a write phase, and a sustain phase, and is turned off during a display phase; The third open relationship is opened during the reset phase and the compensation phase, and is closed during the write phase, the maintenance phase and the display phase; the fourth open relationship is used for the reset phase and the compensation The phase is opened, and the write phase, the maintenance phase and the display phase are closed; and the fifth open relationship is used for the reset phase and the write phase to be turned on, and during the compensation phase, the maintenance The phase and the display phase are closed. 如請求項1所述的顯示控制電路,其中該液晶電容包含一液晶顯示介質。 The display control circuit of claim 1, wherein the liquid crystal capacitor comprises a liquid crystal display medium. 一種顯示控制電路之操作方法,該顯示控制電路包含一液晶電容、一充電單元、一寫入單元、一維持單元、一開關及一第一電容,該充電單元之一第一端用以接收一操作電壓,該液晶電容之一第一端耦接於該充電單元之一第二端,該液晶電容之一第二端耦接於一共電壓端,該開關具有一第一 端及一第二端,該充電單元之一控制端耦接於該開關之該第二端,該第一電容之一第一端耦接於該充電單元之該控制端,該第一電容之一第二端耦接於該寫入單元之一第二端,該寫入單元之一第一端用以接收一資料電壓,該操作方法包含:於一重置階段,維持該寫入單元的關閉狀態,開啟該開關及該維持單元,調整該開關之該第一端之準位以開啟該充電單元,及調整該操作電壓以重置該液晶電容之該第一端之準位;於該重置階段之後的一補償階段,調整該操作電壓以透過該充電單元對該液晶電容之該第一端充電,使該液晶電容之該第一端被充電到一預定準位;於該補償階段之後的一寫入階段,關閉該維持單元及該開關,及開啟該寫入單元,以使該第一電容之該第一端被抬升至該資料電壓及一臨界電壓之和;於該寫入階段之後的一維持階段,關閉該寫入單元,以使該液晶電容之該第一端的準位實質上對應於該資料電壓;以及於該維持階段之後的一顯示階段,調整該開關之該第一端之準位,以關閉該充電單元。 An operation method of a display control circuit, the display control circuit includes a liquid crystal capacitor, a charging unit, a writing unit, a sustaining unit, a switch and a first capacitor, and the first end of the charging unit is configured to receive a The operating voltage, the first end of the liquid crystal capacitor is coupled to the second end of the charging unit, and the second end of the liquid crystal capacitor is coupled to a common voltage end, the switch has a first And a second end, the control end of the charging unit is coupled to the second end of the switch, and the first end of the first capacitor is coupled to the control end of the charging unit, the first capacitor A second end is coupled to the second end of the write unit, and the first end of the write unit is configured to receive a data voltage, the method includes: maintaining the write unit in a reset phase Turning off the switch and the maintaining unit, adjusting the level of the first end of the switch to turn on the charging unit, and adjusting the operating voltage to reset the level of the first end of the liquid crystal capacitor; a compensation phase after the reset phase, adjusting the operating voltage to charge the first end of the liquid crystal capacitor through the charging unit, so that the first end of the liquid crystal capacitor is charged to a predetermined level; a subsequent writing phase, turning off the sustaining unit and the switch, and turning on the writing unit, so that the first end of the first capacitor is raised to a sum of the data voltage and a threshold voltage; Close the maintenance phase after the phase And entering the unit such that the level of the first end of the liquid crystal capacitor substantially corresponds to the data voltage; and in a display stage after the maintaining phase, adjusting the level of the first end of the switch to close the Charging unit. 一種顯示控制電路之操作方法,該顯示控制電路包含一充電單元,一寫入單元,一維持單元,一第一電容,一第三開關及一液晶電容,該充電單元包含一第一開關及一第二開關,該第二開關之一第一端用以接收一操作電壓,該第二開關之一第二端耦接於該第一開關之一第一端及該第三開關之一第一端,該第一開關之一控制端耦接於該第三開關之一第二端及該第一電容之一第一端,該第一開關之一第二端耦接於該液晶電容之一第一端及該維持單元之一第二端,該液晶電容之一第二端耦接於一共電壓端,該維持單元之 一第一端耦接於該第一電容之一第二端、及該寫入單元之一第二端,該寫入單元之一第一端用以接收一資料電壓,該操作方法包含:於一重置階段,開啟該第二、第三開關、該寫入單元及該維持單元,以將該第一電容之該第二端及該第一開關之該第二端重置到一預定準位,以使該第一開關之該控制端及該第二端的準位差大於一門檻值,進而開啟該第一開關;於該重置階段之後的一補償階段,關閉該寫入單元,以將該第一電容之該第一端充電到一第一電位,及將該第一電容之該第二端被充電到該第一電位及該門檻值之差值;於該補償階段之後的一寫入階段,關閉該第三開關及該維持單元,及開啟該寫入單元,以使該資料電壓寫入該第一電容之該第二端,及將該第一電容之該第一端的準位抬升到該資料電壓及該門檻值之和;於該寫入階段之後的一維持階段,關閉該寫入單元,以使該第一開關之該第二端的準位對應於該資料電壓;以及於該維持階段之後的一顯示階段,關閉該第二開關。 A display control circuit includes a charging unit, a writing unit, a maintaining unit, a first capacitor, a third switch and a liquid crystal capacitor, the charging unit including a first switch and a a second switch, the first end of the second switch is configured to receive an operating voltage, and the second end of the second switch is coupled to the first end of the first switch and the first end of the third switch The first end of the first switch is coupled to the second end of the third switch and the first end of the first capacitor, and the second end of the first switch is coupled to one of the liquid crystal capacitors a first end and a second end of the sustaining unit, wherein the second end of the liquid crystal capacitor is coupled to a common voltage terminal, and the maintaining unit a first end is coupled to the second end of the first capacitor, and the second end of the writing unit, the first end of the writing unit is configured to receive a data voltage, and the operation method includes: In a reset phase, the second and third switches, the writing unit and the maintaining unit are turned on to reset the second end of the first capacitor and the second end of the first switch to a predetermined level a bit such that the level difference between the control terminal and the second terminal of the first switch is greater than a threshold value, thereby turning on the first switch; in a compensation phase after the reset phase, the writing unit is turned off to Charging the first end of the first capacitor to a first potential, and charging the second end of the first capacitor to a difference between the first potential and the threshold; one after the compensation phase In the writing phase, the third switch and the sustaining unit are turned off, and the writing unit is turned on to write the data voltage to the second end of the first capacitor, and the first end of the first capacitor The level is raised to the sum of the data voltage and the threshold; a maintenance after the writing phase Section, close the writing unit, so that the level of the second terminal of the first switch of the voltage corresponding to the data; and a display phase to the maintenance phase after closing the second switch.
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