TWI578318B - 3d nand memory device and operation thereof - Google Patents

Description

Three-dimensional anti-gate memory element and its operation method

The present invention relates to a high-density memory component, and more particularly to a memory component in which a plurality of planes of memory cells are arranged to form a three-dimensional component.

Since the critical dimension of the components in the integrated circuit is reduced towards the limit of the memory cell technology, the designer has developed a technology for stacking several layers of memory cell planes to achieve greater storage capacity and achieve lower cost per unit bit. For example, the technology of thin film transistors can be applied to charge trapping memory technologies, such as the "Multilayer Stackable Thin Film Transistor and Gate Flash Memory" published by the IEEE Journal in December 2006 (Lai , et al., "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory", IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006), and the IEEE Journal Institute in December 2006 Published "Three-dimensional stacking and gate flash memory using a stacked single crystal germanium layer on the inner dielectric layer and a TANOS (Si-Oxide-SiN-Al2O3-TaN) structure over 30 nm node" (Jung et al., " Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node", IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006).

Furthermore, the cross-point array technique is also applied to anti-fuse memory, such as the "three-dimensional array of diodes / anti-melting" published by the IEEE Journal in November 2003. "512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells" IEEE J. of Solid-State Circuits, vol .38, no. 11, November 2003), as described by Johnson's published design, the proposed multi-layer word line and bit line have memory elements at the interlaced positions. The memory element includes a p+ type polysilicon anode connected to a word line, and an n-type polysilicon cathode connected to a bit line, and the anode and cathode are separated by an antifuse material.

In the process described by Lai, et al., Jung, et al. and Johnson et al, each memory cell layer has several key yellow light steps. Thus the total number of critical yellow light steps required to fabricate a 3D component is then multiplied by the total number of layers of the memory cell layer. Thus, while the application of 3D arrays can have the benefit of high density, higher manufacturing costs limit the use of this technology.

Another structure provides a technique for vertical reverse gate memory in a charge trapping memory. It is described in June 2007, "Using BiCS technology with stamping and plugging process to make ultra-high-density flash memory" ( Tanaka et al., "Bit Cost Scalable (BiCS) Technology with Punch and Plug Process for Ultra High Density Flash Memory," 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007, pages: 14-15). The structure described in Tanaka et al. includes a multi-gate field effect transistor having a vertical channel that can operate as a NAND gate, using a SONOS charge trapping technique to generate a storage location. Each gate/vertical channel interface. The memory structure is a vertical channel formed by a semiconductor material and arranged as a multi-gate memory cell having a lower-position selective gate adjacent to the substrate and a higher-position selective gate above. A plurality of horizontal control gates are formed by staggering the planar electrode layer and the pillars. The planar electrode layer used to form the control gate does not require a critical yellow light process to be fabricated, thereby reducing manufacturing costs. However, many critical yellow light processes are still required for each vertical memory cell. Moreover, the number of control gates that can be stacked in this way is limited, depending on various factors such as the conductivity of the vertical channel, the stylization and erasing procedures used, and others.

In another configuration, a technique for vertically translating the gate memory to a charge trapping memory is provided, which is described in 2009. "Multilayer with 16 stacked tubular BiCS flash memory and ultra high density storage elements. Memory cell operation" (Katsumata, et al., "Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices," 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009) (attached with the application). The structure described in Katsumata et al. includes a gate-all-around memory cell structure such as BiCS, but it is a P-BiCS having a U-shaped NAND string with a back A back gate reduces the parasitic capacitance at the bottom. Selecting the gate with a more asymmetric source and drain structure reduces the off-current.

While the 3D stacked memory structure can significantly increase memory density, it also introduces significant process challenges, including, for example, the need to etch very many layers to form deep vias, and fill in conductive materials. And a multilayer dielectric layer in the deep perforations to form a cylinder. Such stamping and plugging processes ("punch and plug" processes) will result in a uniform shape from top to bottom. Columns of a shape or diameter become difficult. Furthermore, the thickness of the dielectric charge trapping structure will vary with the shape of the cylinder. Changes in shape and dielectric thickness enhance the tail distribution of threshold voltages, resulting in poor switching conditions and poor memory cell reliability. Furthermore, when the channel voltage is applied to the non-selected word line, the memory cell located at a narrower diameter and width has a problem that the electric field strength becomes stronger and the channel voltage is disturbed on the column having a non-uniform diameter.

Therefore, the related industry has no desire to propose a three-dimensional memory element and an operation method, which can reduce the negative impact caused by the uneven column of the element, and can still change the density of the element after the manufacturing process.

A memory element comprising a plurality of horizontal structures on a substrate, the horizontal structure comprising a conductive material, or a semiconductor material or both; a plurality of vertical structures arranged orthogonally to the horizontal structure, the vertical structure comprising a conductive material, or a semiconductor material or two The plurality of memory cells are located at the intersection of the vertical structure and the horizontal structure; an indicator memory indicates that any horizontal structure in the horizontal structure is affected during operation because the defect is detected. The reliability of the memory cell to the indicator layer is to be excluded; and the control circuit is coupled to the horizontal structure. Where the memory component is read or programmed, a second control voltage is applied to the unselected level in response to the control circuit instructing the memory to apply a first control voltage to a selected one of the horizontal structures. The structure, and a horizontal structure in which one of the third control voltages is applied to the horizontal structure is excluded.

The above description is presented as a basic understanding of some aspects of the disclosure. This description is not intended to define key or critical elements of the disclosure, or to limit the scope of the disclosure. The above description is only intended to present the disclosure in a simplified form. Concepts and a preface to the implementations described in more detail below. The above and other aspects of the present disclosure are described in detail in the following examples, including the claims, the description and the drawings.

10‧‧‧Common source line

11, 611‧‧‧ active layer

12, 612‧‧‧ tandem selection line

13‧‧‧ Grounding selection line

15‧‧‧Cylinder

210‧‧‧ core

211‧‧‧ hole seam

212‧‧‧First layer of antimony oxide

213‧‧‧ layer of tantalum nitride

214‧‧‧Second layer of cerium oxide

215‧‧‧Insulation structure

20‧‧‧ bit line

22‧‧‧Contact

26A, 26B‧‧‧ active layer connection area

28A, 28B‧‧‧ Ground selection line connection area

111, 112, 113, 168‧‧‧ blocks

156‧‧‧ address decoder

158‧‧ layer decoder

160‧‧‧Three-dimensional memory array

161‧‧‧ column decoder

162‧‧‧Sequence selection line

163‧‧ ‧ buffer

164‧‧‧ bit line

165‧‧‧ bus bar

166‧‧‧ row decoder

167‧‧‧ data output line

169‧‧‧ state machine

171‧‧‧ data input line

174‧‧‧Other circuits

175‧‧‧Integrated circuit

191‧‧‧Configuration register

192‧‧‧Indicating memory

604‧‧‧ memory cells

606‧‧‧Serial selection gate

608‧‧‧Ground selection gate

615‧‧‧Listing

T1, T2, T3‧‧‧

V'pass, Vpass‧‧‧ channel voltage

Figure 1 is a simplified block diagram of one of the integrated circuits including an embodiment.

Fig. 2 is a horizontal sectional view showing one of the memory cells in the row direction of the embodiment.

Figure 3 is a perspective view of a three-dimensional vertical channel memory component.

4A and 4B are vertical cross-sectional views of a portion of the structure of Fig. 3 under process variation.

Figure 5 is a circuit diagram including a block of a memory of the present disclosure.

Figure 6 is a timing diagram of one of the stylized operations in accordance with an embodiment.

The embodiments set forth below enable the person skilled in the art to make and use the present disclosure, and to provide a specific application and the content of the requirements as an example. Various modifications and variations of the present invention, which are obvious to those skilled in the art, and the general rules defined in the disclosure may be applied to other embodiments and applications without departing from the spirit and scope of the invention. in. Therefore, the disclosure is not to be limited to the details shown in the embodiments, but the broad scope of the principles and features of the disclosure.

1 is a simplified wafer block diagram of an integrated circuit 175 including an embodiment. As described below, the integrated circuit 175 includes a 3D memory array 160 and an indicator memory 192 indicating that the memory 192 can indicate a layer of the three-dimensional memory array during component operation. Waiting Excluded.

The address decoder 156 includes a row of row decoders 161, a column decoder 166, and a level decoder 158. The column decoder 161 is coupled to a plurality of string select lines (SSLs) 162, and the string select lines 162 are arranged along the column direction of the memory array 160. The row decoder 166 is coupled to the plurality of bit lines 164 to read and program the data of the memory cells in the memory array 160, and the bit lines 164 are arranged along the row direction of the memory array 160. Page buffers 163 are coupled to data-in circuits and data-out circuits by lines 171 and 167, respectively, and are coupled to the memory array. A plurality of bit lines 164 arranged in the row direction of 160 are used to read data from the memory array 160 and write data to the memory array 160. The address decoder 156 provides the address to the page buffer 163 via bus lines 165. In other embodiments, the page buffer can be integrated into row decoder 166. The layer decoder 158 is coupled to a plurality of layers of the memory array 160 via a word line connectors 159. An indicator memory 192 is coupled to the address decoder 156 and/or a controller and stores information to indicate an excluded level (s). In other embodiments, the indication memory 192 can be included in the address decoder 156. The indication memory 192 can be in the form of a mask, which can be masked in the 3D block to avoid storing data, and the indication memory 192 is indicated by the bias design of the masked layers. Excluded layer.

Other circuitry 174 may be included on the wafer to support the task function of utilizing the memory. A controller, in this embodiment, is a state machine 169, which provides a signal to control the power supply of the block 168. A bias configuration application that generates or supplies a voltage, such as controlling the voltages of read, erase, program, erase verify, and stylized verify, to perform the various operations described above. A configuration register 191 is coupled to state machine 169 to set the voltage levels applied to the stylized, erase, and read operations, as well as to set the voltage level applied to the excluded layers. A special-purpose logic circuitry can also be used as the controller as is known to those skilled in the art. In other embodiments, the controller includes a general-purpose processor that can be implemented on the same integrated circuit that executes a computer program to control component operation. In other embodiments, the controller can be implemented using a combination of a special purpose logic circuit and a general purpose processor. The controller may also incorporate other circuitry 174 functions and state machine 169 to vary the voltage supplied by the supply voltage of block 168.

Figure 2 is a horizontal cross-sectional view of one of the memory cells in one of the columns of the embodiment. The structure of the memory cell includes a pillar 15 having a central core 210 formed of a semiconductor material, and the core 210 extending vertically through the active layer and the insulating structure 215 alternately forming a stack, such as a word line layer A stack formed alternately with the insulating layer. The core 210 can be formed through a deposition technique to form a seam 211 through the middle. A dielectric charge trapping structure includes a first layer 212 formed of yttrium oxide, a layer 213 formed of tantalum nitride, and a second layer 214 formed by yttrium oxide (ie, ONO), or other multilayer layers. An electrical charge trapping structure surrounds the core 210. The cascaded memory cell is located at the intersection of the column and each active layer. Due to variations in the diameter of the columns in the various layers of the structure, for example, memory cells in certain layers may have performance characteristics that are outside the acceptable range, making the memory cells in the layer unreliable or even unusable in use. In an embodiment, such a layer can be programmed by an indicator memory. To indicate and then exclude it from the data storage operation.

Figure 3 is a perspective view of a three-dimensional vertical channel memory component. The memory element includes a plurality of active levels 11 such as a word line layer and are respectively parallel to the substrate, and a plurality of columns 15 extend perpendicular to the substrate, and each of the columns 15 includes a plurality of serially connected memory cells (series -connected memory cells) is located at the intersection of the cylinder 15 and the active layer 11. A plurality of string select lines (SSLs) 12 extend parallel to the substrate and above the active layer 11, and the series of select lines intersect the column 15 to form a column. Each of the intersections of a cylinder 15 and a series of select lines 12 defines a string select gate (SSG). The structure of the memory component also includes ground select lines (GSLs) 13 (sometimes because it is located at the lower end of a cylinder 15 , also referred to as a low-end selection line), extending parallel to the substrate and located at the active layer 11 Below. A junction of a cylinder 15 and a ground selection line 13 defines a ground select gate (GSG) of the pillar 15 (sometimes referred to as a low-side selection gate of the pillar 15 ( Lower select gate (LSG) of the pillar. A common source line (CSL) 10 is formed in a layer parallel to the substrate and below the ground selection line (GSLs). The structure of the memory element also includes a plurality of strips. The bit line 20 is formed on a layer parallel to the substrate and above the series select lines (SSLs). Each bit line 20 is stacked above the column 15 of each corresponding row, and each column 15 is in a bit Below one of the lines 20. The construction of the column 15 may be as shown and described in Figure 2.

In Figure 3, the memory component includes a stepped step contact structure to the active layer. Contactes 22 are formed by deep etching into the structure to connect active layer connection regions (active level Connecting regions 26A, 26B are connected to metal interconnects 24 above. Each active layer connection region 26A or 26B defines one of the memory cells. GSL connecting regions 28A and 28B are also formed. Therefore, in order to read data from a particular block of memory, control circuitry triggers an active layer connection region 26A or 26B to select one of the memory cells and a particular layer of the stack, and is more triggered. A series of select lines 12 is selected to select a particular row. A ground selection gate is also triggered. Then, the data of one column of memory cells is read in parallel to the one-page buffer (not shown) through the bit line 20 (the "Activate" mentioned in the text refers to the application of a specific bias to generate the connection memory. The effect of the cell or switch, the bias value may be high or low, depending on the design of the memory). Depending on the specification and design of the product, the page buffer may control two or more columns of data, so a full page read operation may include successful triggering of two or more string select lines 12.

Using a stamped via and plug process, the pillar system extends vertically between all of the semiconductor layers, including a plurality of active layers 11, a plurality of string select lines 12, and a plurality of ground select lines 13. It is important to form a cylinder having a uniform width from top to bottom. The higher the aspect ratio of the cylinder, the worse the uniformity of the column width. A change in the width of the cylinder causes a variation in threshold voltages. The bottom layer of the semiconductor layer is the ground selection line, and the intersection of a pillar and the ground selection line is a ground selection gate, which can be used as a switch to select the corresponding cylinder. Above the ground selection line is the active layer, where the intersection of a cylinder and the active layer is a memory cell. The ground selection line at the lowest level may have the smallest column width, but since all the ground selection gates are in the same layer, the distribution of the threshold voltage of the ground selection gate is not seriously affected by the variation of the column width. But on the contrary, the memory cells are in different layers. Its threshold voltage is affected by changes in the width, diameter or other characteristics of the cylinder.

As the cylinder changes, the distribution of the threshold voltage may become wider to produce tail bits. In general, the memory cells in the array may have a distribution of threshold voltages in the form of a Gaussian distribution or a normal distribution due to process variation. Memory cells that do not follow the normal distribution will cause stylization and erase the end of the critical voltage distribution. These bits are called ending bits and their presence affects the reliability of the memory.

4A and 4B are vertical cross-sectional views of a portion of the structure of Fig. 3 under process variation. In Fig. 4A, the width of the cylinder 15 is drastically lowered at the active layer 11 corresponding to the lower layer, particularly at the block 111. Due to the narrower column width at block 111, a finishing bit with a higher threshold voltage may be generated. In order to prevent the end bit from affecting the reliability of the memory, the active layer 11 at the block 111 is excluded. In the memory component, the width of the intersection of the pillar and the excluded layer in the active layer may be smaller than the width of the cylinder intersecting the selected and non-selected active layers, in terms of operational characteristics. There may be problems with the variability that causes the finishing bit.

In another embodiment, as shown in Fig. 4B, the width of the cylinder may gradually decrease from top to bottom. Therefore, the different widths of the column corresponding to the upper active layer and the lower active layer (please refer to blocks 112 and 113) will widen the distribution of the threshold voltage, and produce a finishing bit with a higher threshold voltage. Similarly, in order to avoid the occurrence of a tailing bit, which occurs at a narrower or wider column width due to a broad threshold voltage distribution, the active layer 11 at blocks 112 and 113 is indicated to be excluded.

Figure 5 is a circuit diagram including a block of a memory of the present disclosure. As shown, the block of memory includes a tandem memory cell 604 having a number _{N IX of} strings 615. Each string 615 has a number of memory cells 604 of N _M . Each memory cell 604 has a structure as shown in FIG. 1 and electrically includes a source, a drain, and a control gate. Since the source and drain of many transistors are electrically interchangeable, the two terminals are sometimes collectively referred to as "current path terminals."

Each of the strings 615 also includes a string select gate 606 and a ground select gate 608 connected in series to the memory cells 604 on opposite sides of the string. The series select gate 606 is selected as a series, and the ground select gate 608 prevents the memory cell current from passing through the series during a stylized operation. Furthermore, each of the serial selection gate 606 and the ground selection gate 608 serves as a control gate electrode of the series current path termination.

The block of memory elements includes N _WL separate active layers 611, each active layer 611 corresponding to a memory cell 604 in a series 615. In all of the series 615 of blocks, each active layer 611 acts as a control gate electrode in the corresponding memory cell 604. The active layer is coupled to a controller responsive to the indicator memory, indicating that the memory can indicate the active layer to be excluded. The memory component of the embodiment includes an indicator memory that can be programmed to indicate which active layers are to be excluded. The indicator memory can identify the same excluded layer in all blocks of the memory element or identify different excluded layers in each block of the memory element.

The block of memory elements includes N _SSL strip separated string select lines 612 active layer 611 coupled to a string of select decoders (SSL decoders), and tandem select lines 612 for corresponding arrays Selecting the gate 606 acts as a control gate electrode.

The block of the memory component includes _NBL strips of bit lines, and the bit lines are respectively coupled to one of the current path terminals of the corresponding serial select gate 606.

The block of the memory component includes a ground select line (GSL). The ground selection line is the control gate electrode of all ground selection gates 608 in the block.

In another embodiment, the block of memory elements can include more than one ground select line, and the ground select gate 608 of the memory element is differentiated into a distinguishable non-zero subset of numbers N _GSL >1 (distinct non -null subsets) ground selection gate 608. For example, when N _GSL = 2, each subset of ground selection gates 608 includes half of the ground selection gates 608 in series 615. In a corresponding subset of one of the ground selection gates 608, the N _GSL strip ground selection lines are the control gate electrodes of all ground selection gates, respectively.

In Fig. 5, one page buffer is composed of N _BL × N _SSL bits, and one block is composed of N _BL × N _SSL × N _WL bits. When the indication memory indicates that the W _{LM is} excluded, the block of the memory component recognizes one of the active layers W _LM to be excluded, and the number of bits of the block is reduced to N _BL ×N _SSL ×(N _WL-1 ). When the indication memory indicates that W _LM and W _{LM-1 are} excluded, the memory element block identifies the two active layers W _LM and W _LM-1 to be excluded, and the number of bits in the block is reduced to N _BL ×N. _SSL × (N _WL-2 ). The density of the blocks can be adjusted by defining the number of active layers to be excluded. The active layer excluded does not necessarily have to be the active layer located in the lower layer, and may be the active layer at any position. When a memory component defines all the blocks with N _EX active layers to be excluded, the density of the memory components is N _BL × N _SSL × (N _WL - N _EX ) × N _BLOCK when N _EX 2. The active layer to be excluded can be set in series or randomly set.

In yet another embodiment, the indicator memory can indicate that the active layer of 1/2, 1/4 or 1/8 is intended to be excluded.

The indicator memory includes an electrically programmable fuse (eFuse) memory, a flash memory, a read only memory (ROM), a random access memory (RAM), or the like.

Control circuitry is coupled to the active layer. In the operation of reading or staging the semiconductor device, the control circuit applies a first control voltage to the active layer selected by one of the active layers in response to the indication memory, applying a second control voltage to the unselected The active layer, and an active layer that is applied to one of the active layers by applying a third control voltage.

The first, second and third control voltages are all different. The first control voltage is a stylized or read voltage applied to the selected active layer. The second control voltage is applied to the unselected active layer by a turn-on voltage (Vpass). The third control voltage is applied to the excluded layer for another turn-on voltage (V'pass).

The third control voltage can be adjusted according to the duration or number of turns, depending on the information stored in the configuration register or the number of turns of the configuration register. For example, after operating a memory such as one year or 1K laps, the state machine can receive a signal from the configuration register and change the third control voltage.

The memory component includes a plurality of horizontal structures on a substrate, a plurality of vertical structures are orthogonal to the horizontal structure, and a plurality of memory cells are located at a cross-point of the vertical structure and the horizontal structure. An indicator memory indicating that any horizontal structures in the horizontal structures are to be excluded, and a control circuitry is coupled to the horizontal structure in which the memory elements are read or programmed ,ring Applying a first control voltage to a horizontal structure in which one of the horizontal structures is selected, applying a second control voltage to the unselected horizontal structure, and applying a third control voltage to the control circuit of the indication memory A horizontal structure that is excluded from one of the horizontal structures.

The indicator memory can also be used to erase the memory components.

In one example, for example, a 3D vertical channel structure, the plurality of horizontal structures include a conductive material, a semiconductor material, or both, and the horizontal structures may be active layers, such as word lines. The plurality of vertical structures include a conductive material, a semiconductor material, or both, and the vertical structures may be pillars.

In another example, such as a 3D vertical gate structure, the plurality of horizontal structures include a conductive material, a semiconductor material, or both, and the horizontal structures may be active layers, such as bit lines. The plurality of vertical structures include a conductive material, a semiconductor material, or both, and these vertical structures may be word lines.

Please refer to Figure 5 for a stylized operation. One of the target memory cells is labeled A, and the active layer to be excluded is WL _M . Prior to programming, the entire block is erased to lower the threshold voltage to a erase voltage threshold, which may be a voltage value below zero in the NAND memory device (NAND). During a stylized pulse applied to the selected memory cell A, the selected bit line BL ₂ receives a bias of about 0V, and the unselected bit lines BL ₁ and BL ₃ -BL _N receive To suppress the voltage of the bias voltage. Similarly, the selected tandem select line SSL ₂ receives a bias of about 3V, while the unselected tandem select lines SSL ₁ and SSL ₃ -SSL _P receive the voltage of the suppression bias. The selected active layer WL ₁ receives the stylized pulse, the unselected active layer WL ₂ -WL _M-1 receives the channel voltage (Vpass), and the active layer WL _M to be excluded receives the other and channel voltage Vpass Different channel voltages (V'pass), according to which the NAND string is turned on.

Since the channel voltage interference is proportional to the number of serial select lines SSL, the channel voltage disturbance problem is greater in a three-dimensional NAND device than in a two-dimensional NAND device. The channel voltage value should be higher than the threshold voltage but less than the voltage required for the memory cell to be programmed. Due to the change in the width of the cylinder, the threshold voltage of the memory cell in the active layer to be excluded may be higher than the threshold voltage of the memory cell in the unselected active layer, so that the channel voltage V'pass may be higher than the channel voltage Vpass. However, higher channel voltages will cause greater interference, while memory cells with narrower column widths will be more susceptible to channel voltage interference. If the interference is sufficient to change the threshold voltage of the interfered memory cell from a low threshold voltage to a high threshold voltage, erasing the memory cell located in the active layer to be removed to have a negative threshold voltage, resulting in a low channel voltage V'pass At the channel voltage Vpass.

The read operation is similar to the stylized operation in terms of channel voltage interference and determining the channel voltage (Vpass and V'pass) applied to the unselected active layer and the active layer to be excluded.

Figure 6 is a timing diagram of a stylized operation in which stylized operations are performed in three intervals.

At the beginning of phase T1, the control circuit applies a voltage (eg, 4.5V) sufficient to turn on unselected serial select line (SSLs) switches, and applies a low voltage (eg, 0V) to turn off the selected tandem select line. switch. The selected word line, and the unselected word line and ground select line (GSL), are maintained at approximately 0V. The control circuit applies about 3V to the selected and unselected bit lines. Since the memory cell is erased to have a negative threshold voltage before this stage, it is applied to the active to be excluded. The channel voltage (V'pass) of the layer is about 3V, which is sufficient to turn on the memory cells of the active layer to be excluded. At the end of phase T1, the unselected tandem select line and the selected bit line return to about 0V, while the voltage applied to the excluded word line maintains the channel voltage (V'pass) about 3V. In one embodiment, stage T1 can be maintained for about 5 microseconds (μs).

In stage T2, the control circuit applies approximately 4.5V to the string select line to turn on the selected tandem select line switch. The selected bit line, the selected and unselected word line, the ground select line (GSL), and the unselected tandem select line are maintained at approximately 0V. The unselected bit line is maintained at approximately 3V. This allows current to flow in the series coupled to the selected bit line, while blocking the flow of current coupled into the series of unselected bit lines. At the end of phase T2, the voltage applied to the selected string select line drops to approximately 3V. In one embodiment, stage T2 can be maintained for about 5 microseconds (μs).

At the beginning of phase T3, the voltage applied to the selected word line layer is boosted to a program potential of about 20V (stylized pulse). Its turn-on voltage is lower than the voltage required to program the memory cell A. In this example, the channel voltage (Vpass) applied to the unselected word line may be 9V, and the channel voltage (V'pass) applied to the excluded character may be 3V. During phase T3, memory cell A is taken. In one embodiment, stage T3 can be maintained for about 10 microseconds (μs).

As shown in FIG. 5, a three-dimensional element includes a plurality of active layers and a plurality of pillars extending vertically between the active layers, and a method of reading or programming a three-dimensional component includes: applying a first control voltage to the active layer One of the selected active layers, applying a second control voltage to one of the active layers that is not selected, and applying a third control voltage to the active layer in which one of the active layers is excluded, and The third control voltage is different from the second control voltage. In this method, the second control voltage turns on a memory cell at the intersection of the pillar and the unselected active layer, and the third control voltage turns on the memory cell at the intersection of the pillar and the excluded active layer. The method further includes stylizing an indicator memory indicating the excluded active layer. Wherein a third control voltage is applied in response to an indicator memory that can indicate the active layer being excluded. The indicator memory can also be used to erase 3D components.

The first, second and third control voltages are all different. The first control voltage is a stylized or read voltage applied to the selected active layer. The second control voltage is applied to all unselected active layers by a turn-on voltage (Vpass). The third control voltage is applied to the excluded active layer for another turn-on voltage (V'pass).

The embodiments described above are intended to be illustrative and illustrative, and are not intended to be Obviously, those skilled in the art can make many changes and refinements according to the disclosure. For example, in the above embodiments, a vertical channel charge storage memory cell is used, and a column having other morphological memory cells can also be applied to the present disclosure, although it is not necessary (and unnecessary) to achieve all of the above advantages. In particular, and without limitation, any and all such variations, suggestions, or background descriptions as set forth in the present application are attached to the embodiments disclosed herein. Furthermore, any and all of the above variations, suggestions, or associated references associated with any embodiment are also related to all other embodiments. The embodiments as described above are used to make a better description of the principles and practical applications of the present disclosure, and those skilled in the art to understand the various embodiments of the disclosure may be suitable for each application. Change and retouch. Therefore, the scope of the invention is defined by the scope of the appended claims.

156‧‧‧ address decoder

158‧‧ layer decoder

159‧‧‧Word line connector

160‧‧‧Three-dimensional memory array

161‧‧‧ column decoder

162‧‧‧Sequence selection line

163‧‧ ‧ buffer

164‧‧‧ bit line

165‧‧‧ bus bar

166‧‧‧ row decoder

167‧‧‧ data output line

168‧‧‧ Block

169‧‧‧ state machine

171‧‧‧ data input line

174‧‧‧Other circuits

175‧‧‧Integrated circuit

191‧‧‧Configuration register

192‧‧‧Indicating memory

Claims (20)

A memory component comprising: a plurality of horizontal structures on a substrate, the horizontal structures comprising a conductive material, or a semiconductor material or both; and a plurality of vertical structures orthogonal to the horizontal structures Arranging that the vertical structures comprise a conductive material, or a semiconductor material or both; a plurality of memory cells located at intersections of the vertical structures and the horizontal structures; an indicator memory Determining whether any of the horizontal structures are to be excluded; and control circuitry is coupled to the horizontal structures, wherein the memory is responsive to the indication when the memory component is read or programmed The control circuit applies a first control voltage to the horizontal structure in which one of the horizontal structures is selected, and applies a second control voltage to the horizontal structures that are not selected, wherein if any of the horizontal structures To be excluded, the control circuit applies a third control voltage to a horizontal structure in which one of the horizontal structures is excluded. The memory component of claim 1, wherein the first control voltage, the second control voltage, and the third control voltage are all different. The memory component of claim 1, wherein all of the horizontal structures that are not selected apply the second control voltage. The memory component of claim 1, wherein the first control voltage comprises a program voltage or a read voltage. The memory component of claim 1, wherein the vertical components The width of the intersection of the structure and the excluded horizontal structure is less than the width of the vertical structure intersecting the selected and unselected horizontal structures. The memory component of claim 1, wherein the horizontal structures comprise word lines. The memory component of claim 6, wherein the vertical structures comprise pillars. The memory component of claim 1, wherein the horizontal structures comprise bit lines. The memory component of claim 8, wherein the vertical structures comprise word lines. A semiconductor component comprising: a plurality of active levels; a plurality of pillars extending vertically between the active layers; a plurality of series-connected memory cells located in the pillars and the plurality of pillars a cross-point of the active layer; and control circuitry coupled to the active layers, wherein the control circuit applies a first control voltage to the active elements when reading or programming the semiconductor component One of the active layers is selected by the active layer, and a second control voltage is applied to the active layers that are not selected, wherein if any of the active layers are to be excluded, the control circuit further applies a third control The voltage is applied to the active layer in which one of the active layers is excluded. The semiconductor device of claim 10, wherein the semiconductor device further comprises an indicator memory indicating that any of the active layers is to be excluded. The semiconductor device of claim 10, wherein the first control voltage, the second control voltage, and the third control voltage are all different. The semiconductor component of claim 10, wherein the second control voltage is applied to all of the active layers that are not selected. The semiconductor device of claim 11, wherein the control circuit responsive to the indication memory applies the third control voltage to an active layer in which one of the active layers is excluded. The semiconductor device of claim 10, wherein the excluded active layer comprises an uppermost layer or a lowermost layer of the active layers. The semiconductor device of claim 10, wherein the width of the pillar of the active layer is less than the width of the pillar of the active layers selected or unselected. A method of reading or staging a three-dimensional component, the three-dimensional component comprising a plurality of active levels and a plurality of pillars extending vertically between the active layers, the method comprising: applying a first control voltage And selecting, by the active layer, one of the active layers; and applying a second control voltage to the plurality of active layers of the active layers that are not selected; wherein if any of the active layers are to be excluded And applying a third control voltage to the active layer in which one of the active layers is excluded, the third control voltage being different from the second control voltage; wherein the second control voltage is turned on in the pillars and Not selected The memory cells at the intersection of the active layers, the third control voltage turns on the memory cells located at the intersection of the pillars and the excluded active layer. The method of claim 17, wherein the second control voltage is applied to all of the active layers that are not selected. The method of claim 17, wherein the third control voltage is applied in response to an indicator memory indicating that the active layer is excluded. The method of claim 17, further comprising staging an indicator memory to indicate the active layer being excluded.