TWI566251B - Flash memory wafer probing method and machine - Google Patents

Description

Flash memory wafer test method and machine

The present invention relates to flash memory wafer testing techniques.

Flash memory is the currently common non-volatile memory. After flash memory wafer fabrication, wafer probing is required to screen out grains of poor yield.

This case discloses a flash memory wafer testing technique that accelerates the screening of bad grains.

A flash memory wafer test method implemented according to an embodiment of the present invention includes: performing a control signal line tolerance simulation on a plurality of flash memory dies on a flash memory wafer, which is fast Tolerance simulation of the word line, or bit line, or word line and bit line of the flash memory die; repeating the programming and erasing the flash memory grains by N times of the loop; After the above control signal line tolerance simulation is performed, and before the N loops are repeatedly programmed and the flash memory grains are erased, the flash memory grains are back-baked.

A flash memory wafer testing machine implemented according to an embodiment of the present invention includes: a probe module; and a microcomputer. The microcomputer operation The probe module performs a control signal line tolerance simulation on a plurality of flash memory chips on a flash memory wafer, and further operates the probe module to be repeatedly programmed in N loops and Erasing the flash memory grains. After the above-mentioned control signal line tolerance simulation is performed, and the N times of the loops are repeatedly programmed and the flash memory grains are erased, the flash memory grains are repaired by bake back. The above control signal line tolerance simulation simulates the tolerance of the word lines, or bit lines, or both word lines and bit lines of the flash memory dies.

The invention is described in detail below with reference to the accompanying drawings.

102‧‧‧Microcomputer

104‧‧‧UV module

106‧‧‧ Probe Module

108‧‧‧temperature regulator

110‧‧‧Flash Memory Wafer

S302...S320‧‧‧Steps

SOP1, SOP2‧‧‧ Weeded element screening first and second stylized mode

SOS‧‧‧ weak bit screen for the word line pressing mode

Control point voltage of V _BL , V _Bulk , V _S , V _WL ‧‧‧ flash memory unit

1 is a schematic diagram of a flash memory wafer testing machine according to an embodiment of the present invention; FIG. 2 is a schematic structural diagram of a flash memory unit in a flash memory die; FIG. 3 is a flow chart according to FIG. One embodiment of the present invention illustrates a method of testing a flash memory wafer; and FIG. 4 is a timing diagram illustrating a method of testing a flash memory wafer in accordance with an embodiment of the present invention.

The following description sets forth various embodiments of the invention. The following description sets forth the basic concepts of the invention and is not intended to limit the invention. The scope of the actual invention shall be defined in accordance with the scope of the patent application.

Figure 1 illustrates a flash memory according to an embodiment of the present invention The wafer testing machine includes a microcomputer 102, an ultraviolet module 104, a probe module 106, and a temperature adjuster 108 for testing a plurality of flashes on a flash memory wafer 110. Memory dies (divided by grid lines within wafer 110).

In addition to controlling the ultraviolet light module 104 to apply ultraviolet light to the flash memory wafer 110 that is completed, the microcomputer 102 provides a plurality of voltages to be applied by the probe module 106 to the flash memory chips. A variety of test points. In particular, during operation of the probe module 106 to perform tolerance detection on the flash memory wafer 110, the microcomputer 102 arranges control signal line tolerance simulation before a stylization-erasing loop. . The so-called control signal line tolerance simulation simulates the tolerance of the word lines or/and bit lines of the flash memory grains. Word line tolerance simulation can be used to brush out word line isolation; for example, the gate of the flash memory unit is poorly insulated from the gate, or the gate and source of the flash memory unit are insulated. Bad person. Bit line tolerance simulation can be used to brush out bit line isolation; for example, to solve the coupling problem of flash memory cells of the same bit line, or the coupling problem of flash memory cells of adjacent bit lines.

In addition, a one-time bake repair procedure was designed to simplify the two-stage tolerance test after the above control signal line tolerance simulation and before the stylization-erasing loop.

In addition, the ambient temperature of the control signal line tolerance simulation can be different from the stylized-erase loop. Microcomputer 102 includes controlling the temperature regulator 108 to provide an appropriate ambient temperature.

2 is a schematic diagram of a flash memory cell in a flash memory die, which is a NAND architecture, wherein the four voltage control points include: a gate (connecting a word line with a voltage label V _WL ); a drain (connecting a bit line with a voltage label V _BL ); a source (on which the voltage is labeled V _S ); and a substrate (on which the voltage is labeled V _Bulk ). For the tolerance detection, the microcomputer 102 includes operating the probe module 106 to apply the voltage control points to perform operations on the corresponding flash memory unit, including: first stylization; first erasing; pre-stylization; word lines Tolerance simulation; bit line tolerance simulation; soft stylization; strong erasing; looping stylization, looping erasing; weak bit sieving first stylization; weak bit sifting Line pressure; weak bit screen to remove the bit line pressure; and weak bit element screen to remove the second stylization.

In one embodiment, the operation of the above different operations of a flash memory unit is as follows: first stylized: V _WL = 7~10V; V _BL = 3~5V; first erase: V _WL -V _Bulk =- 15~-20V, lasting 10~50ms; pre-stylized: V _WL =7~10V; V _BL =3~5V; word line tolerance simulation: V _WL -V _Bulk =>-18~-25V, lasting 50 ~2000s; bit line tolerance simulation: 4~6 volts V _{BL of} 3000~5000 pulse patterns; soft stylization: control V _WL and V _BL to reset the flash memory unit; strong erase: V _WL - V _Bulk = -18~-25V lasts 10~50s; the loop is stylized: V _WL =8~10.5V and V _BL =3~5V strong stylization; loop is erased: V _WL -V _Bulk = -15~-20V performs a general erase of 1ms; the first stylization of weak bit screen removal: V _WL =7~10V; V _BL =3~5V; weak bit screens to remove the word line pressure: V _WL -V _Bulk = -15~-20V; the bit line of the weak bit screen is pressed; V _BL = 3~5V; and the second stylization of the weak bit screen: V _WL = 8~10.5V; V _BL =3~5V; among them, the control terminal that does not specifically indicate the voltage value is controlled at 0V.

The so-called "stylization" above makes the flash memory unit logically '1'. The above-mentioned "erase" is to erase the flash memory unit to logic '0'. The application voltage of each of the above modes may vary. In terms of "stylized" operation, based V _BL "tolerance-analog bit line" of the above "loop with a stylized" V _BL on the principle; e.g., 5% to 15% higher. V _BL "bit line tolerance simulation" of the general design of the pressure of time longer than the "loop with the stylized" V _BL of time pressure. To "erase" operation in terms of, based "simulated word line tolerance" of V _WL -V _Bulk deeper in principle "with erase loop" of V _WL -V _Bulk; e.g., a depth of 5% to 15 %. The V _WL -V _Bulk differential pressure of the "Word Line Tolerance Simulation" is generally supplied in a plurality of pulse patterns.

In particular, the operating temperature of the "control signal line tolerance simulation" including "word line tolerance simulation" or / and "bit line tolerance simulation" can be higher than "looping stylized" and "loop" Use "erase" to form a "stylized-erasing loop". For example, the "Control Signal Line Tolerance Simulation" can be designed to operate at an ambient temperature of 90 degrees Celsius, while the "Stylized-Erase Loop" can be designed to operate at an ambient temperature of 25 degrees Celsius.

In one embodiment, after the "control signal line tolerance simulation", a bake repair program is designed. For example, the flash memory wafer 110 is set at 150 degrees to 300 degrees Celsius for 20 to 60 hours. "Stylized - erase loop" is arranged after such "back to bake repair".

In addition, the above-mentioned "first stylization of weak position screening", "weak position of weak position screening", "pressure line of weak position screening", and "weak position screening" A second post-programming "weak bit screening procedure" can also be followed by a bake repair procedure - for example, setting the flash memory wafer 110 to 255 degrees Celsius for 24 hours.

Figure 3 is a flow chart illustrating an embodiment according to an embodiment of the present invention The flash memory wafer test method relates to the tolerance detection of the flash memory wafer 110.

In step S302, the microcomputer 102 operates the ultraviolet light module 104 to apply ultraviolet light to the flash memory wafer 110. Subsequently, the microcomputer 102 operates the probe module 106 to perform the foregoing various operations on the flash memory cells of the flash memory chips of the flash memory wafer 110. In step S304, the first stylization is performed first, and then the first erasing is performed. Step S306 is to perform the above pre-stylization. Step S308 is to perform the above-described word line tolerance simulation or/and bit line tolerance simulation. Step S310 is performed to perform back-bake repair, and the above-mentioned word line tolerance simulation and the flash memory unit with characteristic drift but not damaged in the bit line tolerance simulation are repaired. Step S312 is to perform the above-described soft programming. Step S314 is to perform the above strong erasing. In step S316, the looping stylization and the loop erase mode are performed N times to complete a stylization-erasing loop; N is a number. Step S318 is to implement weak bit filtering, sequentially performing the first stylization of the weak bit screen, the word line pressing of the weak bit screen, the bit line pressing of the weak bit screen, and the weak position. The first stylization of the meta-screening. Step S320 performs the bake-back repair again.

FIG. 4 is a timing diagram illustrating a method of testing a flash memory wafer according to an embodiment of the present invention, including stylized and erased operations of various applied potentials; and the applied intensity is reflected on the vertical axis. As shown in the figure, after the flash memory wafer 110 is irradiated with ultraviolet light (step S302), the flash memory unit is first programmed and then first erased (step S304), and then pre-stylized. (Step S306), the word line tolerance simulation or/and the bit line tolerance simulation is switched again (step S308). After the bake-back repair (step S310), the flash memory unit is soft-programmed (step S312) to reset its electronic characteristics, followed by strong erasing (step S314), followed by The program-erasing process of the N loops is followed (step S316), and the weak bit screen is performed (step S318, including: the first stylized SOP1 of the weak bit screen, the weak bit screen of the SOS label) In addition to the word line pressing mode or/and the bit line pressing of the weak bit screen, and the second stylization of the weak bit screen of the label SOP2, the bake repair is performed (step S320).

As shown in Figure 4, the first stylized, first erased, pre-programmed, and wordline/bitline tolerance simulations can be designed to operate at high temperatures (eg, 90 degrees Celsius). Soft stylization, strong erasure, stylized-erase procedures for N loops, and weak bit screens can be designed to operate at room temperature (eg, 25 degrees Celsius).

The weak bit screen includes the low conductance flash memory grains that have not reached the minimum current at the critical voltage after the SOP1, SOS, and SOP2 operations.

In particular, the stylization-erasing procedure for the N loops in step S316 is not limited to the "stylization" or "erase" operations of the specific control voltage, and may be variously modified. Even the stylized way of using N loops may not be the same, and the erasing methods used for N loops may not be exactly the same. The weak bit screen of step S318 can also be replaced with other weak bit screening schemes different from SOP1, SOS, and SOP2.

While the invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the invention may be made without departing from the spirit and scope of the invention.

102‧‧‧Microcomputer

104‧‧‧UV module

106‧‧‧ Probe Module

108‧‧‧temperature regulator

110‧‧‧Flash Memory Wafer

Claims (12)

A method for testing a flash memory wafer, comprising: performing a control signal line tolerance simulation on a plurality of flash memory dies on a flash memory wafer, which is a flash memory die Tolerance simulation of word lines, or bit lines, or both word lines and bit lines; reprogramming and erasing the flash memory grains with N loops; and performing the above-mentioned control signal lines After the simulation is performed, and before the N loops are repeatedly programmed and the flash memory grains are erased, the flash memory grains are back-baked. The method for testing a flash memory wafer according to claim 1, wherein the control signal line tolerance simulation is performed on the flash memory grains at a first ambient temperature, and is in a The ambient temperature is repeatedly programmed in N loops and erases the flash memory grains, wherein the first ambient temperature is higher than the second ambient temperature. The method for testing a flash memory wafer according to claim 1, comprising: supplying a first line at a word line end and a substrate end of a flash memory unit in the flash memory die a voltage difference, the tolerance of the word line is simulated, wherein the first voltage difference is greater than the word line end applied to the flash memory cell when the flash memory die is erased in the N times of the loop A second voltage difference between the ends of the substrate. The method for testing a flash memory wafer as described in claim 3, wherein: The supply time of the first voltage difference is longer than the second voltage difference. The flash memory wafer testing method of claim 1, comprising: supplying a first stylized potential to a bit line end of a flash memory unit in the flash memory die, Performing bit line tolerance simulation, wherein the first stylized potential is greater than a second applied to the bit line end of the flash memory unit when the flash memory die is programmed in the N times of the loop Stylized potential. The method of testing a flash memory wafer according to claim 5, wherein the first stylized potential is supplied in a plurality of pulse patterns. A flash memory wafer testing machine includes: a probe module; and a microcomputer operating the probe module to perform a control signal on a plurality of flash memory dies on a flash memory wafer Line tolerance simulation, and further operating the probe module to repeatedly program and erase the flash memory grains in N loops, wherein: the above control signal line tolerance simulation is performed, and the above The flash memory grains are back-fired and repaired before the N-turn loops are repeatedly programmed and erased, and the control signal line tolerance simulation is performed on the flash memory. Tolerance simulations are performed on word lines, or bit lines, or word lines and bit lines of bulk grains. Such as the flash memory wafer test machine described in claim 7 of the patent scope, The method includes: a temperature regulator, wherein the microcomputer 1 includes operating the temperature regulator to simulate the control signal line tolerance to be performed at a first ambient temperature, and repeating the N loops and erasing the The flash memory die is subjected to a second ambient temperature, wherein the first ambient temperature is higher than the second ambient temperature. The flash memory wafer testing machine of claim 7, wherein the microcomputer further operates a word of a flash memory unit of the probe module in the flash memory die A first voltage difference is supplied to the line end and a substrate end to simulate the tolerance of the word line; and the first voltage difference is greater than the above-mentioned N times of the ring is applied to the flash memory die a second voltage difference between the word line end of the flash memory unit and the substrate end. The flash memory wafer testing machine of claim 9, wherein: the supply time of the first voltage difference is longer than the second voltage difference. The flash memory wafer testing machine of claim 7, wherein the microcomputer further operates one of the flash memory units of the probe module in the flash memory die. A first stylized potential is supplied to the line terminal for the tolerance of the bit line; and the first stylized potential is greater than the flash memory in the N-th cycle when the flash memory die is programmed a second pass of the bit line end of the unit The potential. The flash memory wafer testing machine of claim 11, wherein the first stylized potential is supplied in a plurality of pulse patterns.