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TWI543283B - 中介基板之製法 - Google Patents

中介基板之製法 Download PDF

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Publication number
TWI543283B
TWI543283B TW103124685A TW103124685A TWI543283B TW I543283 B TWI543283 B TW I543283B TW 103124685 A TW103124685 A TW 103124685A TW 103124685 A TW103124685 A TW 103124685A TW I543283 B TWI543283 B TW I543283B
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Taiwan
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interposer
substrate
wafer
carrier
substrate body
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TW103124685A
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TW201604978A (zh
Inventor
林孟諺
吳文寬
葉煜岑
袁宗德
盧俊宏
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矽品精密工業股份有限公司
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Priority to TW103124685A priority Critical patent/TWI543283B/zh
Priority to CN201410368337.8A priority patent/CN105261568B/zh
Priority to US14/744,464 priority patent/US9515048B2/en
Publication of TW201604978A publication Critical patent/TW201604978A/zh
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Publication of TWI543283B publication Critical patent/TWI543283B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

中介基板之製法
本發明係有關一種半導體封裝件，尤指一種提高製作良率之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)或多晶片模組封裝(Multi-Chip Module,MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知3D晶片堆疊之半導體封裝件之製法之剖面示意圖。如第1圖所示，提供一矽中介板(Through Silicon interposer,TSI)1，該矽中介板1具有相對之置晶側10a與轉接側10b、及連通該置晶側10a與轉接側10b之複數導電矽穿孔(Through-silicon via,TSV)100，且該轉接側10b上具有一線路重佈結構(Redistribution layer,RDL)101。將間距較小之半導體晶片9之電極墊90係藉由複數銲錫凸塊102電性結合至該置晶側10a上，再以底 膠92包覆該些銲錫凸塊102，且形成封裝膠體8於該矽中介板1上，以覆蓋該半導體晶片9。於該線路重佈結構101上藉由複數如凸塊之導電元件103電性結合間距較大之封裝基板7之銲墊70，並以底膠72包覆該些導電元件103。
第1A至1F圖係為習知矽中介板之製法之示意圖。
如第1A圖所示，提供一已完成佈線製程而尚未切割之晶圓10，其係由複數如第1F圖所示之矽中介板1所構成(其詳細內部結構可參考第1F圖)，且該晶圓10之置晶側10a上覆蓋有一支撐件11之保護層110，使該些銲錫凸塊102埋設於該保護層110中。
如第1B圖所示，將該晶圓10以其轉接側10b結合至一第一承載件12之第一膠膜120上，使該些導電元件103埋設於該第一膠膜120中。
如第1C圖所示，移除該支撐件11及其保護層110，以外露該置晶側10a。
如第1C-1圖所示，於該第一膠膜120上進行預切割製程，以產生複數V形預切割道121於該第一膠膜120上。
如第1C-2圖所示，以一機械手臂5固定(如真空吸附)該晶圓10之置晶側10a。
如第1C-3圖所示，翻轉倒置整體結構，再移除該機械手臂5。接著，利用預切割道121進行定位，使整體結構以該置晶側10a固定於定位板4上，再固化該第一膠膜120。
如第1C-4圖所示，以另一機械手臂5’固定(如真空 吸附)該第一承載件12。
如第1C-5圖所示，移除該定位板4，再將第二承載件13之第二膠膜130結合至該晶圓10之置晶側10a，使該些銲錫凸塊102埋設於該第二膠膜130中。
如第1D圖所示，移除該另一機械手臂5’與第一承載件12，且藉由該預切割道121移除該第一膠膜120。
如第1E圖所示，進行切單作業，以於該晶圓10之轉接側10b上藉由雷射機6進行隱形切割(Stealth Dicing，簡稱SD)製程。
如第1F圖所示，以機械手臂(圖略)取出各該矽中介板1。
目前製作該矽中介板1，於晶圓10進行雷射切單時，因該置晶側10a具有特殊佈線而令雷射無法穿透，故於移除該支撐件11及其保護層110後，需先經過重置(remount)作業，即將第二承載件13之第二膠膜130結合至該晶圓10之置晶側10a，使該轉接側10b朝上，再進行切割。
惟，前述習知矽中介板1之製法中，由於先將該晶圓10以其轉接側10b結合至一第一承載件12之第一膠膜120上，再移除該支撐件11及其保護層110，故於進行切單製程前，需進行重置作業，因而第1C圖至第1D圖的過程極為複雜，即需經過許多步驟(如第1C-1至1C-5圖所示)，導致於第1C-2圖所示之製程、第1C-3圖之翻轉倒置及定位步驟將產生破損(crack)(因晶圓10之厚度僅100um) 或掉落之風險、或於第1D圖之移除該第一膠膜120時，將產生該第二膠膜130脫落(peeling)之風險，以致於製造良率下降，因而增加產品成本。
再者，第1C圖至第1D圖之步驟繁多，將降低產量(throughput)，而難以降低產品成本。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種中介基板之製法，係包括：提供一基板本體，該基板本體具有相對之置晶側與轉接側、及連通該置晶側與轉接側之導電穿孔，且該置晶側上覆蓋有一保護層；於該基板本體之轉接側上進行切單製程；將該基板本體以其轉接側結合至一承載件上；移除該保護層；以及移除該承載件，以取得複數該中介基板。
前述之製法中，該基板本體係為半導體板體。
前述之製法中，該基板本體係為晶圓型式。
前述之製法中，該中介基板係為晶片型式。
前述之製法中，該中介基板之轉接側係用以電性結合封裝基板，該置晶側係用以電性結合晶片。
另外，前述之製法中，該切單製程係為隱形切割製程。
由上可知，本發明之中介基板之製法，藉由先進行切單製程，再移除該保護層，以省略習知重置作業，故能避免習知技術之破裂、掉落或脫落之風險，以提高產品之良 率。
再者，本發明省略習知重置作業，故能節省製程時間及購買機台之成本，因而能提高製程效率。
又，本發明省略習知重置作業，因而能減少該基板本體於生產線上傳送時所造成之產品損壞問題。
另外，本發明省略習知重置作業，能避免該基板本體因該第二膠膜脫落而造成產品損壞之問題。
1‧‧‧矽中介板
10‧‧‧晶圓
10a,20a‧‧‧置晶側
10b,20b‧‧‧轉接側
100‧‧‧導電矽穿孔
101,201‧‧‧線路重佈結構
102,202‧‧‧銲錫凸塊
103,203‧‧‧導電元件
11,21‧‧‧支撐件
110,210‧‧‧保護層
12‧‧‧第一承載件
120‧‧‧第一膠膜
121‧‧‧預切割道
13‧‧‧第二承載件
130‧‧‧第二膠膜
2‧‧‧中介基板
20‧‧‧基板本體
200‧‧‧導電穿孔
22‧‧‧承載件
220‧‧‧膠膜
4‧‧‧定位板
5,5’‧‧‧機械手臂
6‧‧‧雷射機
7‧‧‧封裝基板
70‧‧‧銲墊
72,92‧‧‧底膠
8‧‧‧封裝膠體
9‧‧‧半導體晶片
90‧‧‧電極墊
第1圖係為習知半導體封裝件之剖面示意圖；第1A至1F圖係為習知矽中介板之製法之剖面示意圖；其中，第1C-1至1C-5圖係為第1C至1D圖之步驟，第1E圖係為立體圖；以及第2A至2E圖係為本發明之中介基板之製法的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術 內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之中介基板2之製法的剖面示意圖。
如第2A圖所示，提供一基板本體20，該基板本體20具有相對之置晶側20a與轉接側20b、及連通該置晶側20a與轉接側20b之導電穿孔200(如第2E圖所示)，且該置晶側20a上覆蓋有一支撐件21之保護層210。
於本實施例中，該基板本體20係為矽晶圓(Si wafer)型式，即尚未切單。具體地，如第2E圖所示，該轉接側20b上具有一線路重佈結構(Redistribution layer,RDL)201與複數設於該線路重佈結構201上之導電元件203、結合至該置晶側20a上之導電穿孔200端面之複數銲錫凸塊202。
再者，該些銲錫凸塊202埋設於該保護層210中。
如第2B圖所示，翻轉整體結構，以於該基板本體20之轉接側20b上進行切單作業。
於本實施例中，該切單作業係藉由雷射機6進行隱形切割。
如第2C圖所示，將該基板本體20以其轉接側20b結合至一承載件22之膠膜220上。
於本實施例中，該些導電元件203埋設於該膠膜220 中。
如第2D圖所示，移除該支撐件21及其保護層210，以外露出該置晶側20a與銲錫凸塊202。
如第2E圖所示，移除該承載件22及其膠膜220，且由於已進行切單作業，故能取得複數該中介基板2。
於本實施例中，該中介基板2係為晶片型式，且作為矽中介板，使該轉接側20b用以電性結合封裝基板(如第1圖所示之封裝基板7)，該置晶側20a用以電性結合晶片(如第1圖所示之半導體晶片9)。
綜上所述，本發明之中介基板2之製法，係藉由將該基板本體20先進行切單作業，再移除該支撐件21及其保護層210，故能省略習知重置作業(即第1C-5圖所示之第二承載件13之第二膠膜130結合至該晶圓10之置晶側10a)，以節省成本與時間，且能省略習知技術需經多個製程步驟所造成之風險。
再者，本發明之中介基板2之製法省略習知重置作業，故能節省製程時間，並能避免習知技術降低製程良率之問題，故能產量，以降低產品成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
20‧‧‧基板本體
20b‧‧‧轉接側
21‧‧‧支撐件
210‧‧‧保護層
6‧‧‧雷射機

Claims (5)

  1. 一種中介基板之製法，係包括：提供一基板本體，該基板本體具有相對之置晶側與轉接側、及連通該置晶側與轉接側之導電穿孔，該轉接側係用以電性結合封裝基板，該置晶側係用以電性結合晶片，且該置晶側上覆蓋有一保護層；於該基板本體之轉接側上進行切單製程；將該基板本體以其轉接側結合至一承載件上；移除該保護層；以及移除該承載件，以取得複數該中介基板。
  2. 如申請專利範圍第1項所述之中介基板之製法，其中，該基板本體係為半導體板體。
  3. 如申請專利範圍第1項所述之中介基板之製法，其中，該基板本體係為晶圓型式。
  4. 如申請專利範圍第1項所述之中介基板之製法，其中，該中介基板係為晶片型式。
  5. 如申請專利範圍第1項所述之中介基板之製法，其中，該切單製程係為隱形切割製程。
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